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81. 发明申请

WO2012057769A1 ZONING DATA TO A VIRTUAL MACHINE 审中-公开
标题翻译：分区数据到虚拟机
公开(公告)号：WO2012057769A1
公开(公告)日：2012-05-03
申请号：PCT/US2010/054540
申请日：2010-10-28
申请人： HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. , MYRAH, Michael G. , NATRAJAN, Balaji
发明人： MYRAH, Michael G. , NATRAJAN, Balaji
IPC分类号： G06F9/455 , G06F15/17 , G06F15/76
CPC分类号： G06F9/45558 , G06F9/45533 , G06F13/4022 , G06F13/4068 , G06F13/4282 , G06F2009/45562 , G06F2009/45579
摘要： In a method [300] to zone data to a virtual machine, support information is exchanged [302] between a physical controller and an expander, the support information comprising an indication of an ability of the physical controller and the expander to support thereon a set of virtual controllers and a set of virtual physical layers (virtual PHYs), respectively. In response to a positive indication sending a list of SAS addresses to the expander, a list of SAS addresses is sent [306] to the expander. Then, a first SAS address of the list of SAS addresses is assigned [308] to a first virtual PHY of the set of virtual PHYs, wherein the assigning is performed by the expander, and wherein the first virtual PHY at an assigned SAS address corresponds to a first virtual controller of the set of virtual controllers.
摘要翻译：在用于将数据区分到虚拟机的方法[300]中，支持信息在物理控制器和扩展器之间交换[302]，所述支持信息包括物理控制器和扩展器在其上支持集合的能力的指示的虚拟控制器和一组虚拟物理层（虚拟PHY）。响应于向扩展器发送SAS地址列表的肯定指示，将SAS地址列表[306]发送到扩展器。然后，将SAS地址列表的第一SAS地址分配给虚拟PHY集合的第一虚拟PHY，其中分配由扩展器执行，并且其中分配的SAS地址处的第一虚拟PHY对应于到该组虚拟控制器的第一虚拟控制器。

82. 发明申请

WO2012040684A2 APPLICATION SCHEDULING IN HETEROGENEOUS MULTIPROCESSOR COMPUTING PLATFORMS 审中-公开
标题翻译：异构多媒体计算机平台中的应用调度
公开(公告)号：WO2012040684A2
公开(公告)日：2012-03-29
申请号：PCT/US2011/053177
申请日：2011-09-24
申请人： INTEL CORPORATION , IYER, Ravishankar , SRINIVASAN, Sadagopan , ZHAO, Li , ILLIKKAL, Rameshkumar G.
发明人： IYER, Ravishankar , SRINIVASAN, Sadagopan , ZHAO, Li , ILLIKKAL, Rameshkumar G.
IPC分类号： G06F15/76 , G06F9/46 , G06F9/06
CPC分类号： G06F9/4881 , G06F9/5027 , G06F11/3409 , G06F11/3433 , G06F12/084 , G06F2201/88 , G06N5/02 , Y02D10/13 , Y02D10/22 , Y02D10/34
摘要： Methods and apparatus to schedule applications in heterogeneous multiprocessor computing platforms are described. In one embodiment, information regarding performance (e.g., execution performance and/or power consumption performance) of a plurality of processor cores of a processor is stored (and tracked) in counters and/or tables. Logic in the processor determines which processor core should execute an application based on the stored information. Other embodiments are also claimed and disclosed.
摘要翻译：描述了在异构多处理器计算平台中调度应用程序的方法和装置。在一个实施例中，处理器的多个处理器核心的性能（例如，执行性能和/或功耗性能）的信息被存储（并被跟踪）在计数器和/或表中。处理器中的逻辑根据存储的信息确定哪个处理器核心应该执行应用程序。还要求和公开其他实施例。

83. 发明申请

WO2012040662A2 PROCESSOR POWER MANAGEMENT BASED ON CLASS AND CONTENT OF INSTRUCTIONS 审中-公开
标题翻译：基于指令级别和内容的处理器电源管理
公开(公告)号：WO2012040662A2
公开(公告)日：2012-03-29
申请号：PCT/US2011/053147
申请日：2011-09-23
申请人： INTEL CORPORATION , MADDURI, Venkateswara R. , TONG, Jonathan Y. , CHEONG, Hoichi
发明人： MADDURI, Venkateswara R. , TONG, Jonathan Y. , CHEONG, Hoichi
IPC分类号： G06F1/04 , G06F1/32 , G06F9/30 , G06F15/76
CPC分类号： G06F9/3822 , G06F1/3237 , G06F1/3287 , G06F9/3017 , G06F9/382 , G06F9/3869 , G06F9/3889 , Y02D10/128
摘要： A processor and method are disclosed. In one embodiment the processor includes a prefetch buffer that stores macro instructions. The processor also includes a clock circuit that can provide a clock signal for at least some of the functional units within the processor. The processor additionally includes macro instruction decode logic that can determine a class of each macro instruction. The processor also includes a clock management unit that can cause the clock signal to remain in a steady state entering at least one of the units in the processor that do not operate on a current macro instruction being decoded. Finally, the processor also includes at least one instruction decoder unit that can decode the first macro instruction into one or more opcodes.
摘要翻译：公开了一种处理器和方法。在一个实施例中，处理器包括存储宏指令的预取缓冲器。处理器还包括时钟电路，其可以为处理器内的至少一些功能单元提供时钟信号。处理器还包括宏指令解码逻辑，其可以确定每个宏指令的类别。该处理器还包括时钟管理单元，该时钟管理单元可以使得时钟信号保持在稳定状态，进入处理器中的不依赖于正被解码的当前宏指令进行操作的至少一个单元。最后，处理器还包括至少一个指令解码器单元，其可以将第一宏指令解码成一个或多个操作码。

84. 发明申请

WO2012040545A3 FUNCTIONAL UNIT FOR VECTOR INTEGER MULTIPLY ADD INSTRUCTION 审中-公开
公开(公告)号：WO2012040545A3
公开(公告)日：2012-03-29
申请号：PCT/US2011/052899
申请日：2011-09-23
申请人： INTEL CORPORATION , WIEDEMEIER, Jeff , SAMUDRALA, Sridhar , GOLLIVER, Roger
发明人： WIEDEMEIER, Jeff , SAMUDRALA, Sridhar , GOLLIVER, Roger
IPC分类号： G06F15/76 , G06F7/00 , G06F9/30
摘要： A vector functional unit implemented on a semiconductor chip to perform vector operations of dimension N is described. The vector functional unit includes N functional units. Each of the N functional units have logic circuitry to perform: a first integer multiply add instruction that presents highest ordered bits but not lowest ordered bits of a first integer multiply add calculation, and, a second integer multiply add instruction that presents lowest ordered bits but not highest ordered bits of a second integer multiply add calculation.

85. 发明申请

WO2012040545A2 FUNCTIONAL UNIT FOR VECTOR INTEGER MULTIPLY ADD INSTRUCTION 审中-公开
标题翻译：向量整数倍数加法指令的功能单元
公开(公告)号：WO2012040545A2
公开(公告)日：2012-03-29
申请号：PCT/US2011052899
申请日：2011-09-23
申请人： INTEL CORP , WIEDEMEIER JEFF , SAMUDRALA SRIDHAR , GOLLIVER ROGER
发明人： WIEDEMEIER JEFF , SAMUDRALA SRIDHAR , GOLLIVER ROGER
IPC分类号： G06F15/76 , G06F7/00 , G06F9/30
CPC分类号： G06F7/483 , G06F7/5443 , G06F9/30014 , G06F9/30018 , G06F9/30036
摘要： A vector functional unit implemented on a semiconductor chip to perform vector operations of dimension N is described. The vector functional unit includes N functional units. Each of the N functional units have logic circuitry to perform: a first integer multiply add instruction that presents highest ordered bits but not lowest ordered bits of a first integer multiply add calculation, and, a second integer multiply add instruction that presents lowest ordered bits but not highest ordered bits of a second integer multiply add calculation.
摘要翻译：描述在半导体芯片上实现的用于执行维度N的矢量运算的矢量功能单元。矢量功能单元包括N个功能单元。 N个功能单元中的每一个具有执行以下操作的逻辑电路：第一整数乘加指令，其呈现最高有序位但不是第一整数乘加计算的最低有序位;以及第二整数乘加指令，其呈现最低有序位，但是而不是第二整数乘加计算的最高有序位。

86. 发明申请

WO2011041047A3 HOME AGENT DATA AND MEMORY MANAGEMENT 审中-公开
标题翻译：家庭代理数据和内存管理
公开(公告)号：WO2011041047A3
公开(公告)日：2011-06-23
申请号：PCT/US2010046658
申请日：2010-08-25
申请人： INTEL CORP , KUMAR GANESH , DELANO ERIC , NAGARAJ DHEEMANTH , AVERILL GREGORY S , FREYTAG VINCENT R
发明人： KUMAR GANESH , DELANO ERIC , NAGARAJ DHEEMANTH , AVERILL GREGORY S , FREYTAG VINCENT R
IPC分类号： G06F15/16 , G06F11/22 , G06F12/08 , G06F15/76
CPC分类号： G06F12/0817
摘要： Methods and apparatus relating to home agent data and memory management are described. In one embodiment, a scrubber logic corrects an error at a location in a memory corresponding to a target address by writing back the corrected version of data to the target location. In an embodiment, a map out logic maps out an index or way of a directory cache in response to a number of errors, corresponding to the directory cache, exceeding a threshold value. Other embodiments are also disclosed.
摘要翻译：描述与归属代理数据和存储器管理有关的方法和装置。在一个实施例中，洗涤器逻辑通过将校正的数据版本写回到目标位置来校正与目标地址相对应的存储器中的位置处的错误。在一个实施例中，映射逻辑响应于对应于目录高速缓存的多个错误超过阈值来映射目录高速缓存的索引或方式。还公开了其他实施例。

87. 发明申请

WO2011041047A2 HOME AGENT DATA AND MEMORY MANAGEMENT 审中-公开
标题翻译：主页代理数据和内存管理
公开(公告)号：WO2011041047A2
公开(公告)日：2011-04-07
申请号：PCT/US2010/046658
申请日：2010-08-25
申请人： INTEL CORPORATION , KUMAR, Ganesh , DELANO, Eric , NAGARAJ, Dheemanth , AVERILL, Gregory S. , FREYTAG, Vincent R.
发明人： KUMAR, Ganesh , DELANO, Eric , NAGARAJ, Dheemanth , AVERILL, Gregory S. , FREYTAG, Vincent R.
IPC分类号： G06F15/16 , G06F12/08 , G06F11/22 , G06F15/76
CPC分类号： G06F12/0817
摘要： Methods and apparatus relating to home agent data and memory management are described. In one embodiment, a scrubber logic corrects an error at a location in a memory corresponding to a target address by writing back the corrected version of data to the target location. In an embodiment, a map out logic maps out an index or way of a directory cache in response to a number of errors, corresponding to the directory cache, exceeding a threshold value. Other embodiments are also disclosed.
摘要翻译：描述与归属代理数据和存储器管理有关的方法和设备。在一个实施例中，擦除器逻辑通过将修正版本的数据写回到目标位置来纠正与目标地址对应的存储器中的位置处的错误。在一个实施例中，响应于对应于目录高速缓存的多个错误，映射出逻辑映射出目录高速缓存的索引或方式超过阈值。其他实施例也被公开。

88. 发明申请

WO2010126679A2 EMBEDDED DIGITAL IP STRIP CHIP 审中-公开
标题翻译：嵌入式数字IP条带芯片
公开(公告)号：WO2010126679A2
公开(公告)日：2010-11-04
申请号：PCT/US2010/029860
申请日：2010-04-02
申请人： ALTERA CORPORATION , WORTMAN, Curt , LEE, Chong, H. , CLIFF, Richard, G.
发明人： WORTMAN, Curt , LEE, Chong, H. , CLIFF, Richard, G.
IPC分类号： G11C7/00 , G11C5/02 , G06F15/76
CPC分类号： G06F17/5045 , G06F2217/84 , H03K19/17724 , H03K19/17732
摘要： An integrated circuit (IC) is provided. The IC includes a first region having an array of programmable logic cells. The IC also includes a second region incorporated into the IC and in communication with the first region. The second region includes standard logic cells and base cells. In one embodiment, the standard logic cells are assembled or interconnected to accommodate known protocols. The base cells include configurable logic to adapt to modifications to emerging communication protocols, which are supported by the base cells. The second region can be embedded in the first region in one embodiment. In another embodiment, the second region is defined around a perimeter of the first region. The configurable logic may be composed of hybrid logic elements that have metal mask programmable interconnections so that as emerging communication protocols evolve and are modified, the IC can be modified to accommodate to the changes in the protocol. In another embodiment, a generic device can be customized by replacing the original function with a completely new function targeting a specific application space, e.g., replacing the original function such as a PCI Express, used for computing based applications, with 4OG /10OG Ethernet and Interlaken, used in wireline applications. A method of designing an integrated circuit is also provided.
摘要翻译：提供集成电路（IC）。 IC包括具有可编程逻辑单元阵列的第一区域。 IC还包括结合到IC中并与第一区域通信的第二区域。第二区包括标准逻辑单元和基本单元。在一个实施例中，标准逻辑单元被组合或互连以适应已知协议。基本单元包括可配置逻辑以适应由基本单元支持的新兴通信协议的修改。在一个实施例中，第二区域可以嵌入第一区域。在另一个实施例中，第二区域围绕第一区域的周边限定。可配置逻辑可以由具有金属掩模可编程互连的混合逻辑元件组成，使得随着新兴通信协议的发展和修改，可以修改IC以适应协议的改变。在另一个实施例中，可以通过用针对特定应用空间的全新功能替换原始功能来定制通用设备，例如用4OG / 10OG以太网替换用于基于计算的应用的诸如PCI Express的原始功能，例如PCI Express，因特拉肯，用于有线应用。还提供了一种设计集成电路的方法。

89. 发明申请

WO2010120444A2 CLOUD COMPUTING FOR A MANUFACTURING EXECUTION SYSTEM 审中-公开
标题翻译：制造执行系统的云计算
公开(公告)号：WO2010120444A2
公开(公告)日：2010-10-21
申请号：PCT/US2010/028222
申请日：2010-03-23
申请人： HONEYWELL INTERNATIONAL INC. , MCLAUGHLIN, Paul, F. , DUCA, Andrew , BURD, Matthew, G.
发明人： MCLAUGHLIN, Paul, F. , DUCA, Andrew , BURD, Matthew, G.
IPC分类号： G06F15/16 , G06F15/76
CPC分类号： G06Q50/04 , G05B19/4183 , G05B2219/31282 , G06Q10/06 , H04L67/10 , H04L67/12 , Y02P90/10 , Y02P90/12 , Y02P90/30 , Y02P90/86
摘要： A computing cloud system includes at least one data storage unit (112, 602-606) configured to store information associated with at least one manufacturing execution system. The computing cloud system also includes at least one processing unit (110, 612) configured to execute instructions associated with the at least one manufacturing execution system and at least one communications interface (610) configured to receive information from the at least one manufacturing site and to interpret the information.
摘要翻译：计算云系统包括被配置为存储与至少一个制造执行系统相关联的信息的至少一个数据存储单元（112,602-606）。计算云系统还包括被配置为执行与至少一个制造执行系统相关联的指令的至少一个处理单元（110,612）以及被配置为从至少一个制造站点接收信息的至少一个通信接口（610）来解释信息。

90. 发明申请

WO2010111249A3 SYSTEM AND METHOD FOR ACHIEVING IMPROVED ACCURACY FROM EFFICIENT COMPUTER ARCHITECTURES 审中-公开
公开(公告)号：WO2010111249A3
公开(公告)日：2010-09-30
申请号：PCT/US2010/028279
申请日：2010-03-23
申请人： COGNITIVE ELECTRONICS, INC. , FELCH, Andrew, C. , GRANGER, Richard, H., Jr.
发明人： FELCH, Andrew, C. , GRANGER, Richard, H., Jr.
IPC分类号： G06F15/00 , G06F15/76
摘要： In a method and equipment for continuous sintering of pelletized mineral material, a partition wall (7, 8) arranged between two adjacent cooling chambers (4, 5; 5, 6) is in the height direction placed at a distance from the pellet bed (2), so that in between the partition wall (7, 8) and pellet bed (2), there is left a gap (s) that allows gas to flow between two adjacent cooling chambers (4, 5; 5; 6) through the gap (s) in order to equalize the pressure between the cooling chambers.

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