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81. 发明申请

WO2012109161A3 APPARATUS AND METHODS FOR ENVELOPE TRACKING CALIBRATION 审中-公开
标题翻译：用于包围跟踪校准的装置和方法
公开(公告)号：WO2012109161A3
公开(公告)日：2012-11-15
申请号：PCT/US2012024019
申请日：2012-02-06
申请人： SKYWORKS SOLUTIONS INC , NUJIRA LTD , RIPLEY DAVID STEVEN , KHESBAK SABAH , BARTRAM BENJAMIN , COBLEY KEVIN LEE , HENSHAW ROBERT ASTLE , HILDERSLEY JULIAN , THOMPSON ROBERT JOHN
发明人： RIPLEY DAVID STEVEN , KHESBAK SABAH , BARTRAM BENJAMIN , COBLEY KEVIN LEE , HENSHAW ROBERT ASTLE , HILDERSLEY JULIAN , THOMPSON ROBERT JOHN
IPC分类号： H03F3/20 , H03F3/24
CPC分类号： H04B17/13 , H03F1/0211 , H03F1/0216 , H03F1/0222 , H03F1/0227 , H03F1/025 , H03F1/30 , H03F1/301 , H03F1/32 , H03F1/56 , H03F3/19 , H03F3/193 , H03F3/21 , H03F3/211 , H03F3/245 , H03F3/68 , H03F3/72 , H03F2200/102 , H03F2200/108 , H03F2200/111 , H03F2200/15 , H03F2200/387 , H03F2200/405 , H03F2200/429 , H03F2200/451 , H03F2200/462 , H03F2200/465 , H03F2200/471 , H03F2200/507 , H03F2200/511 , H03F2203/21106 , H03G3/30 , H03G3/3036 , H03G3/3042 , H04B1/40 , H04W88/02
摘要： Apparatus and methods for envelope tracking calibration are provided. In one embodiment, a method of calibrating an envelope tracker having an envelope shaping table generated at a desired gain compression of a power amplifier is provided. The method includes generating a supply voltage for the power amplifier using the envelope tracker, operating the supply voltage of the power amplifier at a first voltage level associated with substantially no gain compression of the power amplifier, and measuring an output power of the power amplifier at the first voltage level. The method further includes decreasing a voltage level of the supply voltage one or more times and measuring the output power at each voltage level, determining a second voltage level of the power amplifier associated with a gain compression equal to about that of the desired gain compression, and calibrating the envelope tracker based on the determination.
摘要翻译：提供用于包络跟踪校准的装置和方法。在一个实施例中，提供了一种校准具有在功率放大器的期望增益压缩下产生的包络整形表的包络跟踪器的方法。该方法包括使用包络跟踪器产生用于功率放大器的电源电压，在与功率放大器基本上没有增益压缩相关联的第一电压电平下操作功率放大器的电源电压，以及测量功率放大器的输出功率第一个电压电平。该方法进一步包括将电源电压的电压电平降低一次或多次，并测量每个电压电平处的输出功率，确定与等于期望增益压缩的增益压缩相关联的增益压缩相关联的功率放大器的第二电压电平，并根据确定校准包络跟踪器。

82. 发明申请

WO2012097035A1 A BUFFER TO DRIVE REFERENCE VOLTAGE 审中-公开
标题翻译：驱动参考电压的缓冲器
公开(公告)号：WO2012097035A1
公开(公告)日：2012-07-19
申请号：PCT/US2012/020889
申请日：2012-01-11
申请人： ANALOG DEVICES, INC. , WAKIMOTO, Tsutomu
发明人： WAKIMOTO, Tsutomu
IPC分类号： H03F1/34
CPC分类号： H03F3/345 , G05F1/56 , H03F1/301 , H03F1/342 , H03F2200/405
摘要： Embodiments of the present invention may provide an integrated circuit that may comprise a first transistor to receive an input voltage signal at its gate and generate an output voltage signal at its drain. Further, the integrated circuit may comprise a second transistor to form an active load of the first transistor, the second transistor may have its drain and gate coupled to the drain of the first transistor. In addition, the integrated circuit may comprise a third transistor to form a current mirror with the second transistor, a fourth transistor to form an active load of the third transistor, and a fifth transistor to form a current mirror with the fourth transistor. The fifth transistor may be connected to the drain of the second transistor. The integrated circuit may form an amplifier and Gm stage of a reference buffer.
摘要翻译：本发明的实施例可以提供一种集成电路，其可以包括第一晶体管，以在其栅极处接收输入电压信号并在其漏极处产生输出电压信号。此外，集成电路可以包括形成第一晶体管的有源负载的第二晶体管，第二晶体管可以使其漏极和栅极耦合到第一晶体管的漏极。此外，集成电路可以包括与第二晶体管形成电流镜的第三晶体管，形成第三晶体管的有源负载的第四晶体管，以及与第四晶体管形成电流镜的第五晶体管。第五晶体管可以连接到第二晶体管的漏极。集成电路可以形成参考缓冲器的放大器和Gm级。

83. 发明申请

WO2011022551A1 STACKED AMPLIFIER WITH DIODE-BASED BIASING 审中-公开
标题翻译：基于二极管偏置的堆叠放大器
公开(公告)号：WO2011022551A1
公开(公告)日：2011-02-24
申请号：PCT/US2010/046023
申请日：2010-08-19
申请人： QUALCOMM INCORPORATED , ZHAO, Yu , PLETCHER, Nathan M.
发明人： ZHAO, Yu , PLETCHER, Nathan M.
IPC分类号： H03F1/02 , H03F1/30 , H03F3/189
CPC分类号： H03F1/0283 , H03F1/301 , H03F3/189
摘要： Techniques for improving linearity of amplifiers are described. In an exemplary design, an amplifier (e.g., a power amplifier) may include a plurality of transistors coupled in a stack and at least one diode. The plurality of transistors may receive and amplify an input signal and provide an output signal. The at least one diode may be operatively coupled to at least one transistor in the stack. Each diode may provide a variable bias voltage to an associated transistor in the stack. Each diode may have a lower voltage drop across the diode at high input power and may provide a higher bias voltage to the associated transistor at high input power. The at least one transistor may have higher gain at high input power due to the higher bias voltage from the at least one diode. The higher gain may improve the linearity of the amplifier.
摘要翻译：描述了用于提高放大器线性度的技术。在示例性设计中，放大器（例如，功率放大器）可以包括耦合在堆叠中的多个晶体管和至少一个二极管。多个晶体管可以接收和放大输入信号并提供输出信号。至少一个二极管可以可操作地耦合到堆叠中的至少一个晶体管。每个二极管可以向堆叠中的相关联的晶体管提供可变偏置电压。每个二极管可以在高输入功率下在二极管上具有较低的电压降，并且可以在高输入功率下向相关联的晶体管提供更高的偏置电压。由于来自至少一个二极管的较高偏置电压，至少一个晶体管可能在高输入功率下具有更高的增益。较高的增益可以提高放大器的线性度。

84. 发明申请

WO2007088363A1 POWER AMPLIFIER WITH DIGITAL PRE-DISTORSION 审中-公开
标题翻译：带数字预失真的功率放大器
公开(公告)号：WO2007088363A1
公开(公告)日：2007-08-09
申请号：PCT/GB2007/000337
申请日：2007-02-01
申请人： FILTRONIC PLC , RHODES, John, David
发明人： RHODES, John, David
IPC分类号： H03F1/32 , H03F3/20
CPC分类号： H03F3/245 , H03F1/301 , H03F1/3205 , H03F1/3241 , H03F1/56 , H03F3/193 , H03F2200/15 , H03F2200/387 , H03F2200/451 , H03F2201/3224
摘要： A power amplifier using a digitally pre-distorted compound semiconductor transistor is discussed. The amplifier has improved linearity. For a given gate bias voltage, there exists a drain voltage at which the drain current is the same for a pulsed signal as for a DC signal and is invariant to quiescent bias points occurring when a pulsed signal is applied. If an amplifier operates at this point, the trapping effects that lead to memory effects do not affect the dynamic behaviour of a digitally pre-distorted amplifier, resulting in improved linearity. The existence of this point, and it' s benefits to the linearity of a digitally pre-distorted amplifier, have not been previously recognised.
摘要翻译：讨论了使用数字预失真化合物半导体晶体管的功率放大器。放大器具有提高的线性度。对于给定的栅极偏置电压，存在漏极电压，对于脉冲信号，漏极电流对于DC信号是相同的，并且对于施加脉冲信号时发生的静态偏置点是不变的。如果此时放大器工作，则导致记忆效应的捕获效应不会影响数字预失真放大器的动态特性，从而提高线性度。这一点的存在，并且它对数字预失真放大器的线性有好处，以前没有被认可。

85. 发明申请

WO2007064201A1 AMPLIFIER WITH COMPENSATED GATE BIAS 审中-公开
标题翻译：具有补偿门偏置的放大器
公开(公告)号：WO2007064201A1
公开(公告)日：2007-06-07
申请号：PCT/NL2006/000608
申请日：2006-12-04
申请人： NEDERLANDSE ORGANISATIE VOOR TOEGEPAST-NATUURWETENSCHAPPELIJK ONDERZOEK TNO , BUSKING, Erik Bert , DE HEK, Andries Peter
发明人： BUSKING, Erik Bert , DE HEK, Andries Peter
IPC分类号： H03F1/30
CPC分类号： H03F1/301 , H03F3/193 , H03F2200/18 , H03F2200/451
摘要： An amplifier circuit has an amplifier stage (10), comprising an amplifier transistor (104) with a gate coupled to an input (100) of the amplifier stage (10), a source coupled to a reference connection (gnd) and a drain coupled to a positive power supply connection (V+). A bias stage (12) is provided comprising a bias transistor (120), a drain resistance (124) and a source resistance (122), the bias transistor (120) having a gate coupled to a negative power supply connection (V-), a source coupled to the negative power supply connection (V-) via the source resistance (122) and a drain coupled to the reference connection (gnd) via the drain resistance (124) and to the gate of the amplifier transistor (104). The bias stage comprises a further resistance (20, 22), coupled from a node between the source of the bias transistor and the source resistance of the bias transistor (120) to a circuit node that carries a voltage higher than the voltage at the negative power supply connection.
摘要翻译：放大器电路具有放大器级（10），其包括放大器晶体管（104），其中栅极耦合到放大器级（10）的输入（100），耦合到参考连接（gnd）和漏耦合到正电源连接（V +）。提供偏置级（12），其包括偏置晶体管（120），漏极电阻（124）和源极电阻（122），偏置晶体管（120）具有耦合到负电源连接（V-）的栅极，，经由源极电阻（122）耦合到负电源连接（V-）的源极和经由漏极电阻（124）和放大器晶体管（104）的栅极耦合到参考连接（gnd）的漏极，。偏置级包括从偏置晶体管的源极和偏置晶体管（120）的源极之间的节点耦合到电路节点的另一个电阻（20,22），该电路节点承载的电压高于负极电源连接。

86. 发明申请

WO2007043122A9 VARIABLE GAIN AMPLIFIER AND ITS CONTROL METHOD 审中-公开
标题翻译：可变增益放大器及其控制方法
公开(公告)号：WO2007043122A9
公开(公告)日：2007-05-31
申请号：PCT/JP2005018181
申请日：2005-09-30
申请人： FUJITSU LTD , ARAI TOMOYUKI
发明人： ARAI TOMOYUKI
IPC分类号： H03G3/10 , H03F1/56
CPC分类号： H03G1/0088 , H03F1/301 , H03F1/3211 , H03F1/56 , H03F3/193 , H03F2200/105 , H03F2200/18 , H03F2200/213 , H03F2200/222 , H03F2200/228 , H03F2200/252 , H03F2200/42 , H03F2200/451 , H03F2200/75 , H03G3/001
摘要： A variable gain amplifier comprises a first amplifier circuit (106), a gate bias control circuit (102), and a variable matching circuit (103). The first amplifier circuit (106) has a first field effect transistor and amplifies and outputs a signal received by the gate of the first field effect transistor. The gate bias control circuit (102) controls the gain of the first amplifier circuit by controlling the gate bias of the first amplifier circuit. The variable matching circuit (103) controls the gain of the first amplifier circuit by controlling a capacitor connected to the gate of the first amplifier circuit.
摘要翻译：可变增益放大器包括第一放大器电路（106），栅极偏置控制电路（102）和可变匹配电路（103）。第一放大器电路（106）具有第一场效应晶体管，并放大并输出由第一场效应晶体管的栅极接收的信号。栅极偏置控制电路（102）通过控制第一放大器电路的栅极偏置来控制第一放大器电路的增益。可变匹配电路（103）通过控制连接到第一放大器电路的栅极的电容来控制第一放大器电路的增益。

87. 发明申请

WO2007016045A1 DISTRIBUTED TRANSISTOR STRUCTURE FOR HIGH LINEARITY ACTIVE CATV POWER SPLITTER 审中-公开
标题翻译：高分辨率有源CATV功率分配器的分布式晶体管结构
公开(公告)号：WO2007016045A1
公开(公告)日：2007-02-08
申请号：PCT/US2006/028716
申请日：2006-07-24
申请人： ANALOG DEVICES, INC. , ZHANG, Shuyun , ZHAO, Yibing
发明人： ZHANG, Shuyun , ZHAO, Yibing
IPC分类号： H03F1/32
CPC分类号： H03F3/193 , H03F1/301 , H03F1/3205 , H03F3/195 , H03F3/345 , H03F2200/63
摘要： A transistor cell includes a first stage comprising a first transistor that is coupled to a RC filter arrangement. A second stage has a second transistor that is coupled to the first stage. The linearity of the transistor cell is improved by shifting the DC bias point so that the first stage is biased at a high quiescent current while the second stage is biased at a low quiescent current.
摘要翻译：晶体管单元包括第一级，其包括耦合到RC滤波器装置的第一晶体管。第二级具有耦合到第一级的第二晶体管。通过移动DC偏置点来改善晶体管单元的线性，使得第一级被偏置在高静态电流，而第二级被偏置在低静态电流。

88. 发明申请

WO2006077909A1 定電流回路、それを用いた電源装置および発光装置审中-公开
标题翻译：恒定电流电路，发光装置和使用恒流电路的电源装置
公开(公告)号：WO2006077909A1
公开(公告)日：2006-07-27
申请号：PCT/JP2006/300699
申请日：2006-01-19
申请人：ローム株式会社 , 千田泰輔
发明人：千田泰輔
IPC分类号： G05F3/24
CPC分类号： G05F1/563 , H03F1/301 , H03F2200/18 , H03F2200/78
摘要： A constant current circuit capable of operating on a low voltage. In a constant current circuit (200) for supplying a constant current to a circuit connected to a current output terminal (102) of the constant current circuit (200), a first transistor (M1) is disposed on a current path of the constant current. A second transistor (M2) is connected to the first transistor (M1) in such a manner that their gate terminals, which serve as the respective control terminals, are commonly connected. A first current/voltage converting part (14) converts the current flowing through the second transistor (M2) and through a third transistor (M3) to a voltage. A constant current source (10) generates a reference current. A second current/voltage converting part (16) converts the reference current to a voltage. A first error amplifier (12), to which the voltages of the first and second current/voltage converting parts (14,16) are inputted, adjusts the gate voltages of the first and second transistors (M1,M2). A voltage adjusting part (20) adjusts the voltage at the gate terminal of the third transistor (M3) such that the voltage (Vd2) at an end of the second transistor (M2) gets close to the predetermined reference voltage.
摘要翻译：能够在低电压下工作的恒流电路。在用于向与恒流电路（200）的电流输出端（102）连接的电路供给恒定电流的恒流电路（200）中，第一晶体管（M1）设置在恒流电流路径上。第二晶体管（M2）以这样的方式连接到第一晶体管（M1），使得它们作为各个控制端子的栅极端子共同连接。第一电流/电压转换部件（14）将流过第二晶体管（M2）的电流和通过第三晶体管（M3）转换成电压。恒流源（10）产生参考电流。第二电流/电压转换部分（16）将参考电流转换成电压。输入第一和第二电流/电压转换部分（14,16）的电压的第一误差放大器（12）调节第一和第二晶体管（M1，M2）的栅极电压。电压调节部（20）调整第三晶体管（M3）的栅极端的电压，使得第二晶体管（M2）的端部的电压（Vd2）接近预定的基准电压。

89. 发明申请

WO2005104355A1 METHOD AND APPARATUS FOR DOHERTY AMPLIFIER BIASING 审中-公开
标题翻译： DOHERTY放大器偏置的方法和装置
公开(公告)号：WO2005104355A1
公开(公告)日：2005-11-03
申请号：PCT/US2005/002494
申请日：2005-01-26
申请人： FREESCALE SEMICONDUCTOR, INC. , KRVAVAC, Enver , MITZLAFF, James, E. , VAN HORN, Mark, I.
发明人： KRVAVAC, Enver , MITZLAFF, James, E. , VAN HORN, Mark, I.
IPC分类号： H03F3/04
CPC分类号： H03F1/0288 , H03F1/301 , H03F3/04 , H03F2200/18 , H03F2200/366 , H03F2200/75
摘要： Apparatus and methods are described for biasing amplifiers with multiple outputs. A semiconductor die (100) may include a reference Field Effect Transistor (FET) (112) integrated on the semiconductor die and coupled to an amplifier (116) integrated on the semiconductor die. A voltage offset circuit (114) may also be integrated on the semiconductor die (100) for determining the voltage needed to operate the amplifier (116).
摘要翻译：描述用于具有多个输出的偏置放大器的装置和方法。半导体管芯（100）可以包括集成在半导体管芯上并耦合到集成在半导体管芯上的放大器（116）的参考场效应晶体管（FET）（112）。电压偏移电路（114）也可以集成在半导体管芯（100）上，用于确定操作放大器（116）所需的电压。

90. 发明申请

WO2005069097A1 TRANSISTORANORDNUNG MIT TEMPERATURKOMPENSATION UND VERFAHREN ZUR TEMPERATURKOMPENSATION 审中-公开
标题翻译：带温度补偿温度补偿和方法的晶体管装置
公开(公告)号：WO2005069097A1
公开(公告)日：2005-07-28
申请号：PCT/DE2005/000020
申请日：2005-01-11
申请人： INFINEON TECHNOLOGIES AG , OEHM, Jürgen
发明人： OEHM, Jürgen
IPC分类号： G05F3/26
CPC分类号： H03F3/45183 , H03F1/301 , H03F2200/447
摘要： Es ist eine Transistoranordnung mit Temperaturkompensation angegeben, bei der ein Transistor (1) zumindest einen einstellbaren Geometrieparameter aufweist. Ein Mittel zur Temperaturmessung (15) gibt ein temperaturabhängiges Signal ab, in dessen Abhängigkeit eine Steuereinheit (2) den Geometrieparameter des Transistors (1) derart ansteuert, daß dessen elektrische Kenngrößen temperaturunabhängig sind. Der einstellbare Geometrieparameter ist bevorzugt die Kanalweite des Transistors (1).
摘要翻译：提供了一种具有温度补偿的晶体管装置，其中一个晶体管（1）具有至少一个可调节几何参数。温度测量装置（15）输出一个依赖于温度的信号，据其的控制单元，（2）在晶体管的几何形状的参数（1），使得它的电特性与温度无关。所述可调节的几何形状参数是优选的晶体管（1）的信道宽度。

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