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81. 发明申请

WO2017111954A1 FIN-BASED III-V/SI or GE CMOS SAGE INTEGRATION 审中-公开
标题翻译：基于FIN的III-V / SI或GE CMOS SAGE集成
公开(公告)号：WO2017111954A1
公开(公告)日：2017-06-29
申请号：PCT/US2015/067432
申请日：2015-12-22
申请人： INTEL CORPORATION
发明人： RACHMADY, Willy , METZ, Matthew V. , DEWEY, Gilbert , MOHAPATRA, Chandra S. , KAVALIEROS, Jack T. , MURTHY, Anand S. , GHANI, Tahir
IPC分类号： H01L21/8238
CPC分类号： H01L27/0924 , H01L21/823807 , H01L21/823821 , H01L21/8258
摘要： Embodiments of the invention include a semiconductor structure and a method of making such a structure. In one embodiment, the semiconductor structure comprises a first fin and a second fin formed over a substrate. The first fin may comprise a first semiconductor material and the second fin may comprise a second semiconductor material. In an embodiment, a first cage structure is formed adjacent to the first fin, and a second cage structure is formed adjacent to the second fin. Additionally, embodiments may include a first gate electrode formed over the first fin, where the first cage structure directly contacts the first gate electrode, and a second gate electrode formed over the second fin, where the second cage structure directly contacts the second gate electrode.
摘要翻译：本发明的实施例包括半导体结构和制造这种结构的方法。在一个实施例中，半导体结构包括形成在衬底上的第一鳍和第二鳍。第一鳍状物可以包括第一半导体材料并且第二鳍状物可以包括第二半导体材料。在一个实施例中，第一保持架结构邻近第一鳍形成，并且第二保持架结构邻近第二鳍形成。另外，实施例可以包括形成在第一鳍上方的第一栅电极，其中第一笼结构直接接触第一栅电极，以及第二栅电极形成在第二鳍上方，其中第二笼结构直接接触第二栅电极。

82. 发明申请

WO2017111914A1 LOW BAND GAP SEMICONDUCTOR DEVICES HAVING REDUCED GATE INDUCED DRAIN LEAKAGE (GIDL) AND THEIR METHODS OF FABRICATION 审中-公开
标题翻译：低带隙半导体器件具有栅极泄漏泄漏减少（GIDL）及其制造方法
公开(公告)号：WO2017111914A1
公开(公告)日：2017-06-29
申请号：PCT/US2015/067168
申请日：2015-12-21
申请人： INTEL CORPORATION
发明人： DEWEY, Gilbert , KAVALIEROS, Jack T. , RACHMADY, Willy , METZ, Matthew V. , LE, Van H. , KIM, Seiyon , CHU-KUNG, Benjamin
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/78 , H01L29/775 , H01L29/785
摘要： Embodiments of the present invention are directed to low band gap channel semiconductor devices. In an example, a device includes a first semiconductor material formed above a substrate, the first semiconductor material having a first band gap. A gate dielectric layer is on a surface of the first semiconductor material. A gate electrode is on the gate dielectric layer. A pair of source/drain regions is on opposite sides of the gate electrode. A channel is disposed in the first semiconductor material between the pair of source/drain regions and beneath the gate electrode. The pair of source/drain regions includes a second semiconductor material having a second band gap, and a third semiconductor material having a third band gap. The second semiconductor material is between the first semiconductor material and the third semiconductor material, and the second band gap is greater than the first bandgap.
摘要翻译：本发明的实施例针对低带隙半导体器件。在示例中，器件包括形成在衬底上方的第一半导体材料，第一半导体材料具有第一带隙。栅极介电层位于第一半导体材料的表面上。栅电极在栅极介电层上。一对源极/漏极区位于栅电极的相对侧上。沟道设置在第一半导体材料中位于一对源极/漏极区域之间并且在栅极电极下方。该对源极/漏极区域包括具有第二带隙的第二半导体材料以及具有第三带隙的第三半导体材料。第二半导体材料在第一半导体材料和第三半导体材料之间，并且第二带隙大于第一带隙。

83. 发明申请

WO2017111848A1 TRANSISTOR INCLUDING TENSILE-STRAINED GERMANIUM GERMANIUM CHANNEL 审中-公开
标题翻译：晶体管包括拉伸应变的德国锗通道
公开(公告)号：WO2017111848A1
公开(公告)日：2017-06-29
申请号：PCT/US2015/000414
申请日：2015-12-24
申请人： INTEL CORPORATION
发明人： MOHAPATRA, Chandra, S. , GLASS, Glenn, A. , MURTHY, Anand, S. , JAMBUNATHAN, Karthik , RACHMADY, Willy , DEWEY, Gilbert , GHANI, Tahir , KAVALIEROS, Jack, T.
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/1054 , H01L21/823821 , H01L27/0924 , H01L29/42392 , H01L29/66356 , H01L29/66545 , H01L29/66795 , H01L29/7391 , H01L29/785 , H01L29/78696
摘要： Techniques are disclosed for forming transistor structures including tensile-strained germanium (Ge) channel material. The transistor structures may be used for either or both of n-type and p- type transistor devices, as tensile-strained Ge has very high carrier mobility properties suitable for both types. Thus, a simplified CMOS integration scheme may be achieved by forming n- MOS and p-MOS devices included in the CMOS device using the techniques described herein. In some cases, the tensile-strained Ge may be achieved by epitaxially growing the Ge material on a group III-V material having a lattice constant that is higher than that of Ge and/or by applying a macroscopic 3-point bending to the die on which the transistor is formed. The techniques may be used to form transistors having planar or non-planar configurations, such as finned configurations (e.g., finFET or tri-gate) or gate-all-around (GAA) configurations (including at least one nanowire).
摘要翻译：公开了用于形成包括拉伸应变锗（Ge）沟道材料的晶体管结构的技术。晶体管结构可用于n型和p型晶体管器件中的任一个或两者，因为拉伸应变的Ge具有适用于这两种类型的非常高的载流子迁移率特性。因此，可以通过使用本文描述的技术形成CMOS器件中包括的n-MOS和p-MOS器件来实现简化的CMOS集成方案。在一些情况下，拉伸应变Ge可以通过在晶格常数高于Ge的III-V族材料上外延生长Ge材料和/或通过对模具施加宏观3点弯曲来实现在其上形成晶体管。该技术可以用于形成具有平面或非平面配置的晶体管，诸如翅片配置（例如，finFET或三栅极）或全栅（GAA）配置（包括至少一个纳米线）。

84. 发明申请

WO2017111810A1 LOW SCHOTTKY BARRIER CONTACT STRUCTURE FOR GE NMOS 审中-公开
标题翻译： GE NMOS的低肖特基势垒接触结构
公开(公告)号：WO2017111810A1
公开(公告)日：2017-06-29
申请号：PCT/US2015/000362
申请日：2015-12-24
申请人： INTEL CORPORATION
发明人： RACHMADY, Willy , METZ, Matthew, V. , CHU-KUNG, Benjamin , LE, Van, H. , DEWEY, Gilbert , AGRAWAL, Ashish , KAVALIEROS, Jack, T.
IPC分类号： H01L29/872
CPC分类号： H01L29/78 , H01L21/28255 , H01L29/45 , H01L29/66477
摘要： An apparatus including a substrate; a transistor device on the substrate including a channel and a source and a drain disposed between the channel; a source contact coupled to the source and a drain contact coupled to the drain; and the source and drain each including a composition including a concentration of germanium at an interface with the channel that is greater than a concentration of germanium at a junction with the source contact. A method including defining an area on a substrate for a transistor device; forming a source and a drain each including an interface with the channel; and forming a contact to one of the source and the drain, wherein a composition of each of the source and the drain includes a concentration of germanium at an interface with the channel that is greater than a concentration at a junction with the contact.
摘要翻译：一种包括衬底的设备; 衬底上的晶体管器件，其包括沟道以及设置在沟道之间的源极和漏极; 耦合到所述源极的源极触点和耦合到所述漏极的漏极触点; 并且所述源极和漏极各自包括组分，所述组分包括在与所述沟道的界面处的锗浓度大于在与所述源极触点的连接处的锗浓度。一种方法，包括：在晶体管器件的衬底上定义一个区域; 形成均包括与所述通道的界面的源极和漏极; 以及形成与所述源极和所述漏极中的一个的接触，其中所述源极和所述漏极中的每一个的组成包括在与所述沟道的界面处的锗浓度大于在与所述接触的结处的浓度。 p>

85. 发明申请

WO2017003414A1 LOW DAMAGE SELF-ALIGNED AMPHOTERIC FINFET TIP DOPING 审中-公开
标题翻译：低损耗自对准AMPHOTERIC FINFET TIP DOPING
公开(公告)号：WO2017003414A1
公开(公告)日：2017-01-05
申请号：PCT/US2015/038197
申请日：2015-06-27
申请人： INTEL CORPORATION
发明人： KAVALIEROS, Jack T. , MOHAPATRA, Chandra S. , MURTHY, Anand S. , RACHMADY, Willy , METZ, Matthew V. , DEWEY, Gilbert , GHANI, Tahir , KENNEL, Harold W.
IPC分类号： H01L29/78 , H01L21/336 , H01L21/8238
CPC分类号： H01L27/0924 , H01L21/2258 , H01L21/8258 , H01L29/205 , H01L29/66522 , H01L29/66545 , H01L29/66803
摘要： Monolithic finFETs including a majority carrier channel in a first III-V compound semiconductor material disposed on a second III-V compound semiconductor. While a mask, such as a sacrificial gate stack, is covering the channel region, a source of an amphoteric dopant is deposited over exposed fin sidewalls and diffused into the first III-V compound semiconductor material. The amphoteric dopant preferentially activates as a donor within the first III-V material and an acceptor with the second III-V material, providing transistor tip doping with a p-n junction between the first and second III-V materials. A lateral spacer is deposited to cover the tip portion of the fin. Source/drain regions in regions of the fin not covered by the mask or spacer electrically couple to the channel through the tip region. The channel mask is replaced with a gate stack.
摘要翻译：包括设置在第二III-V族化合物半导体上的第一III-V族化合物半导体材料中的多数载流子通道的单片finFET。虽然诸如牺牲栅极堆叠的掩模覆盖沟道区，但两性掺杂剂的源沉积在暴露的翅片侧壁上并扩散到第一III-V族化合物半导体材料中。两性掺杂剂优选地在第一III-V材料内作为供体激活，并且具有第二III-V材料的受体，从而在第一和第二III-V材料之间提供晶体管尖端掺杂p-n结。沉积横向间隔件以覆盖翅片的尖端部分。未被掩模或间隔物覆盖的鳍的区域中的源极/漏极区域通过尖端区域电耦合到沟道。通道掩码被门堆叠替换。

86. 发明申请

WO2017003408A1 METHOD TO FORM OHMIC CONTACTS TO SEMICONDUCTORS USING QUANTIZED METALS 审中-公开
标题翻译：使用量化金属形成与半导体的OHMIC接触的方法
公开(公告)号：WO2017003408A1
公开(公告)日：2017-01-05
申请号：PCT/US2015/038191
申请日：2015-06-27
申请人： INTEL CORPORATION
发明人： CHU-KUNG, Benjamin , LE, Van H. , RIOS, Rafael , DEWEY, Gilbert , CLENDENNING, Scott B. , KAVALIEROS, Jack T.
IPC分类号： H01L21/3205 , H01L21/336 , H01L21/28
CPC分类号： H01L29/45 , H01L21/28556 , H01L21/28568 , H01L21/76802 , H01L21/76883 , H01L23/49827 , H01L23/49838 , H01L29/0847 , H01L29/41783 , H01L29/66568 , H01L29/78
摘要： An apparatus including an integrated circuit device including at least one low density of state metal/semiconductor material interface, wherein the at least one low density of state metal is quantized. An apparatus including an integrated circuit device including at least one interface of a low density of state metal and a semiconductor material, wherein a contact area of the metal at the interface is graded. A method including confining a contact area of a semiconductor material; and forming a metal contact in the contact area.
摘要翻译：一种包括集成电路装置的装置，其包括至少一种低密度状态金属/半导体材料界面，其中所述至少一种低密度状态金属被量化。一种包括集成电路装置的装置，其包括至少一个低密度状态金属和半导体材料的界面，其中金属在界面处的接触面积被分级。一种包括限制半导体材料的接触面积的方法; 以及在所述接触区域中形成金属接触。

87. 发明申请

WO2016105426A1 INGAAS EPI STRUCTURE AND WET ETCH PROCESS FOR ENABLING III-V GAA IN ART TRENCH 审中-公开
标题翻译： INGAAS EPI结构和湿蚀刻工艺，用于在ART TRENCH中启用III-V GAA
公开(公告)号：WO2016105426A1
公开(公告)日：2016-06-30
申请号：PCT/US2014/072396
申请日：2014-12-24
申请人： INTEL CORPORATION
发明人： GARDNER, Sanaz K. , RACHMADY, Willy , METZ, Matthew V. , DEWEY, Gilbert , KAVALIEROS, Jack T. , MOHAPATRA, Chandra S. , MURTHY, Anand S. , RAHHAL-ORABI, Nadia M. , ZELICK, Nancy M. , GHANI, Tahir
IPC分类号： H01L21/762 , H01L21/336 , H01L29/78
CPC分类号： H01L29/0673 , H01L21/76224 , H01L29/045 , H01L29/0649 , H01L29/205 , H01L29/267 , H01L29/66522 , H01L29/66545 , H01L29/785
摘要： Embodiments of the invention include nanowire and nanoribbon transistors and methods of forming such transistors. According to an embodiment, a method for forming a microelectronic device may include forming a multi-layer stack within a trench formed in a shallow trench isolation (STI) layer. The multi-layer stack may comprise at least a channel layer, a release layer formed below the channel layer, and a buffer layer formed below the channel layer. The STI layer may be recessed so that a top surface of the STI layer is below a top surface of the release layer. The exposed release layer from below the channel layer by selectively etching away the release layer relative to the channel layer.
摘要翻译：本发明的实施例包括纳米线和纳米棒状晶体管以及形成这种晶体管的方法。根据实施例，用于形成微电子器件的方法可以包括在形成于浅沟槽隔离（STI）层中的沟槽内形成多层堆叠。多层堆叠可以包括至少沟道层，形成在沟道层下面的释放层，以及形成在沟道层下面的缓冲层。 STI层可以凹入，使得STI层的顶表面在释放层的顶表面下方。通过相对于沟道层选择性地蚀刻剥离层，从沟道层下方暴露的剥离层。

88. 发明申请

WO2016105404A1 THIN CHANNEL REGION ON WIDE SUBFIN 审中-公开
标题翻译：窄沟槽区域
公开(公告)号：WO2016105404A1
公开(公告)日：2016-06-30
申请号：PCT/US2014/072276
申请日：2014-12-23
申请人： INTEL CORPORATION
发明人： GARDNER, Sanaz K. , RACHMADY, Willy , METZ, Matthew V. , DEWEY, Gilbert , KAVALIEROS, Jack T. , MOHAPATRA, Chandra S. , MURTHY, Anand S. , RAHHAL-ORABI, Nadia , ZELICK, Nancy M. , GHANI, Tahir
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/785 , H01L29/1054 , H01L29/205 , H01L29/66795 , H01L29/66818
摘要： An embodiment includes a device comprising: a fin structure including an upper portion and a lower portion, the upper portion having a bottom surface directly contacting an upper surface of the lower portion; wherein (a) the lower portion is included in a trench having an aspect ratio (depth to width) of at least 2:1; (b) the bottom surface has a bottom maximum width and the upper surface has an upper maximum width that is greater the bottom maximum width; (c) the bottom surface covers a middle portion of the upper surface but does not cover lateral portions of the upper surface; and (d) the upper portion includes an upper III-V material and the lower portion includes a lower III-V material different from the upper III-V material. Other embodiments are described herein.
摘要翻译：一个实施例包括一种装置，包括：鳍结构，其包括上部和下部，所述上部具有与所述下部的上表面直接接触的底面; 其中（a）下部包括在具有至少2:1的纵横比（深度与宽度）的沟槽中; （b）底面具有底部最大宽度，并且上表面具有大于底部最大宽度的上最大宽度; （c）底面覆盖上表面的中间部分，但不覆盖上表面的侧面部分; 和（d）上部包括上III-V材料，下部包括不同于上III-V材料的下III-V材料。本文描述了其它实施例。

89. 发明申请

WO2014209396A1 INTEGRATING VLSI-COMPATIBLE FIN STRUCTURES WITH SELECTIVE EPITAXIAL GROWTH AND FABRICATING DEVICES THEREON 审中-公开
标题翻译：集成具有选择性外延生长和制造设备的VLSI兼容FIN结构
公开(公告)号：WO2014209396A1
公开(公告)日：2014-12-31
申请号：PCT/US2013/048773
申请日：2013-06-28
申请人： INTEL CORPORATION
发明人： GOEL, Niti , PILLARISETTY, Ravi , RACHMADY, Willy , KAVALIEROS, Jack, T. , DEWEY, Gilbert , CHU-KUNG, Benjamin , RADOSAVLJEVIC, Marko , METZ, Matthew, V. , MUKHERJEE, Niloy , CHAU, Robert S.
IPC分类号： H01L21/336 , H01L29/78 , H01L21/20
CPC分类号： H01L21/823807 , H01L21/0245 , H01L21/02455 , H01L21/02502 , H01L21/02532 , H01L21/02538 , H01L21/02639 , H01L21/02647 , H01L21/76224 , H01L21/823431 , H01L21/823821 , H01L21/823878 , H01L27/0886 , H01L27/0924 , H01L29/0649 , H01L29/1054 , H01L29/267 , H01L29/66795
摘要： Different n- and p- types of device fins are formed by epitaxially growing first epitaxial regions of a first type material from a substrate surface at a bottom of first trenches formed between shallow trench isolation (STI) regions. The STI regions and first trench heights are at least 1.5 times their width. The STI regions are etched away to expose the top surface of the substrate to form second trenches between the first epitaxial regions. A layer of a spacer material is formed in the second trenches on sidewalls of the first epitaxial regions. Second epitaxial regions of a second type material are grown from the substrate surface at a bottom of the second trenches between the first epitaxial regions. Pairs of n- and p- type fins can be formed from the first and second epitaxial regions. The fins are co-integrated and have reduced defects from material interface lattice mismatch.
摘要翻译：通过在形成在浅沟槽隔离（STI）区域之间的第一沟槽的底部的衬底表面外延生长第一类型材料的第一外延区域，形成不同的n型和p-型器件鳍。 STI区域和第一沟槽高度至少是其宽度的1.5倍。蚀刻掉STI区域以暴露衬底的顶表面以在第一外延区域之间形成第二沟槽。在第一外延区域的侧壁上的第二沟槽中形成间隔材料层。在第二外延区域之间的第二沟槽的底部的衬底表面生长第二类型材料的第二外延区域。可以从第一和第二外延区域形成正对和p-型翅片对。翅片是共同整合的，并且从材料界面晶格失配减少缺陷。

90. 发明申请

WO2014051738A1 NON-PLANAR SEMICONDUCTOR DEVICE HAVING GROUP III-V MATERIAL ACTIVE REGION WITH MULTI-DIELECTRIC GATE STACK 审中-公开
标题翻译：具有多层电极堆叠的III-V族材料活性区域的非平面半导体器件
公开(公告)号：WO2014051738A1
公开(公告)日：2014-04-03
申请号：PCT/US2013/045507
申请日：2013-06-12
申请人： INTEL CORPORATION
发明人： DEWEY, Gilbert , RADOSAVLJEVIC, Marko , PILLARISETTY, Ravi , CHU-KUNG, Benjamin , MUKHERJEE, Niloy
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/0673 , B82Y10/00 , B82Y99/00 , H01L29/0665 , H01L29/201 , H01L29/205 , H01L29/408 , H01L29/4236 , H01L29/42364 , H01L29/42392 , H01L29/511 , H01L29/512 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66462 , H01L29/775 , H01L29/78 , H01L29/785 , H01L29/78696
摘要： Non-planar semiconductor devices having group III-V material active regions with multi-dielectric gate stacks are described. For example, a semiconductor device includes a hetero-structure disposed above a substrate. The hetero-structure includes a three-dimensional group III-V material body with a channel region. A source and drain material region is disposed above the three-dimensional group III-V material body. A trench is disposed in the source and drain material region separating a source region from a drain region, and exposing at least a portion of the channel region. A gate stack is disposed in the trench and on the exposed portion of the channel region. The gate stack includes first and second dielectric layers and a gate electrode.
摘要翻译：描述具有多电介质栅叠层的具有III-V族材料的区域的非平面半导体器件。例如，半导体器件包括设置在衬底上的异质结构。异质结构包括具有沟道区的三维III-V族材料体。源极和漏极材料区域设置在三维III-V族材料体上方。在源极和漏极材料区域中布置沟槽，其将源极区域与漏极区域分离，并且暴露沟道区域的至少一部分。栅极堆叠设置在沟槽中和沟道区域的暴露部分上。栅极堆叠包括第一和第二电介质层和栅电极。

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