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71. 发明申请

WO2022011190A1 ELECTRONIC SIGNAL VERIFICATION USING A TRANSLATED SIMULATED WAVEFORM 审中-公开
公开(公告)号：WO2022011190A1
公开(公告)日：2022-01-13
申请号：PCT/US2021/040963
申请日：2021-07-08
申请人： TEKTRONIX, INC.
发明人： BURGESS, David Everett
IPC分类号： G01R31/3183 , G01R23/16 , G01R23/00
摘要： A system for verifying signals in electronic circuits that includes a waveform translator and a test-and-measurement instrument. The waveform translator is configured to receive a simulated waveform for a node of a simulated prototype circuit and to translate the simulated waveform into a translated waveform. The test-and-measurement instrument is configured to obtain a measured waveform and to determine a deviation of the measured waveform from the simulated waveform using the translated waveform.

72. 发明申请

WO2021002914A3 SYSTEMS AND/OR METHODS FOR ANOMALY DETECTION AND CHARACTERIZATION IN INTEGRATED CIRCUITS 审中-公开
公开(公告)号：WO2021002914A3
公开(公告)日：2021-01-07
申请号：PCT/US2020/027433
申请日：2020-04-09
申请人： GRAMMATECH, INC.
发明人： DICKENS, Jason
IPC分类号： G01R31/3177 , G01R31/3183 , G01R31/3185 , G01R31/319
摘要： Systems, methods, and computer readable medium described herein relate to techniques for characterizing and/or anomaly detection in integrated circuits such as, but not limited to, field programmable gate arrays (FPGAs) and application-specific integrated circuits (ASICs). In one example aspect of certain example embodiments, a fully digital technique relies on the pulse width of signals propagated through a path under test. In another example aspect, the re-configurability of the integrated circuit is leveraged to combine the pulse propagation technique with a delay characterization technique to yield better detection of certain type of Trojans and the like. Another example aspect provides for running the test through reconfigurable path segments in order to isolate and identify anomalous circuit elements. Yet another example aspect provides for performing the characterization and anomaly detection without requiring golden references and the like.

73. 发明申请

WO2020206442A1 TEST GENERATION SYSTEMS AND METHODS 审中-公开
公开(公告)号：WO2020206442A1
公开(公告)日：2020-10-08
申请号：PCT/US2020/026909
申请日：2020-04-06
申请人： VAXEL INC.
发明人： TAKARA, Jun
IPC分类号： G01R31/317 , G01R31/3183 , G01R31/28
摘要： Example test generation systems and methods are described. In one implementation, a hardware test suite generator includes a script reader that receives a test definition script and parses the test definition script. A test generator receives the parsed test definition script from the script reader and creates a test suite. A template reader receives a test definition template and parses the test definition template. A code generator receives the parsed test definition script from the script reader and receives the parsed test definition template from the template reader.

74. 发明申请

WO2020182992A1 HIGH-DIMENSIONAL MULTI-DISTRIBUTED IMPORTANCE SAMPLING FOR CIRCUIT YIELD ANALYSIS 审中-公开
公开(公告)号：WO2020182992A1
公开(公告)日：2020-09-17
申请号：PCT/EP2020/056890
申请日：2020-03-13
申请人： XENERGIC AB
发明人： JOHANSSON, Tom , PRABHU, Hemanth , LLORENS, Arturo, Prieto , MOHAMMADI, Babak
IPC分类号： G06F30/33 , G01R31/3183 , G06F11/26
摘要： The present disclosure relates to a computer-implemented method for simulation of an integrated circuit for yield analysis of the integrated circuit, the method comprising the steps of: a) for a plurality of variables, generating initial sampling sets by sampling from provided distributions related to physical properties of the integrated circuits; b) selecting at least one sample from each initial sampling set randomly and combining the selected samples into an initial simulation set; c) running an initial simulation of an operation of the integrated circuit, applying the initial simulation set, wherein the operation has a criterion for passing and failing the operation; d) if the initial simulation fails: storing the samples of the initial simulation set into initial sampling distributions for each variable; e) repeating steps b) – d) until a sufficient number of failures have been obtained; f) building an importance sampling distribution based on each initial sampling distribution, the importance sampling distribution having a lower portion, a center portion and an upper portion; g) generating a secondary simulation set by drawing a number of samples from the importance sampling distribution for each variable; h) simulating the integrated circuit by applying the secondary simulation set; i) repeating steps g) – h) a number of times; j) mapping of the resulting yields to the provided distributions, thereby obtaining a yield of the integrated circuit.

75. 发明申请

WO2020003458A1 半導体検査装置审中-公开
公开(公告)号：WO2020003458A1
公开(公告)日：2020-01-02
申请号：PCT/JP2018/024678
申请日：2018-06-28
申请人：株式会社日立ハイテクノロジーズ
发明人：古森　正明 , 大木　克夫
IPC分类号： H01L21/66 , G01R31/28 , G01R31/3183
摘要：微小デバイスの不良解析において高感度に異常を検出できる半導体検査装置を提供する。半導体検査装置は、試料を載置する試料台６と、試料に電子線を照射する電子光学系１と、試料に接触される測定探針３と、測定探針からの出力を測定する測定器８と、試料への電子線の照射に応答した測定探針からの出力の測定値を取得する情報処理装置９とを有し、情報処理装置は、試料に対して電子線の照射を開始するタイミング及び電子線の照射をフリーズするタイミングと、電子線が試料に照射された状態で測定器が測定探針からの出力を測定する第１の測定期間と、電子線の照射がフリーズされた後に測定器が測定探針からの出力を測定する第２の測定期間とを設定し、試料への電子線の照射に応答した測定探針からの出力の測定値を、第１の測定期間に測定された第１の測定値と第２の測定期間に測定された第２の測定値との差から求める。

76. 发明申请

WO2018132595A1 SYSTEMS AND METHODS FOR DYNAMICALLY RECONFIGURING AUTOMATIC TEST EQUIPMENT 审中-公开
公开(公告)号：WO2018132595A1
公开(公告)日：2018-07-19
申请号：PCT/US2018/013359
申请日：2018-01-11
申请人： A.T.E. SOLUTIONS, INC.
发明人： UNGAR, Louis Yehuda , TAK, Ming Mak , JACOBSON`, Neil Glenn
IPC分类号： G01R31/3183 , G06F11/263 , G11C29/10 , G11C29/56
摘要： A dynamically reconfigurable interface for an automatic test equipment is disclosed where one or more synthetic instruments transmit the high speed signals as well as receive the high speed signals from a device under test so that testing can be performed at speeds higher than the ATE was originally designed to accommodate. Synthetic instruments are implemented on a field programmable gate array (FPGA) that operate at higher speeds than COTS instruments and can reach the frequencies that high speed I/O buses use. SIs can be created by configuring the FPGA, with different configurations creating different SIs. A single FPGA can house a number of SIs.

77. 发明申请

WO2018037787A1 テスト項目生成方法、演算装置审中-公开
标题翻译：测试项目生成方法，计算设备
公开(公告)号：WO2018037787A1
公开(公告)日：2018-03-01
申请号：PCT/JP2017/026374
申请日：2017-07-20
申请人：日立オートモティブシステムズ株式会社
发明人：中川　雄一郎 , 月舘　統宙 , 蛯名　朋仁
IPC分类号： G06F11/263 , G01R31/3183 , G06F11/36 , G06F17/50
摘要：複数のタスクを実行する複数のＣＰＵコア、および複数のＣＰＵコアがアクセスする共有資源を備える演算装置におけるテスト項目を生成するテスト項目生成方法は以下のとおりである。すなわち、コンピュータが、複数のタスクのうち、共有資源にアクセスするタスクを特定することと、コンピュータが、複数のタスクを、実行されるＣＰＵコアごとに分類することと、コンピュータが、分類された複数のタスクのＣＰＵコア内における実行順番を特定することと、コンピュータが、特定されたＣＰＵコア内における複数のタスクの実行順番に適合し、かつ異なるＣＰＵコアでそれぞれ実行される共有資源にアクセスする２以上のタスクの実行順番が互いに入れ替えられたタスク実行順列を複数生成することにより、テスト項目を生成することとを備える。
摘要翻译：
测试项目的生成方法，其中，用于执行多个任务和多个CPU内核的多个CPU内核，以产生在所述运算装置的检查项目包括要访问的共享资源是如下。多个单词，计算机，多个任务之一，以确定访问共享的资源，所述计算机，所述方法包括的任务：多个任务的分类中，待执行的每个CPU内核中，计算机已被分类在CPU内核中的任务中，访问与指定CPU内核中的多个任务的执行顺序兼容并且分别由不同CPU内核执行的共享资源2 并且通过生成多个任务执行序列来生成测试项目，其中任务的执行顺序被互换。

78. 发明申请

WO2017155636A1 USING AN OPTICAL INTERFACE BETWEEN A DEVICE UNDER TEST AND A TEST APPARATUS 审中-公开
标题翻译：在测试设备和测试设备之间使用光学接口
公开(公告)号：WO2017155636A1
公开(公告)日：2017-09-14
申请号：PCT/US2017/016012
申请日：2017-02-01
申请人： INTEL CORPORATION
发明人： KUEHNIS, Rolf H. , EDER, Patrik
IPC分类号： G01R31/319 , G01R31/3183
CPC分类号： H04N17/004 , G06F11/079 , G06F11/2294 , G06K9/036 , G06K9/2054
摘要： Embodiments of the present disclosure provide a method and apparatus for device testing via an optical interface. In one instance, the apparatus may comprise a test -controller to operate a camera to generate an image to capture test data displayed on a screen of a device under test. The test controller may be configured to extract the test data from the image, analyze the test data, and generate feedback information for the device under test, based at least in part on a result of the analysis of the test data. The camera may be included in the apparatus and communicatively coupled with the test controller. Other embodiments may be described and/or claimed.
摘要翻译：本公开的实施例提供了一种用于经由光学接口进行设备测试的方法和装置。在一个实例中，该装置可以包括测试控制器以操作照相机以生成图像以捕捉被测设备的屏幕上显示的测试数据。测试控制器可以被配置为至少部分地基于测试数据的分析结果来从图像中提取测试数据，分析测试数据并且为被测设备生成反馈信息。照相机可以被包括在设备中并且与测试控制器可通信地耦合。其他实施例可以被描述和/或要求保护。

79. 发明申请

WO2016153662A1 PSEUDORANDOM BIT SEQUENCES IN AN INTERCONNECT 审中-公开
标题翻译：互连中的PSEUDORANDOM位比特序列
公开(公告)号：WO2016153662A1
公开(公告)日：2016-09-29
申请号：PCT/US2016/018842
申请日：2016-02-22
申请人： INTEL CORPORATION
发明人： WAGH, Mahesh , WU, Zuoguo , IYER, Venkatraman
IPC分类号： G01R31/317 , G01R31/3177 , G01R31/3183 , G06F13/42
CPC分类号： H04B3/46 , H04B3/32 , H04B3/487
摘要： In an example, a linear feedback shift register (LFSR) provides pseudorandom bit sequences (PRBSs) to an interconnect for training, testing, and scrambling purposes. The interconnect may include a state machine, with states including LOOPBACK, CENTERING, RECENTERING, and ACTIVE states, among others The interconnect is permitted to move from "CENTERING" to "LOOPBACK" via a sideband signal. In LOOPBACK, CENTERING, and RECENTERING, PRBSs are used for training and testing purposes to electrically characterize and test the interconnect, and to locate a midpoint for a reference voltage V ref. A unique, noncorrelated PRBS is provided to each lane, calculated using one common output bit. Multiple bits per lane may also be computed per clock cycle so that the LFSR can run at a slower clock rate than the interconnect. A selecting network may also be provided so that, as necessary, "victim," "aggressor," and "neutral" lanes may be provided for testing purposes.
摘要翻译：在一个示例中，线性反馈移位寄存器（LFSR）向用于训练，测试和加扰目的的互连提供伪随机比特序列（PRBS）。互连可以包括状态机，其中包括LOOPBACK，CENTERING，RECENTERING和ACTIVE状态等状态。互连允许经由边带信号从“CENTERING”移动到“LOOPBACK”。在LOOPBACK，CENTERING和RECENTERING中，PRBS用于训练和测试目的，用于电气表征和测试互连，并定位参考电压V ref的中点。使用一个公共输出位计算每个通道提供一个独特的，不相关的PRBS。每个时钟周期也可以计算每个通道的多个位，以便LFSR可以以比互连更慢的时钟速率运行。还可以提供选择网络，以便根据需要，可以为测试目的提供“受害者”，“侵略者”和“中立”通道。

80. 发明申请

WO2016073388A1 TEST OF SEMICONDUCTOR STORAGE POWER CONSUMPTION ON BASIS OF EXECUTED ACCESS COMMANDS 审中-公开
标题翻译：基于执行访问命令的半导体存储功耗测试
公开(公告)号：WO2016073388A1
公开(公告)日：2016-05-12
申请号：PCT/US2015/058695
申请日：2015-11-03
申请人： MICROSOFT TECHNOLOGY LICENSING, LLC
发明人： CAULFIELD, Laura Marie , SANTANIELLO, Mark Alan , ANDREWARTHA, J. Michael , SIEGLER, John J.
IPC分类号： G11C29/02 , G11C29/50 , G01R31/3183 , G01R21/00
CPC分类号： G11C29/50 , G01R31/3004 , G01R31/318342 , G11C5/14 , G11C29/021 , G11C29/10 , G11C29/50004 , G11C2029/0409 , G11C2029/5004 , G11C2029/5006
摘要： The present invention extends to methods, systems, and computer program products for testing storage device power circuitry (113). A storage device controller (102) includes an embedded test program (104). The storage device controller executes the test program in response to receiving a test command. In one aspect, the test program issues a plurality of different command patterns (107A,..., 107C) to test shared power circuitry (113) of storage device components (e.g., shared by an array of NAND flash memory devices (108A,..., 108C)). The test program identifies a command pattern (107) that causes a greatest total current draw. In another aspect, the test program issues a specified command pattern (possibly repeatedly) to shared power circuitry to determine if the shared power circuitry fails.
摘要翻译：本发明扩展到用于测试存储设备电源电路（113）的方法，系统和计算机程序产品。存储设备控制器（102）包括嵌入式测试程序（104）。响应于接收到测试命令，存储设备控制器执行测试程序。在一个方面，测试程序发布多个不同的命令模式（107A，...，107C），以测试存储设备组件的共享电源电路（113）（例如，由NAND闪存设备阵列（108A， ...，108C））。测试程序识别导致最大总电流消耗的命令模式（107）。在另一方面，测试程序向共享的电源电路发出指定的指令模式（可能重复），以确定共享电源电路是否发生故障。

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