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71. 发明申请

WO03025757A2 METHOD AND APPARATUS FOR DECOUPLING TAG AND DATA ACCESSES IN A CACHE MEMORY 审中-公开
标题翻译：用于解除缓存中的标签和数据访问的方法和装置
公开(公告)号：WO03025757A2
公开(公告)日：2003-03-27
申请号：PCT/US0229259
申请日：2002-09-13
申请人： SUN MICROSYSTEMS INC
发明人： CHAUDHRY SHAILENDER , TREMBLAY MARC
IPC分类号： G06F12/08
CPC分类号： G06F12/0855
摘要： One embodiment of the present invention provides a system that decouples a tag access from a corresponding data access within a cache memory. The system operates by receiving a memory request at the cache memory, wherein the memory request includes an address identifying a memory location. Next, the system performs the tag access by looking up at least one tag from a tag array within the cache memory and comparing the at least one tag with a tag portion of the address to determine if a cache line containing the address is located in the cache memory. If the cache line containing the address is located in the cache memory but a data array containing the cache line is busy, the system performs the corresponding data access at a later time when the data array becomes free. Furthermore, if the memory request is for a load operation, the corresponding data access takes place without waiting for preceding load operations to complete.
摘要翻译：本发明的一个实施例提供一种将标签访问与高速缓存存储器内的对应数据访问分离的系统。该系统通过在高速缓存存储器处接收存储器请求来操作，其中存储器请求包括标识存储器位置的地址。接下来，系统通过从高速缓冲存储器内的标签阵列中查找至少一个标签来执行标签访问，并将该至少一个标签与该地址的标签部分进行比较，以确定包含地址的高速缓存行是否位于高速缓存存储器。如果包含该地址的高速缓存行位于高速缓冲存储器中，而包含高速缓存行的数据阵列正忙，则在数据数组空闲时，系统会在稍后执行相应的数据访问。此外，如果存储器请求用于加载操作，则相应的数据访问在不等待先前的加载操作完成的情况下进行。

72. 发明申请

WO0174134A2 SYSTEM HAVING A CONFIGURABLE CACHE/SRAM MEMORY 审中-公开
标题翻译：具有可配置缓存/ SRAM存储器的系统
公开(公告)号：WO0174134A2
公开(公告)日：2001-10-11
申请号：PCT/US0110299
申请日：2001-03-30
申请人： INTEL CORP , RAMAGOPAL HEBBALALU S , WITT DAVID B , ALLEN MICHAEL , SYED MOINUL , KOLAGOTLA RAVI , BOOTH LAWRENCE A JR , ANDERSON WILLIAM C
发明人： RAMAGOPAL HEBBALALU S , WITT DAVID B , ALLEN MICHAEL , SYED MOINUL , KOLAGOTLA RAVI , BOOTH LAWRENCE A JR , ANDERSON WILLIAM C
IPC分类号： G06F12/08 , G06F13/16
CPC分类号： G06F12/0855 , G06F12/0893 , G06F13/16
摘要： An apparatus having a core processor and a memory system is disclosed. The core processor includes at least one data port. The memory system is connected in such a way as to provide substantially simultaneous data accesses through the data port. The memory system can be made user configurable to provide appropriate memory model.
摘要翻译：公开了一种具有核心处理器和存储器系统的设备。核心处理器包括至少一个数据端口。存储器系统以这样的方式连接，以便通过数据端口提供基本上同时的数据访问。存储器系统可以由用户配置来提供适当的存储器模型。

73. 发明申请

WO00026742A3 PROCESSING ORDERED DATA REQUESTS TO A MEMORY 审中-公开
标题翻译：处理有关的数据请求寄往一个存储器
公开(公告)号：WO00026742A3
公开(公告)日：2000-08-10
申请号：PCT/US1999/024362
申请日：1999-10-18
IPC分类号： G06F12/08 , G06F12/00 , G06F13/00
CPC分类号： G06F12/0855
摘要： A method is provided for requesting data from a memory (120). The method includes issuing a plurality of data requests to a data request port for the memory (120). The plurality of data requests includes at least two ordered data requests. The method includes determining if an earlier one of the ordered data requests corresponds to a miss in the memory (120), and converting a later one of the ordered data requests to a prefetch in response to the earlier one of the ordered data requests corresponding to a miss in the memory (120). An apparatus includes memory (120) having at least one pipelined port for receiving data requests. The port is adapted to determine whether an earlier ordered one of the data requests corresponds to a miss in the memory (120). The port converts a later ordered one of the data requests to a prefetch in response to determining that the earlier ordered one of the data requests corresponds to a miss in the memory (120).
摘要翻译：本发明涉及一种寻址到存储器的数据请求方法，该方法包括向存储器的数据请求端口发送多个数据请求。数据查询包含至少两个有序的数据查询。该方法然后包括确定构成有序数据请求的一部分的预期请求是否对应于存储器中的不存在并且响应于该请求将形成有序数据的查询的部分的后续请求转换成预提取。先前对应于存储器中的不存在。用于执行该方法的设备包括具有至少一个用于接收数据请求的管道端口的存储器。此端口用于确定作为数据请求一部分的较早订购的请求是否对应于存储器中的不存在。响应于确定操作，作为数据请求的一部分的预期有序请求对应于存储器中的不存在，端口将作为数据请求的一部分的后续有序请求转换为预提取。

74. 发明申请

WO0026742A2 PROCESSING ORDERED DATA REQUESTS TO A MEMORY 审中-公开
标题翻译：对存储器处理订购的数据请求
公开(公告)号：WO0026742A2
公开(公告)日：2000-05-11
申请号：PCT/US9924362
申请日：1999-10-18
申请人： INTEL CORP , FU JOHN WAI CHEONG , MULLA DEAN AHMAD , MATHEWS GREGORY S , SAILER STUART E , SHAW JENG JYE
发明人： FU JOHN WAI CHEONG , MULLA DEAN AHMAD , MATHEWS GREGORY S , SAILER STUART E , SHAW JENG-JYE
IPC分类号： G06F12/08 , G06F
CPC分类号： G06F12/0855
摘要： A method is provided for requesting data from a memory (120). The method includes issuing a plurality of data requests to a data request port for the memory (120). The plurality of data requests includes at least two ordered data requests. The method includes determining if an earlier one of the ordered data requests corresponds to a miss in the memory (120), and converting a later one of the ordered data requests to a prefetch in response to the earlier one of the ordered data requests corresponding to a miss in the memory (120). An apparatus includes memory (120) having at least one pipelined port for receiving data requests. The port is adapted to determine whether an earlier ordered one of the data requests corresponds to a miss in the memory (120). The port converts a later ordered one of the data requests to a prefetch in response to determining that the earlier ordered one of the data requests corresponds to a miss in the memory (120).
摘要翻译：提供一种用于从存储器（120）请求数据的方法。该方法包括向存储器（120）的数据请求端口发出多个数据请求。多个数据请求包括至少两个有序数据请求。所述方法包括确定所述有序数据请求中的较早的一个是否对应于所述存储器（120）中的未命中，以及响应于所述有序数据请求中较早的一个对应于在记忆中的一个念头（120）。一种装置包括具有用于接收数据请求的至少一个流水线端口的存储器（120）。端口适于确定数据请求中的较早有序的数据请求是否对应于存储器（120）中的未命中。响应于确定早期有序数据请求对应于存储器（120）中的未命中，端口将稍后排序的一个数据请求转换为预取。

75. 发明申请

WO1996012227A1 AN ADDRESS QUEUE CAPABLE OF TRACKING MEMORY DEPENDENCIES 审中-公开
标题翻译：跟踪记忆依赖关系的地址队列
公开(公告)号：WO1996012227A1
公开(公告)日：1996-04-25
申请号：PCT/US1995013299
申请日：1995-10-13
申请人： SILICON GRAPHICS, INC.
发明人： SILICON GRAPHICS, INC. , YEAGER, Kenneth, C.
IPC分类号： G06F12/00
CPC分类号： G06F9/3836 , G06F9/3834 , G06F9/3838 , G06F9/384 , G06F9/3857 , G06F12/0855 , G06F12/0864
摘要： An address queue (308) in a superscalar processor has the capability to track memory dependency of memory access instructions that may be executed out-of-order. In accessing a two way-set-associative data cache, the address queue imposes a dependency for accesses to the same cache set to prevent unnecessary cache trashing. The address queue (308) holds a plurality of entries used to access a set-associative data cache. This queue includes a comparator circuit (2406), a first matrix (2400) of RAM cells and a second matrix (2450) of RAM cells. The comparator circuit (2406) compares a newly calculated partial address derived from a new queue entry with a previously calculated partial address derived from one of a number of previous entries. The first matrix (2400) of RAM cells tracks all of the previous entries in the queue that use a cache set that is also used by the new queue entry. The second matrix (2450) of RAM cells tracks queue entries that are store instructions which store a portion of data in the data cache which is accessed by a subsequent load instruction.
摘要翻译：超标量处理器中的地址队列（308）具有跟踪可以无序执行的存储器访问指令的存储器依赖性的能力。在访问双向组关联数据高速缓存时，地址队列强加了对同一缓存集的访问的依赖关系，以防止不必要的高速缓存丢弃。地址队列（308）保存用于访问集合关联数据高速缓存的多个条目。该队列包括比较器电路（2406），RAM单元的第一矩阵（2400）和RAM单元的第二矩阵（2450）。比较器电路（2406）将从新的队列条目导出的新计算的部分地址与从多个先前条目之一导出的先前计算的部分地址进行比较。 RAM单元的第一矩阵（2400）跟踪队列中使用也由新队列条目使用的高速缓存集合的所有先前条目。 RAM单元的第二矩阵（2450）跟踪作为存储指令的队列条目，存储指令存储由后续加载指令访问的数据高速缓存中的一部分数据。

76. 发明申请

WO8906397A3 METHOD FOR PREFETCHING VECTOR DATA FROM MEMORY IN A MEMORY SYSTEM DESIGNED FOR SCALAR PROCESSING 审中-公开
标题翻译：用于在设计用于标量处理的存储器系统中从存储器预先映射向量数据的方法
公开(公告)号：WO8906397A3
公开(公告)日：1989-08-10
申请号：PCT/US8900021
申请日：1989-01-04
申请人： DIGITAL EQUIPMENT CORP
发明人： FOSSUM TRYGGVE , HETHERINGTON RICKY C , FITE DAVID B JR , MANLEY DWIGHT P , MCKEEN FRANCIS X , MURRAY JOHN E
IPC分类号： G06F12/06 , G06F9/38 , G06F12/02 , G06F12/08 , G06F15/78 , G06F17/16
CPC分类号： G06F15/8069 , G06F9/3455 , G06F9/383 , G06F12/0207 , G06F12/0855
摘要： A main memory and cache suitable for scalar processing are used in connection with a vector processor by issuing prefetch requests in response to the recognition of a vector load instruction. A respective prefetch request is issued for each block containing an element of the vector to be loaded from memory. In response to a prefetch request, the cache is checked for a ''miss'' and if the cache does not include the required block, a refill request is sent to the main memory. The main memory is configured into a plurality of banks and has a capability of processing multiple references. Therefore the different banks can be referenced simultaneously to prefetch multiple blocks of vector data. Preferably a cache bypass is provided to transmit data directly to the vector processor as the data from the main memory are being stored in the cache. In a preferred embodiment, a vector processor is added to a digital computing system including a scalar processor, a virtual address translation buffer, a main memory and a cache. The scalar processor includes a microcode interpreter which sends a vector load command to the vector processing unit and which also generates vector prefetch requests. The addresses for the data blocks to be prefetched are computed based upon the vector address, the length of the vector and the ''stride'' or spacing between the addresses of the elements of the vector.

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