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71. 发明申请

WO2020182361A1 METHOD FOR MAKING A COHESIVE CONNECTION BY FLUXLESS CHIP- OR ELEMENT SOLDERING, GLUING OR SINTERING USING A MATERIAL PREFORM 审中-公开
公开(公告)号：WO2020182361A1
公开(公告)日：2020-09-17
申请号：PCT/EP2020/051916
申请日：2020-01-27
申请人： DANFOSS SILICON POWER GMBH
发明人： ULRICH, Holger , RABSCH, Tom
IPC分类号： H01L23/488 , H01L21/60 , H01L21/58
摘要： A method (100) for making a cohesive connection of a first component (1) (e.g., a DCB (Direct Copper Bonding) substrate) of a power semiconductor module to a second component (2) (e.g., an electronic component, in particular a semiconductor) of the power semiconductor module comprises the steps of: applying (101) a bonding material preform (14) to a bonding surface (3) of the first component (1), the bonding material preform (14) comprising a first surface (7) to be placed on the bonding surface (3) of the first component (1) and a second surface (6), opposite the first surface (7), which comprises one or more locating structures (13, 15, 16) suitable for locating the second component (2); arranging (103) the second component (2) on the surface (6) of the bonding material preform (14) opposite to the surface facing the first component (1) and located using the locating structures (13, 15, 16); and processing (104) (e.g., by heating and/or applying pressure) the complete area of the bonding material (9). The locating structures (13, 15, 16) ensure that the second component (2) is accurately and firmly retained in position in relation to the bonding material preform (14). The locating structures (13, 15, 16) may comprise a raised wall (15) or raised indexes (16) protruding from the otherwise substantially flat second surface of the bonding material preform (14). The bonding material preform (14) may be formed by preparing (105) a flat bonding material preform (4) and modifying (106) the flat material preform (4) to form a material preform (14) comprising one or more locating structures (13) suitable for locating the second component (2). The method may comprise, after applying the material preform (4, 14) to the bonding surface of the first component (1), a step of fixing (102) the material preform (4, 14) to the first component (1) by heating in a locally delimited partial area (5) of the material preform, wherein the heating may be provided by a laser (17) or by a heating probe (8). The bonding material (9) may be a sintering material, a solder, an organic foil or a thermosetting adhesive. The material preform (14) may comprise a stabilizing means (30), which keeps a specific gap between the surfaces being connected during the period when the material of the material preform (14) is at a raised temperature and may therefore be in a liquid state. This may be the case if the method is used to simultaneously connect a plurality of surfaces in a single stack but using material preforms (4, 14) of differing materials, such as a sintering material and a solder material. The stabilizing means (30) may be solid spacer means (e.g., substantially spherical bodies made of metal (in particular copper), glass or ceramics, or a wire mesh, in particular made of metal (in particular copper)) which are incorporated in a soldering material preform (14). It is also possible to arrange a distribution of the stabilizing means (30) within the material preform (14) to ensure a separation between the finally connected surfaces which is constant, or which is at an angle, for example increases across the surface from one side to another, e.g. when the stabilizing means (30) comprises a copper wire mesh.

72. 发明申请

WO2020178143A1 PRESSURE SINTERING DEVICE AND METHOD FOR MANUFACTURING AN ELECTRONIC COMPONENT BY A PRESSURE-ASSISTED LOW-TEMPERATURE SINTERING PROCESS 审中-公开
公开(公告)号：WO2020178143A1
公开(公告)日：2020-09-10
申请号：PCT/EP2020/055181
申请日：2020-02-27
申请人： DANFOSS SILICON POWER GMBH
发明人： BECKER, Martin , DITTMANN, Dirk
IPC分类号： H01L21/67 , H05K13/04 , H01L21/98 , H01L21/60 , H05K3/32
摘要： A method for manufacturing an electronic component (34, 34', 34") by a pressure-assisted low-temperature sintering process, by using a pressure sintering device (2) having an upper die (4) and a lower die (6) is disclosed. The upper die (4) and/or the lower die (6) is provided with a first pressure pad (10, 10", 10"', 210, 210", 210"'). The method comprises the following steps: placing a first component (26) on a first sintering layer (24) provided on the top layer (22) of a first substrate (20+12+22), intended to form a first electronic component (34); placing, in a level above or below the to-be-formed first electronic component (34), at least a second component (26', 26") on a second sintering layer (24", 24"") provided on a top layer (22', 22") of a second substrate (20'+12'+22', 20" + 12"+22"), intended to form a second electronic component (34', 34"); placing a second pressure pad (10', 10", 10'", 10"", 10''''', 210', 210", 210'", 210"", 210''''') between the to-be-formed first electronic component (34) and second electronic component (34', 34"); and joining the first component (26) and the top layer (22) of the first substrate (20+12+22) by means of the first sintering layer (24) to form the first electronic component (34) as well as joining the second component (26', 26") and the top layer (22', 22") of the second substrate (20' + 12'+22', 20" + 12"+22") by means of the second sintering layer (24", 24"") to form the second electronic component (34', 34"), by pressing the upper die (4) and the lower die (6) towards each other, wherein the sintering device (2) is simultaneously heated. The method may further comprise a step of covering the first component (26) with a first protective foil (18) arranged to be brought into engagement with the first pressure pad (10, 210). The method may also comprise a step of covering the second component (26', 26") with a second protective foil (18', 18"). One or more of the pressure pads (10, 10', 10", 10'", 10"", 10''''') may be deformable pressure pads (210, 210', 210", 210'", 210"", 210'''''), which may comprise a fluid contained in an enclosure. A plate (36, 36') may be arranged between adjacent electronic components (34, 34', 34"), wherein the plate (36) may be provided with heating elements (32') or the plate (36, 36') may be heated by induction means (232). The first electronic component (34, 34', 34") or the second electronic component (34, 34', 34") may comprise a baseplate (28, 28', 28"), which may function as the additional pressure pad. The first and second electronic components (34, 34', 34") may be double-sided electronic components comprising an insulation (12, 12', 12") having a top surface provided with a first sintering layer (24, 24", 24'") onto which a first component (26, 26", 26"') is placed and having an underside surface provided with a second sintering layer (24', 24'") onto which a second component (26', 26'") is arranged.

73. 发明申请

WO2020127442A3 SEMICONDUCTOR HOUSING FOR PARTIALLY ENCLOSING A SEMICONDUCTOR DIE, INTERMEDIATE PRODUCT AND METHOD OF MANUFACTURING THE SAME 审中-公开
公开(公告)号：WO2020127442A3
公开(公告)日：2020-06-25
申请号：PCT/EP2019/085883
申请日：2019-12-18
申请人： DANFOSS SILICON POWER GMBH
发明人： BECKER, Martin , RUDZKI, Jacek , EISELE, Ronald , OSTERWALD, Frank , BASTOS ABIBE, André
IPC分类号： H01L23/49 , H01L23/492 , H01L21/60
摘要： A semiconductor module having a semiconductor and a housing (100) enclosing the semiconductor, wherein the housing is made of an electrically conductive material and has a recess (30) occupied by the semiconductor, wherein the side of the semiconductor opposite the recess (30) is coplanar with the surface of the housing (100) having the recess (30). The housing (100) may have an opening which communicates with the recess (30) to make the control terminal of the semiconductor accessible from outside the housing (100). The control terminal may be connected to the corresponding control terminal on a substrate (200) through a bond wire (300).

74. 发明申请

WO2019179955A1 BUSBAR, METHOD FOR MANUFACTURING THE SAME AND POWER MODULE COMPRISING THE SAME 审中-公开
公开(公告)号：WO2019179955A1
公开(公告)日：2019-09-26
申请号：PCT/EP2019/056729
申请日：2019-03-18
申请人： DANFOSS SILICON POWER GMBH
发明人： TØNNES, Michael
IPC分类号： H01L23/498
摘要： A conducting busbar (2, 4) suitable for use in a semiconductor power module(8)is provided. The busbar (2, 4) comprises a main plate (210, 410), one or more legs (220, 420) extending from the main plate (210, 410), and one or more feet (230, 430) formed at the free end of the legs (220, 420). According to the invention, the intersection line (L) between at least one of the legs (220, 420) and the associated foot(230, 430)forms an offset angle (α) with respect to the longitudinal direction(X)of the main plate (210, 410).

75. 发明申请

WO2018130408A1 POWER MODULE WITH OPTIMIZED PIN LAYOUT 审中-公开
公开(公告)号：WO2018130408A1
公开(公告)日：2018-07-19
申请号：PCT/EP2017/084356
申请日：2017-12-22
申请人： DANFOSS SILICON POWER GMBH
发明人： MÜHLFELD, Ole , MANNMEUSEL, Guido , BERGMANN, Jörg
IPC分类号： H02M7/00 , H01L23/373 , H02M7/483 , H02M7/487
CPC分类号： H02M7/003 , H01L23/3735 , H01L2224/49111 , H01L2924/19107 , H02M7/483 , H02M7/487
摘要： The present disclosure provides a three-level power module comprising sets of one or more pins which are suitable for connecting to a positive Direct Current (DC) potential, a negative DC potential and a neutral potential, wherein at least one of pins suitable for connecting to the positive DC potential and at least one of pins suitable for connecting to the negative DC potential are each placed adjacent to a pin suitable for connecting to the neutral potential.

76. 发明申请

WO2018015156A1 ELECTRICAL ASSEMBLY COMPRISING A METAL BODY ARRANGED ON A SEMICONDUCTOR CHIP AND A CONNECTING MATERIAL ARRANGED BETWEEN THE SEMICONDUCTOR CHIP AND THE METAL BODY AND CONNECTING THEM 审中-公开
标题翻译：包括设置在半导体芯片上的金属体和在半导体芯片和金属体之间设置的连接材料并连接它们的电气组件
公开(公告)号：WO2018015156A1
公开(公告)日：2018-01-25
申请号：PCT/EP2017/066786
申请日：2017-07-05
申请人： DANFOSS SILICON POWER GMBH
发明人： OSTERWALD, Frank , SCHEFUSS, Frank , RUDZKI, Jacek
IPC分类号： H01L23/49 , H01L23/485 , H01L21/603
摘要： Electrical assembly (10) comprising a semiconductor chip (20), a metal body (30) arranged on the semiconductor chip (20), and a connecting material (40) (in particular, a sintering material) arranged between the semiconductor chip (20) and the metal body (30) and serving for connecting the semiconductor chip (20) to the metal body (30), wherein the metal body (30) has a first section (30a) arranged above the connecting material (40), a second section (30b) arranged in a manner surrounding the connecting material (40) and touching the semiconductor chip (20), and a third section (30c) connecting the first section (30a) to the second section (30b). In particular, a portion (40a) of the sintering material (40) which is arranged adjacent to the second section (30b), and in particular in the region of the third section (30c) of the metal body (30), is more compressed than the portion (40b) of the sintering material (40) arranged centrally below the first section (30a) of the metal body (30). The connecting layer (40), that is sensitive to crack initiations against environmental influences, is thus shielded by virtue of the fact that the metal body (30) covering the connecting layer (40) is pressed onto the semiconductor chip (20) with its sections extending beyond the area of the connecting layer (40). The metal body (30) additionally acts as a barrier to environmental influences otherwise acting in the direction of the connecting layer (40). Crack initiation or a corrosive attack by external influences is effectively minimized by this design.
摘要翻译：包括半导体芯片（20），布置在半导体芯片（20）上的金属体（30）以及布置在半导体芯片（20）之间的连接材料（40）（特别是烧结材料）的电气组件（10））和金属体（30）之间并用于将半导体芯片（20）连接到金属体（30），其中金属体（30）具有布置在连接材料（40）上方的第一部分（30a）以包围连接材料40并接触半导体芯片20的方式布置的第二部分30b以及将第一部分30a连接到第二部分30b的第三部分30c。特别地，与金属体（30）的第二部分（30b）相邻并且特别是在第三部分（30c）的区域中布置的烧结材料（40）的一部分（40a）更多（30）的第一部分（30a）下方中央的烧结材料（40）的部分（40b）被压缩。因此，由于覆盖连接层（40）的金属体（30）以其覆盖半导体芯片（20）的方式被压在半导体芯片（20）上，因此屏蔽了对抗环境影响的开裂引发的连接层延伸超出连接层（40）的区域。金属体（30）另外用作对环境影响的屏障，否则沿连接层（40）的方向作用。这种设计有效降低了裂纹萌生或外部影响的腐蚀性攻击。

77. 发明申请

WO2018007062A1 LOW-INDUCTANCE POWER MODULE DESIGN 审中-公开
标题翻译：低电感功率模块设计
公开(公告)号：WO2018007062A1
公开(公告)日：2018-01-11
申请号：PCT/EP2017/061645
申请日：2017-05-15
申请人： DANFOSS SILICON POWER GMBH
发明人： EISELE, Ronald , OSTERWALD, Frank , MÜHLFELD, Ole , BEER, Holger
IPC分类号： H01L25/07
CPC分类号： H01L25/072 , H01L2224/32225 , H01L2224/32245 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/73265 , H01L2924/15153 , H01L2924/00014 , H01L2924/00
摘要： A power module (10) having at least two mutually electrically insulating layer, arranged one on top of the other, of conductor tracks (40, 60) conducting anti-parallel currents.
摘要翻译：功率模块（10）具有至少两个相互电绝缘的层，一个位于另一个之上地布置有导电反向并联电流的导体线路（40,60）。

78. 发明申请

WO2016184645A1 METHOD FOR MANUFACTURING A CIRCUIT CARRIER 审中-公开
标题翻译：制造电路载体的方法
公开(公告)号：WO2016184645A1
公开(公告)日：2016-11-24
申请号：PCT/EP2016/059236
申请日：2016-04-26
申请人： DANFOSS SILICON POWER GMBH
发明人： OSTERWALD, Frank , BICAKCI, Aylin , EISELE, Ronald
IPC分类号： H01L21/48
CPC分类号： H01L21/4846 , H01L23/142
摘要： A method for manufacturing a circuit carrier (100') having a base plate (10), an organic insulating foil (20) arranged on the base plate (10) and a metal shaped body (30) arranged on the insulating foil (20), wherein the base plate (10), insulating foil (20) and metal shaped body (30) are connected to each other by applying a quasi-hydrostatic pressure acting from the top while maintaining an even insulating foil layer thickness.
摘要翻译：一种制造具有基板（10），布置在基板（10）上的有机绝缘箔（20）和布置在绝缘箔（20）上的金属体）的电路载体（100'）的方法，其特征在于，所述基板（10），绝缘箔（20）和金属成形体（30）通过施加从顶部起作用的准静水压力相互连接，同时保持均匀的绝缘箔层厚度。

79. 发明申请

WO2016128231A1 POWER MODULE 审中-公开
标题翻译：电源模块
公开(公告)号：WO2016128231A1
公开(公告)日：2016-08-18
申请号：PCT/EP2016/051875
申请日：2016-01-29
申请人： DANFOSS SILICON POWER GMBH
发明人： EISELE, Ronald , OSTERWALD, Frank
IPC分类号： H01L23/433 , H01L23/29 , H01L23/495
CPC分类号： H01L23/49562 , H01L21/565 , H01L23/291 , H01L23/3121 , H01L23/4334 , H01L2224/32245 , H01L2224/83801 , H01L2224/8384
摘要： A power module (10) having a leadframe (20), a power semiconductor (30) arranged on the leadframe (20), a base plate (40) for dispersing heat generated by the power semiconductor (30) and a potting compound (50) surrounding the leadframe (20) and the power semiconductor (30), that physically connects the power semiconductor (30) and/or the leadframe (20) to the base plate (40).
摘要翻译：具有引线框架（20）的功率模块（10），布置在引线框架（20）上的功率半导体（30）），用于分散由功率半导体（30）产生的热量的基板（40）和灌封化合物）包围引线框架（20）和功率半导体（30），其将功率半导体（30）和/或引线框（20）物理连接到基板（40）。

80. 发明申请

WO2016050466A1 SINTERING DEVICE 审中-公开
标题翻译：烧结装置
公开(公告)号：WO2016050466A1
公开(公告)日：2016-04-07
申请号：PCT/EP2015/070617
申请日：2015-09-09
申请人： DANFOSS SILICON POWER GMBH
发明人： OSTERWALD, Frank , EISELE, Ronald , BECKER, Martin , PAULSEN, Lars , RUDZKI, Jacek , ULRICH, Holger
IPC分类号： H01L21/67 , H01L21/60
CPC分类号： H01L24/75 , B22F3/14 , B22F5/00 , B22F2998/10 , H01L24/83 , H01L2224/32225 , H01L2224/75251 , H01L2224/75252 , H01L2224/7531 , H01L2224/75315 , H01L2224/75316 , H01L2224/75317 , H01L2224/75318 , H01L2224/7532 , H01L2224/75704 , H01L2224/75821 , H01L2224/75824 , H01L2224/7598 , H01L2224/83203 , H01L2224/83209 , H01L2224/8384
摘要： Sintering device (10) for sintering at least one electronic assembly (BG), having a lower die (20) and an upper die (30) which is slidable towards the lower die (20), or a lower die (20) which is slidable towards the upper die (30), wherein the lower die (20) forms a support for the assembly (BG) to be sintered and the upper die (30) comprises a receptacle which receives a pressure pad (32) for exerting pressure directed towards the lower die (20) and which comprises a delimitation wall (34) which laterally surrounds the pressure pad (32), and wherein the delimitation wall (34) has an outer delimitation wall (34a) and an inner delimitation wall (34b) which is surrounded in an adjacent manner by the outer delimitation wall (34a), and wherein the inner delimitation wall (34b) is mounted so as to be slidable towards the outer delimitation wall (34a) and, when pressure in the direction of the upper die (30) is exerted on the pressure pad (32), is mounted so as to be slid in the direction of the lower die (20), whereby, following the placing of the inner delimitation wall (34b) on the lower die (20), the pressure pad (32) is displaceable in the direction of the lower die (20).
摘要翻译：一种用于烧结至少一个电子组件（BG）的烧结装置（10），具有可向下模具（20）滑动的下模具（20）和上模具（30），或下模具（20）可向上模具（30）滑动，其中下模具（20）形成用于要烧结的组件（BG）的支撑件，并且上模具（30）包括接收压力垫（32）的容器，用于施加压力朝向下模具（20）并且其包括侧向围绕压力垫（32）的分隔壁（34），并且其中定界壁（34）具有外部限定壁（34a）和内部限定壁（34b）其被外部限定壁（34a）相邻地包围，并且其中内部限定壁（34b）被安装成能够朝向外部限定壁（34a）滑动，并且当在上部方向上的压力模具（30）被施加在压力垫（32）上，安装成沿着方向o滑动在下模具（20）上，由此，在将内部定界壁（34b）放置在下模具（20）上之后，压力垫（32）能够在下模具（20）的方向上移动。

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