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61. 发明申请

WO2007041500A3 MCU WITH POWER SAVING MODE 审中-公开
标题翻译：具有省电模式的MCU
公开(公告)号：WO2007041500A3
公开(公告)日：2009-04-23
申请号：PCT/US2006038447
申请日：2006-09-29
申请人： PASTORELLO DOUGLAS F
发明人： PASTORELLO DOUGLAS F , HOLBERG DOUGLAS , DURBIN WILLIAM GENE , SAHU BIRANCHINATH , CHOWDHURY GOLAM R
IPC分类号： G06F1/00
CPC分类号： G06F1/3203 , H03K19/0016
摘要： A microcontroller unit includes a processor for generating a first control signal to start a comatose mode of operation for the microcontroller unit. Control logic responsive to the first control signal generates an enable signal at a first level and the control logic is further responsive to a second control signal for generating the enable signal at a second level. A voltage regulator generates regulated voltage from an input voltage. The voltage regulator shuts down to provide a zero volt regulated voltage responsive to the enable signal at the first level and powers up to provide a regulated voltage at an operating level responsive to the enable signal at the second level.
摘要翻译：微控制器单元包括用于产生第一控制信号以开始微控制器单元的昏迷模式的处理器。响应于第一控制信号的控制逻辑在第一电平产生使能信号，并且控制逻辑还响应于第二控制信号，以在第二电平产生使能信号。电压调节器从输入电压产生调节电压。电压调节器关闭，以响应于在第一电平的使能信号提供零伏调节电压，并且上电以响应于在第二电平的使能信号提供处于工作电平的调节电压。

62. 发明申请

WO2008146299A2 AN ADAPTIVE KEEPER CIRCUIT TO CONTROL DOMINO LOGIC DYNAMIC CIRCUITS USING RATE SENSING TECHNIQUE 审中-公开
标题翻译：自适应保持电路使用速率传感技术来控制多米诺逻辑动态电路
公开(公告)号：WO2008146299A2
公开(公告)日：2008-12-04
申请号：PCT/IN2007/000259
申请日：2007-06-26
申请人： INDIAN INSTITUTE OF SCIENCE , BHAT, Navakanta , JEYASINGH, Rakesh, Gnana, David
发明人： BHAT, Navakanta , JEYASINGH, Rakesh, Gnana, David
IPC分类号： H03K19/096 , H03K19/017 , H03K19/003
CPC分类号： H03K19/096 , H03K19/0016 , H03K19/00315 , H03K19/20
摘要： The present invention provides an adaptive keeper circuit to control Domino Logic Dynamic Circuits using Rate Sensing Technique to provide reduced contention and efficient process tracking at given noise robustness with less overhead in area, power and delay, said adaptive keeper comprising, keeper PMOS transistor (M1), wherein the drain of M1 is connected to wide AND-OR logic circuit; the rate controller consisting of reference rate transistor (M4), feedback PMOS transistor (M2), feedback shutoff transistor (M5), clock shutoff transistor (M6), pre-charge PMOS transistor (M3), wherein the input of the rate controller is directly connected to drain of the keeper PMOS (M1) and the output of the rate controller is directly connected to the gate of the PMOS keeper (M1),
摘要翻译：本发明提供了一种自适应保持器电路，其使用速率感测技术来控制多达逻辑逻辑动态电路，以在具有较小的面积，功率和延迟开销的给定噪声鲁棒性下提供减少的争用和有效的过程跟踪，所述自适应保持器包括保持器PMOS晶体管），其中M1的漏极连接到宽的AND-OR逻辑电路; 由参考速率晶体管（M4），反馈PMOS晶体管（M2），反馈截止晶体管（M5），时钟截止晶体管（M6），预充电PMOS晶体管（M3）组成的速率控制器，其中速率控制器的输入直接连接到保持器PMOS（M1）的漏极，并且速率控制器的输出直接连接到PMOS保持器（M1）的栅极，

63. 发明申请

WO2008131146A1 SPECIALIZED UNIVERSAL SERIAL BUS CONTROLLER 审中-公开
标题翻译：专用通用串行总线控制器
公开(公告)号：WO2008131146A1
公开(公告)日：2008-10-30
申请号：PCT/US2008/060702
申请日：2008-04-17
申请人： CYPRESS SEMICONDUCTOR CORPORATION , WRIGHT, David , KOLOKOWSKY, Steve
发明人： WRIGHT, David , KOLOKOWSKY, Steve
IPC分类号： G06F13/20
CPC分类号： H03K17/687 , H03K19/0016 , H03K19/00369
摘要： A universal serial bus controller pre-generates and stores a subset of USB commands in a memory, the pre-generated commands available for transmission to at least one USB peripheral device over universal serial bus, and transfers at least one command from the subset of pre-generated commands stored in the memory to the USB peripheral device over the universal serial bus. The universal serial bus controller may receive a response to the transferred command from the USB peripheral device over the universal serial bus, and send an acknowledgment packet to the USB peripheral device over the universal serial bus responsive to receiving the response from the USB peripheral device.
摘要翻译：通用串行总线控制器预先生成并将一些USB命令的子集存储在存储器中，预生成的命令可用于通过通用串行总线传输到至少一个USB外设，并从预先的子集传输至少一个命令通过通用串行总线将存储在存储器中的生成命令发送到USB外围设备。通用串行总线控制器可以通过通用串行总线从USB外围设备接收对传送命令的响应，并响应于接收到来自USB外围设备的响应，通过通用串行总线向USB外围设备发送确认分组。

64. 发明申请

WO2007008579A3 SOURCE TRANSISTOR CONFIGURATIONS AND CONTROL METHODS 审中-公开
标题翻译：源晶体管配置和控制方法
公开(公告)号：WO2007008579A3
公开(公告)日：2007-07-05
申请号：PCT/US2006026317
申请日：2006-07-06
申请人： ZMOS TECHNOLOGY INC , YOO SEUNG-MOON , YOO JAE HOON , SOHN JEONG DUK , SON SUNG JU , CHOI MYUNG CHAN , KIM YOUNG TAE , YOON OH SANG , HAN SAN-KYUN
发明人： YOO SEUNG-MOON , YOO JAE HOON , SOHN JEONG DUK , SON SUNG JU , CHOI MYUNG CHAN , KIM YOUNG TAE , YOON OH SANG , HAN SAN-KYUN
IPC分类号： H01L29/00
CPC分类号： H03K19/0016 , G11C7/1045 , G11C11/4074 , G11C11/4076 , G11C2207/2227
摘要： Source transistor configurations are described for reducing leakage and delay within integrated circuits. Virtual power and ground nodes are supported with the use of stacked transistor configurations, such as a two transistor stack between a first virtual supply connection and VSS, and a second virtual supply connection and VDD. Gate drives of these stacked transistors are modulated with different voltage levels in response to the operating power mode of the circuit, for example active mode, active-standby mode, and deep power-down mode. Means for driving these source stacks are described. In one embodiment separate virtual nodes are adapted for different types of circuits, such as buffers, row address strobe, and column address strobe. Other techniques, such as directional placement of the transistors is also described.
摘要翻译：描述了源晶体管配置以减少集成电路内的泄漏和延迟。虚拟电源和接地节点通过使用堆叠晶体管配置（如第一个虚拟电源连接和VSS之间的双晶体管堆栈），第二个虚拟电源连接和VDD来支持。响应于电路的工作功率模式，例如激活模式，激活待机模式和深度掉电模式，这些堆叠晶体管的栅极驱动器被调制为具有不同电压电平。描述了驱动这些源码堆的手段。在一个实施例中，单独的虚拟节点适用于不同类型的电路，诸如缓冲器，行地址选通和列地址选通。还描述了其他技术，例如晶体管的定向放置。

65. 发明申请

WO2005114667A3 INTERNAL VOLTAGE GENERATOR SCHEME AND POWER MANAGEMENT METHOD 审中-公开
标题翻译：内部电压发生器方案和电源管理方法
公开(公告)号：WO2005114667A3
公开(公告)日：2007-03-01
申请号：PCT/US2005016008
申请日：2005-05-06
申请人： ZMOS TECHNOLOGY INC , CHOI MYUNG CHAN
发明人： CHOI MYUNG CHAN
IPC分类号： G05F1/10 , G05F1/46 , G05F3/02 , G05F3/16 , G05F3/20 , G11C5/00 , G11C5/14 , H02M3/07 , H03K17/12 , H03K17/30 , H03K19/00
CPC分类号： H03K17/122 , G05F1/465 , G11C5/145 , H02M3/073 , H02M2003/077 , H03K17/302 , H03K19/0016
摘要： Apparatus and method for generating internal voltages (IVCC) within an integrated circuit. Current drivers are configured to pass current from external sources (EVCC) to internal power lines (IVCC) in response to circuit power needs and operating mode (e.g., active, stand-by, deep power down). Single current drivers (Fig. 2-Fig. 4) can be modulated on one or more internal supply lines (IVCC), preferably in response to comparing (with AMP2 - AMP4) the internal voltage supply line (IVCC) with a reference voltage (Vref2-VreF3). Additional embodiments describe parallel current drivers (MN1-MN4 and MP1-MP4 of Fig. 5), preferably configured with differing current carrying capacity, switched singly or in combinations to control internal voltage supply line power (IVSS1, IVSS2, IVCCl, or IVCC2) in response to the operating mode of the integrated circuit (state of signals C1-C22, and C1B-C22). The invention is directed toward reducing both power dissipation and current leakage, especially under stand-by and power-down operating modes.
摘要翻译：用于在集成电路内产生内部电压（IVCC）的装置和方法。电流驱动器被配置为响应于电路功率需求和操作模式（例如，活动，待机，深度断电）将电流从外部源（EVCC）传递到内部电力线（IVCC）。单电流驱动器（图2 - 图4）可以在一个或多个内部电源线（IVCC）上进行调制，优选地响应于（与AMP2-AMP4）内部电压供应线（IVCC）与参考电压（ VREF2，VREF3）。另外的实施例描述了并联电流驱动器（图5的MN1-MN4和MP1-MP4），优选地被配置为具有不同的载流能力，单独或组合地切换以控制内部电压供应线路功率（IVSS1，IVSS2，IVCC1或IVCC2）响应于集成电路的工作模式（信号C1-C22和C1B-C22的状态）。本发明旨在减少功耗和电流泄漏，特别是在待机和断电操作模式下。

66. 发明申请

WO2006075768A1 容量負荷駆動方法、容量負荷駆動装置、および液晶表示装置审中-公开
标题翻译：电力负载驱动方法，电力负载驱动装置和液晶显示装置
公开(公告)号：WO2006075768A1
公开(公告)日：2006-07-20
申请号：PCT/JP2006/300570
申请日：2006-01-11
申请人：ローム株式会社 , 丸尾明政
发明人：丸尾明政
IPC分类号： H03K17/00 , G09G3/20 , G09G3/36
CPC分类号： G09G3/3692 , G09G3/2014 , G09G3/3681 , G09G2310/0297 , G09G2310/06 , G09G2330/023 , H03K19/0016
摘要：容量負荷の一端の電位を、第１電源電位から第２電源電位へ、あるいはその逆に切り替えるに際に、第１電源電位と第２電源電位との所定の中間電の電位点に、所定時間だけ接続する。これにより、大きなキャパシタンスを持つ電荷蓄積用キャパシタを設けることなく、充放電時の電流を小さくして、容量負荷への電源電位の変動を小さくするとともに、消費電力を低減する。
摘要翻译：当电容性负载结束时的电位从第一电源电位切换到第二电源电位或反之亦然时，它连接到第一和第二电源电位之间的预定的中间电位点一段预定时间段。这可以减少在充电或放电期间的电流，电容性负载的电源电位的变化以及功率消耗，而不需要提供具有大电容的任何电荷存储电容器。

67. 发明申请

WO2006058559A1 APPARATUS AND METHOD FOR REDUCING POWER CONSUMPTION USING SELECTIVE POWER GATING 审中-公开
标题翻译：使用选择功率增益降低功耗的装置和方法
公开(公告)号：WO2006058559A1
公开(公告)日：2006-06-08
申请号：PCT/EP2004/014917
申请日：2004-11-30
申请人： FREESCALE SEMICONDUCTOR, INC. , PRIEL, Michael , KUZMIN, Dan , ZIMIN, Michael
发明人： PRIEL, Michael , KUZMIN, Dan , ZIMIN, Michael
IPC分类号： H03K19/00
CPC分类号： H03K19/0016
摘要： A method (200) for reducing power consumption of transistor-based circuit, the method including receiving (230) a low power mode indication; determining (240) whether to supply power to at least a portion of the transistor-based circuit in response to a reset value of the transistor-based circuit and a state of the transistor-based circuit prior the receiving of the low power mode indication, and selectively providing (250) power to at least a portion of the transistor-based circuit. An apparatus (200) for reducing power consumption of a transistor-based circuit (100), the apparatus being connected to the transistor-based circuit, and being adapted to receive a low power mode indication, wherein the apparatus includes: means (38) for determining whether to supply power to at least a portion of the transistor-based circuit in response a state of the transistor-based circuit prior the receiving of the low power mode indication; and means for power gating (40, 42), adapted to selectively provide power to at least a portion of the transistor-based circuit in response to the determination.
摘要翻译：一种用于降低基于晶体管的电路的功耗的方法（200），该方法包括接收（230）低功率模式指示; 确定（240）是否响应于基于晶体管的电路的复位值和在接收到低功率模式指示之前的基于晶体管的电路的状态来向基于晶体管的电路的至少一部分供电，以及选择性地向所述基于晶体管的电路的至少一部分提供（250）功率。一种用于降低基于晶体管的电路（100）的功耗的装置（200），所述装置连接到基于晶体管的电路，并且适于接收低功率模式指示，其中所述装置包括：装置（38）用于在接收到低功率模式指示之前响应于基于晶体管的电路的状态来确定是否向所述基于晶体管的电路的至少一部分供电; 以及用于电源门控（40,42）的装置，适于响应于所述确定而选择性地向所述基于晶体管的电路的至少一部分提供电力。

68. 发明申请

WO2006002316A1 INPUT ENABLE/DISABLE CIRCUIT 审中-公开
标题翻译：输入使能/禁止电路
公开(公告)号：WO2006002316A1
公开(公告)日：2006-01-05
申请号：PCT/US2005/022262
申请日：2005-06-21
申请人： TEXAS INSTRUMENTS INCORPORATED , HINTERSCHER, Eugene, B.
发明人： HINTERSCHER, Eugene, B.
IPC分类号： H03K19/20
CPC分类号： H03K19/0016 , H03K5/15
摘要： An integrated circuit (200) includes an input circuit (206), an output circuit (214), and a functional circuit (208) that processes an input received from input circuit (206) to provide an output to output circuit (214). Input and output circuits (206, 214) are enabled or disabled by a control signal OE to reduce power consumption during periods of inactivity. A control circuit (224) controls application of control signal OE so that input circuit (206) is enabled, to enable processing of the input by functional circuit (208) before output circuit (214) is enabled, thereby preventing a glitch in the output signal due to a race condition. Control circuit (224) controls application of control signal OE so that output circuit (214) is disabled prior to disablement of input circuit (206).
摘要翻译：集成电路（200）包括输入电路（206），输出电路（214）和处理从输入电路（206）接收的输入以向输出电路（214）提供输出的功能电路（208）。输入和输出电路（206,214）由控制信号OE启用或禁用，以在不活动期间减少功耗。控制电路（224）控制控制信号OE的施加，使得输入电路（206）被使能，以使能在输出电路（214）被使能之前由功能电路（208）输入的处理，从而防止输出中的毛刺信号由于竞争条件。控制电路（224）控制控制信号OE的施加，使得输出电路（214）在禁止输入电路（206）之前被禁用。

69. 发明申请

WO2005094517A2 LEAKAGE CURRENT REDUCTION METHOD 审中-公开
标题翻译：漏电流减少方法
公开(公告)号：WO2005094517A2
公开(公告)日：2005-10-13
申请号：PCT/US2005/009830
申请日：2005-03-23
申请人： TEXAS INSTRUMENTS INCORPORATED , MAIR, Hugh , DANG, Luan, A. , DENG, Xiaowei , JAMISON, George, B. , TRAN, Tam, M. , YANG, Shyh-Horng , SCOTT, David, B.
发明人： MAIR, Hugh , DANG, Luan, A. , DENG, Xiaowei , JAMISON, George, B. , TRAN, Tam, M. , YANG, Shyh-Horng , SCOTT, David, B.
IPC分类号： H03K17/16 , H03K19/00 , H03K19/003
CPC分类号： H03K19/00361 , H03K19/0016
摘要： The method for powering down a circuit for a data retention mode includes: changing a supply voltage node from an active power voltage level to an inactive power level; coupling a source of a P channel device to the supply voltage node; providing a retaining power supply voltage level to a back gate of the P channel device; changing a drain voltage of the P channel device to a reference voltage level, wherein the reference voltage level is different from the retaining power supply voltage level; and changing a gate voltage of the P channel device to the reference voltage level.
摘要翻译：用于为数据保持模式断电的方法包括：将电源电压节点从有功功率电压电平改变为无功功率电平; 将P沟道器件的源极耦合到电源电压节点; 向P通道装置的后门提供保持电源电压电平; 将所述P沟道器件的漏极电压改变为参考电压电平，其中所述参考电压电平不同于所述保持电源电压电平; 并将P沟道器件的栅极电压改变到参考电压电平。

70. 发明申请

WO2005024910A3 APPARATUS AND METHOD FOR INTEGRATED CIRCUIT POWER MANAGEMENT 审中-公开
标题翻译：集成电路电源管理的装置和方法
公开(公告)号：WO2005024910A3
公开(公告)日：2005-05-19
申请号：PCT/US2004029717
申请日：2004-09-09
申请人： EISENSTADT ROBERT , SHIELL JON H
发明人： EISENSTADT ROBERT , SHIELL JON H
IPC分类号： G06F17/50 , H01L20060101
CPC分类号： G06F17/505 , G06F2217/78 , H03K19/0016 , H03K19/00346 , H03K19/17736 , H03K19/17744 , H03K19/17784
摘要： Methods and/or associated devices and/or systems for providing power management in electronic circuits, including custom ICs, programmable logic devices (Fig.2), and application specific integrated circuits (ASICs) places portions of various power management solutions in the 1/O ring or in VO macros (Fig.2). The invention has numerous specific embodiments and applications to a wide variety of 1Cs and logic or other circuit design components including circuit modules, software descriptions of circuit modules and/or design or simulation or test systems for circuit development.
摘要翻译：包括定制IC，可编程逻辑器件（图2）和专用集成电路（ASIC）在电子电路中提供电源管理的方法和/或相关设备和/或系统将各种电源管理解决方案的部分放置在1 / O环或VO宏（图2）。本发明具有许多具体实施例和应用于各种各样的1C和逻辑或其他电路设计组件，包括电路模块，电路模块的软件描述和/或用于电路开发的设计或仿真或测试系统。

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