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51. 发明申请

WO2012064677A1 BIMODAL BRANCH PREDICTOR ENCODED IN A BRANCH INSTRUCTION 审中-公开
标题翻译：分支指令编码的双模分支预测
公开(公告)号：WO2012064677A1
公开(公告)日：2012-05-18
申请号：PCT/US2011/059658
申请日：2011-11-07
申请人： QUALCOMM INCORPORATED , VENKUMAHANTI, Suresh K. , CODRESCU, Lucian , SHANNON, Stephen R. , WANG, Lin , JONES, Phillip M. , PALAL, Daisy T. , TU, Jiajin
发明人： VENKUMAHANTI, Suresh K. , CODRESCU, Lucian , SHANNON, Stephen R. , WANG, Lin , JONES, Phillip M. , PALAL, Daisy T. , TU, Jiajin
IPC分类号： G06F9/38
CPC分类号： G06F9/3844
摘要： Each branch instruction having branch prediction support has branch prediction bits in architecture specified bit positions in the branch instruction. An instruction cache supports modifying the branch instructions with updated branch prediction bits that are dynamically determined when the branch instruction executes.
摘要翻译：具有分支预测支持的每个分支指令在分支指令中的架构指定的位位置具有分支预测位。指令高速缓存支持使用在分支指令执行时动态确定的更新的分支预测位修改分支指令。

52. 发明申请

WO2010107774A2 REAL-TIME MULTITHREADED SCHEDULER AND SCHEDULING METHOD 审中-公开
标题翻译：实时多路调度和调度方法
公开(公告)号：WO2010107774A2
公开(公告)日：2010-09-23
申请号：PCT/US2010/027453
申请日：2010-03-16
申请人： QUALCOMM INCORPORATED , PLONDKE, Erich, James , CODRESCU, Lucian
发明人： PLONDKE, Erich, James , CODRESCU, Lucian
IPC分类号： G06F9/06 , G06F9/30 , G06F13/14 , G06F9/44
CPC分类号： G06F9/3851 , G06F9/4812 , G06F9/4881
摘要： In a particular embodiment, a method is disclosed that includes receiving an interrupt at a first thread, the first thread including a lowest priority thread of a plurality of executing threads at a processor at a first time. The method also includes identifying a second thread, the second thread including a lowest priority thread of a plurality of executing threads at a processor at a second time. The method further includes directing a subsequent interrupt to the second thread.
摘要翻译：在特定实施例中，公开了一种包括在第一线程处接收中断的方法，所述第一线程在第一时间包括处理器处的多个执行线程的最低优先级线程。所述方法还包括识别第二线程，所述第二线程在第二时间包括处理器处的多个执行线程的最低优先级线程。该方法还包括将后续中断引导到第二线程。

53. 发明申请

WO2008061086A3 DIGITAL SIGNAL PROCESSOR DEBUGGING DURING POWER TRANSITIONS 审中-公开
标题翻译：数字信号处理器在功率转换期间调试
公开(公告)号：WO2008061086A3
公开(公告)日：2009-09-24
申请号：PCT/US2007084523
申请日：2007-11-13
申请人： QUALCOMM INC , CODRESCU LUCIAN , ANDERSON WILLIAM C , VENKUMAHANTI SURESH , GIANNINI LOUIS ACHILLE , PYLA MANOJKUMAR , CHEN XUFENG
发明人： CODRESCU LUCIAN , ANDERSON WILLIAM C , VENKUMAHANTI SURESH , GIANNINI LOUIS ACHILLE , PYLA MANOJKUMAR , CHEN XUFENG
IPC分类号： G06F1/32 , G06F11/36
CPC分类号： G06F1/3203 , G06F11/362 , G06F11/3656
摘要： Techniques for the design and use of a digital signal processor, including (but not limited to) for processing transmissions in a communications (e.g., CDMA) system. A method and system control transferring data between debugging registers and digital signal processor processes in association with a power transition sequence of the digital signal processor. In a digital signal processor, debugging registers associate with the core processor process and the debugging process. Control bits control transferring data among the debugging registers, the core processor process and the debugging process. The control bit prevents transferring data among the debugging registers, the core processor process and the debugging process in the event of a power transition sequence. Control bits also prevent a power transition sequence of the digital signal processor in the event of transferring data among the debugging registers and the core processor process or the debugging process.
摘要翻译：用于设计和使用数字信号处理器的技术，包括（但不限于）用于处理通信（例如，CDMA）系统中的传输。一种与数字信号处理器的功率转换序列相关联的在调试寄存器和数字信号处理器处理之间传送数据的方法和系统控制。在数字信号处理器中，调试寄存器与核心处理器进程和调试过程相关联。控制位控制在调试寄存器，核心处理器进程和调试过程之间传输数据。控制位防止在电源转换序列的情况下在调试寄存器，核心处理器进程和调试过程之间传输数据。在调试寄存器和核心处理器处理或调试过程之间传送数据的情况下，控制位还可以防止数字信号处理器的电源转换序列。

54. 发明申请

WO2009067590A1 SYSTEM AND METHOD OF SELECTIVELY ACCESSING A REGISTER FILE 审中-公开
标题翻译：选择一个寄存器文件的系统和方法
公开(公告)号：WO2009067590A1
公开(公告)日：2009-05-28
申请号：PCT/US2008/084181
申请日：2008-11-20
申请人： QUALCOMM Incorporated , VENKUMAHANTI, Suresh K , CODRESCU, Lucian , KRITHIVASAN, Shankar , SHEN, Jian , WANG, Lin
发明人： VENKUMAHANTI, Suresh K , CODRESCU, Lucian , KRITHIVASAN, Shankar , SHEN, Jian , WANG, Lin
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30101 , G06F9/30072 , G06F9/30112 , G06F9/30141 , G06F9/3016 , G06F9/3824
摘要： In a particular embodiment, a method is disclosed that includes identifying a first block of bits within a result to be written to a destination register by an execution unit. The result includes a plurality of bits having the first block of bits and a second block of bits. The first block of bits has a value of zero. The method further includes providing an encoded bit value representing the first block of bits to a control register and selectively writing the second block of bits, but not the first block of bits, to the destination register. The destination register is sized to receive the first and second blocks of bits.
摘要翻译：在特定实施例中，公开了一种方法，其包括通过执行单元识别要写入到目的地寄存器的结果内的第一比特块。结果包括具有第一比特块和第二比特块的多个比特。第一个位块的值为零。该方法还包括向控制寄存器提供表示第一比特位的编码比特值，并将第二比特块而不是第一比特块写入目的寄存器。目的地寄存器的大小适于接收第一和第二位块。

55. 发明申请

WO2009032936A1 SYSTEM AND METHOD OF EXECUTING INSTRUCTIONS IN A MULTI-STAGE DATA PROCESSING PIPELINE 审中-公开
标题翻译：在多级数据处理管道中执行指令的系统和方法
公开(公告)号：WO2009032936A1
公开(公告)日：2009-03-12
申请号：PCT/US2008/075270
申请日：2008-09-04
申请人： QUALCOMM Incorporated , INGLE, Ajay Anant , CODRESCU, Lucian , VENKUMAHANTI, Suresh
发明人： INGLE, Ajay Anant , CODRESCU, Lucian , VENKUMAHANTI, Suresh
IPC分类号： G06F9/38
CPC分类号： G06F9/3851 , G06F9/3867
摘要： A device is disclosed that includes an instruction execution pipeline having multiple stages for executing an instruction. The device also includes a control logic circuit coupled to the instruction execution pipeline. The control logic circuit is adapted to skip at least one stage of the instruction execution pipeline during execution of the instruction. The control logic circuit is also adapted to execute at least one non-skipped stage during execution of the decoded instruction.
摘要翻译：公开了一种包括具有用于执行指令的多个级的指令执行流水线的装置。该装置还包括耦合到指令执行管线的控制逻辑电路。控制逻辑电路适于在执行指令期间跳过指令执行流水线的至少一个级。控制逻辑电路还适于在执行解码的指令期间执行至少一个非跳过级。

56. 发明申请

WO2008061067A3 NON-INTRUSIVE, THREAD-SELECTIVE, DEBUGGING METHOD AND SYSTEM FOR A MULTI-THREADED DIGITAL SIGNAL PROCESSOR 审中-公开
标题翻译：用于多通道数字信号处理器的无扰动，螺纹选择，调试方法和系统
公开(公告)号：WO2008061067A3
公开(公告)日：2008-07-24
申请号：PCT/US2007084456
申请日：2007-11-12
申请人： QUALCOMM INC , CODRESCU LUCIAN , ANDERSON WILLIAM C , VENKUMAHANTI SURESH , GIANNINI LOUIS ACHILLE , PYLA MANOJKUMAR , CHEN XUFENG
发明人： CODRESCU LUCIAN , ANDERSON WILLIAM C , VENKUMAHANTI SURESH , GIANNINI LOUIS ACHILLE , PYLA MANOJKUMAR , CHEN XUFENG
IPC分类号： G06F11/36
CPC分类号： G06F9/3005 , G06F9/3009 , G06F9/3851 , G06F11/362
摘要： Techniques for the design and use of a digital signal processor, including (but not limited to) for processing transmissions in a communications (e.g., CDMA) system. The disclosed method and system provide for processing instructions in a multi-threaded process including the use of breakpoint instructions for generating debugging event(s). Generating a debugging event occurs in response to the execution of breakpoint instructions and executes debugging instructions in response to the debugging event. The debugging instructions debug processing instructions in the multi-threaded processor by transitioning at least one or more threads into a debugging mode. The disclosure generates a debugging return for reporting the executing debugging instructions in the subset of the threads of the multi-threaded processor.
摘要翻译：用于设计和使用数字信号处理器的技术，包括（但不限于）用于处理通信（例如CDMA）系统中的传输。所公开的方法和系统提供了在多线程过程中处理指令，包括使用断点指令来产生调试事件。响应于断点指令的执行而产生调试事件，并根据调试事件执行调试指令。调试指令通过将至少一个或多个线程转变为调试模式来调试多线程处理器中的处理指令。本公开生成用于报告多线程处理器的线程的子集中的执行调试指令的调试返回。

57. 发明申请

WO2006110905A8 SYSTEM AND METHOD OF USING A PREDICATE VALUE TO ACCESS A REGISTER FILE 审中-公开
标题翻译：使用预测值访问寄存器文件的系统和方法
公开(公告)号：WO2006110905A8
公开(公告)日：2008-02-21
申请号：PCT/US2006014173
申请日：2006-04-11
申请人： QUALCOMM INC , AHMED MUHAMMAD , PLONDKE ERICH , CODRESCU LUCIAN , ANDERSON WILLIAM C
发明人： AHMED MUHAMMAD , PLONDKE ERICH , CODRESCU LUCIAN , ANDERSON WILLIAM C
IPC分类号： G06F9/38
CPC分类号： G06F9/3842 , G06F9/3851 , G06F9/3885
摘要： A processor device is disclosed and includes a memory unit and at least one interleaved multi-threading instruction pipeline. The interleaved multi-threading instruction pipeline utilizes a number of clock cycles that is less than an instruction issue rate for each of a plurality of program threads that are stored within the memory unit. The memory unit includes six instruction caches. Further, the processor device includes six register files and each of the six register files is associated with one of the six instruction caches. Each of the plurality of program threads is associated with one of the six register files. Further, each of the six program threads includes a plurality of instructions and each of the plurality of instructions is stored within one of the six instruction caches of the memory.
摘要翻译：公开了处理器设备，并且包括存储器单元和至少一个交错多线程指令流水线。交错多线程指令流水线利用小于存储在存储器单元内的多个程序线程中的每一个的指令发布速率的多个时钟周期。存储单元包括六个指令高速缓存。此外，处理器设备包括六个寄存器文件，六个寄存器文件中的每一个与六个指令高速缓存中的一个相关联。多个程序线程中的每一个与六个寄存器文件中的一个相关联。此外，六个程序线程中的每一个包括多个指令，并且多个指令中的每一个被存储在存储器的六个指令高速缓存之一中。

58. 发明申请

WO2007134013A2 METHOD AND SYSTEM TO COMBINE CORRESPONDING HALF WORD UNITS FROM MULTIPLE REGISTER UNITS WITHIN A MICROPROCESSOR 审中-公开
标题翻译：在微处理器中从多个寄存器单元组合相应的半字单元的方法和系统
公开(公告)号：WO2007134013A2
公开(公告)日：2007-11-22
申请号：PCT/US2007/068394
申请日：2007-05-07
申请人： QUALCOMM Incorporated , ZENG, Mao , CODRESCU, Lucian
发明人： ZENG, Mao , CODRESCU, Lucian
IPC分类号： G06F9/315
CPC分类号： G06F9/30032 , G06F9/30025 , G06F9/30036
摘要： A method and system to combine corresponding half word units from multiple register units within a microprocessor, such as, for example, a digital signal processor, during execution of a single instruction are described. An instruction to combine predetermined disparate source register units from a register file structure is received within a processing unit. The instruction is then executed to combine corresponding half word units from the source register units and to input the half word units into respective portions of a resulting destination register unit. During the execution of the instruction, the predetermined source register units are identified and corresponding most significant half word units and associated data are retrieved from the identified register units. The retrieved half word units are further combined and input into a respective most significant portion of a resulting destination register unit. Similarly, corresponding least significant half word units and associated data are retrieved from the identified register units. The retrieved half word units are further combined and input into a respective least significant portion of a resulting destination register unit. Finally, the resulting destination register unit is stored into the register file structure for further processing.
摘要翻译：描述了在执行单个指令期间组合微处理器内的多个寄存器单元（例如数字信号处理器）的相应半字单元的方法和系统。在处理单元内接收从寄存器文件结构组合预定的不同的源寄存器单元的指令。然后执行指令以组合来自源寄存器单元的对应的半字单元，并将半字单元输入到所得到的目标寄存器单元的相应部分。在执行指令期间，识别预定的源寄存器单元，并且从所识别的寄存器单元检索对应的最高有效半字单元和相关联的数据。所获取的半字单元被进一步组合并输入到所得到的目标寄存器单元的相应最高有效部分。类似地，从所识别的寄存器单元检索相应的最低有效半字单元和相关数据。所检索的半字单元被进一步组合并输入到所得到的目标寄存器单元的相应的最低有效部分。最后，将所得到的目标寄存器单元存储到寄存器文件结构中以进一步处理。

59. 发明申请

WO2007134011A3 INSTRUCTION FOR PRODUCING TWO INDEPENDENT SUMS OF ABSOLUTE DIFFERENCES 审中-公开
公开(公告)号：WO2007134011A3
公开(公告)日：2007-11-22
申请号：PCT/US2007/068389
申请日：2007-05-07
申请人： QUALCOMM INCORPORATED , ZENG, Mao , CODRESCU, Lucian
发明人： ZENG, Mao , CODRESCU, Lucian
IPC分类号： H04N7/36 , G06F9/302
摘要： Method and apparatus for performing two independent sum-of-absolute-difference (SAD) operations when receiving a single instruction (505, 705) is provided. The two operations may be performed in parallel. The operations process values stored in two source registers (405, 410) and the results are stored to a destination register (425). The source and destination registers each have two independently accessible sections, whereby a first SAD operation (401) can access a first section while a second independent SAD operation (402) can simultaneously access a second section of the register. The first SAD operation is performed on values in a first section of the source registers, the result being stored to a first section of the destination register. The second SAD operation is performed on values in a second section of the source registers, the result being stored to a second section of the destination register. The values may comprise pixel values.

60. 发明申请

WO2007134011A2 INSTRUCTION FOR PRODUCING TWO INDEPENDENT SUMS OF ABSOLUTE DIFFERENCES 审中-公开
标题翻译：生产两个独立的绝对差异的指令
公开(公告)号：WO2007134011A2
公开(公告)日：2007-11-22
申请号：PCT/US2007068389
申请日：2007-05-07
申请人： QUALCOMM INC , ZENG MAO , CODRESCU LUCIAN
发明人： ZENG MAO , CODRESCU LUCIAN
CPC分类号： H04N19/43
摘要： Method and apparatus for performing two independent sum-of-absolute-difference (SAD) operations when receiving a single instruction (505, 705) is provided. The two operations may be performed in parallel. The operations process values stored in two source registers (405, 410) and the results are stored to a destination register (425). The source and destination registers each have two independently accessible sections, whereby a first SAD operation (401) can access a first section while a second independent SAD operation (402) can simultaneously access a second section of the register. The first SAD operation is performed on values in a first section of the source registers, the result being stored to a first section of the destination register. The second SAD operation is performed on values in a second section of the source registers, the result being stored to a second section of the destination register. The values may comprise pixel values.
摘要翻译：提供了当接收单个指令（505,705）时执行两个独立的绝对差值（SAD）操作的方法和装置。这两个操作可以并行执行。存储在两个源寄存器（405,410）中的操作处理值和结果被存储到目的地寄存器（425）。源寄存器和目标寄存器各具有两个可独立访问的部分，由此第一SAD操作（401）可以访问第一部分，而第二独立的SAD操作（402）可以同时访问寄存器的第二部分。第一个SAD操作是根据源寄存器的第一部分中的值执行的，结果被存储到目标寄存器的第一部分。第二个SAD操作是在源寄存器的第二部分中的值上执行的，结果被存储到目标寄存器的第二部分。这些值可以包括像素值。

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