专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

51. 发明申请

WO2014093347A1 GESTURE PRE-PROCESSING OF VIDEO STREAM USING A MARKERED REGION 审中-公开
标题翻译：使用标记区域对视频流进行预处理
公开(公告)号：WO2014093347A1
公开(公告)日：2014-06-19
申请号：PCT/US2013/074135
申请日：2013-12-10
申请人： INTEL CORPORATION , BURR, Jeremy
发明人： BURR, Jeremy
IPC分类号： G06T7/20 , G06F3/01
CPC分类号： G06F3/017 , G06F3/0304 , G06K9/00228 , G06K9/00234 , G06K9/00355 , G06K9/00993 , G06K9/2054
摘要： Techniques are disclosed for processing a video stream to reduce platform power by employing a stepped and distributed pipeline process, wherein CPU-intensive processing is selectively performed. The techniques are particularly well-suited for hand-based navigational gesture processing. In one example case, for instance, the techniques are implemented in a computer system wherein initial threshold detection (image disturbance) and optionally user presence (hand image) processing components are proximate to or within the system's camera, and the camera is located in or proximate to the system's primary display. In some cases, image processing and communication of pixel information between various processing stages which lies outside a markered region is suppressed. In some embodiments, the markered region is aligned with, a mouse pad or designated desk area or a user input device such as a keyboard. Pixels evaluated by the system can be limited to a subset of the markered region.
摘要翻译：公开了用于处理视频流以降低平台功率的技术，其中采用阶梯式和分布式流水线处理，其中选择性地执行CPU密集型处理。这些技术特别适用于基于手的导航手势处理。在一个示例情况下，例如，这些技术在计算机系统中实现，其中初始阈值检测（图像干扰）和可选地用户存在（手图像）处理部件靠近或在系统的相机内，并且相机位于或靠近系统的主显示。在某些情况下，抑制位于标记区域之外的各处理级之间的像素信息的图像处理和通信。在一些实施例中，标记区域与鼠标垫或指定的桌面区域或诸如键盘的用户输入设备对准。由系统评估的像素可以限于标记区域的子集。

52. 发明申请

WO2013154574A1 CONVERSION OF STRAIN-INDUCING BUFFER TO ELECTRICAL INSULATOR 审中-公开
标题翻译：应变诱导缓冲器对电绝缘子的转换
公开(公告)号：WO2013154574A1
公开(公告)日：2013-10-17
申请号：PCT/US2012/033472
申请日：2012-04-13
申请人： INTEL CORPORATION , CAPPELLANI, Annalisa , LE, Van H. , GLASS, Glenn A. , KUHN, Kelin J. , CEA, Stephen M.
发明人： CAPPELLANI, Annalisa , LE, Van H. , GLASS, Glenn A. , KUHN, Kelin J. , CEA, Stephen M.
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/66795 , H01L21/02233 , H01L21/02236 , H01L21/02238 , H01L21/02241 , H01L21/02255 , H01L21/02304 , H01L21/02439 , H01L21/0245 , H01L21/02455 , H01L21/02488 , H01L21/02532 , H01L21/306 , H01L21/76 , H01L21/7624 , H01L21/76283 , H01L29/0603 , H01L29/0642 , H01L29/0653 , H01L29/0657 , H01L29/1054 , H01L29/7378 , H01L29/785 , H01L33/12 , H05K1/18
摘要： Techniques are disclosed for converting a strain-inducing semiconductor buffer layer into an electrical insulator at one or more locations of the buffer layer, thereby allowing an above device layer to have a number of benefits, which in some embodiments include those that arise from being grown on a strain-inducing buffer and having a buried electrical insulator layer. For instance, having a buried electrical insulator layer (initially used as a strain-inducing buffer during fabrication of the above active device layer) between the Fin and substrate of a non-planar integrated transistor circuit may simultaneously enable a low-doped Fin with high mobility, desirable device electrostatics and elimination or otherwise reduction of substrate junction leakage. Also, the presence of such an electrical insulator under the source and drain regions may further significantly reduce junction leakage. In some embodiments, substantially the entire buffer layer is converted to an electrical insulator.
摘要翻译：公开了用于将应变诱导半导体缓冲层转变成缓冲层的一个或多个位置处的电绝缘体的技术，从而允许上述器件层具有许多益处，其在一些实施例中包括从生长出来的那些在应变诱导缓冲器上并具有埋入的电绝缘体层。例如，在非平面集成晶体管电路的Fin和衬底之间具有埋入的电绝缘体层（最初用作制造上述有源器件层期间的应变诱导缓冲器）可以同时使得具有高的低掺杂Fin 移动性，期望的器件静电，以及消除或以其他方式减少衬底结泄漏。此外，源极和漏极区域下的这种电绝缘体的存在可以进一步显着减少结漏电。在一些实施例中，基本上整个缓冲层被转换成电绝缘体。

53. 发明申请

WO2013101204A1 SELF-ENCLOSED ASYMMETRIC INTERCONNECT STRUCTURES 审中-公开
标题翻译：自封不对称互连结构
公开(公告)号：WO2013101204A1
公开(公告)日：2013-07-04
申请号：PCT/US2011/068159
申请日：2011-12-30
申请人： INTEL CORPORATION , BOYANOV, Boyan
发明人： BOYANOV, Boyan
IPC分类号： H01L21/28
CPC分类号： H01L23/522 , H01L21/768 , H01L21/76804 , H01L21/76829 , H01L21/76834 , H01L21/76849 , H01L21/76883 , H01L21/76897 , H01L23/5226 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Techniques are disclosed that enable improved shorting margin between unlanded conductive interconnect features and neighboring conductive features. The techniques provided are particularly useful, for instance, when lithography registration errors cause neighboring conductive features to be physically closer than expected, but can also be used when such proximity is intentional. In some embodiments, the techniques can be implemented using a layer of electromigration management material (EMM) and one or more insulator layers, wherein the various layers are provisioned to enable a differential etch rate. In particular, the overall etch rate of materials above the target landing pad is faster than the overall etch rate of materials above the off-target landing pad, which results in a self-enclosed conductive interconnect feature having an asymmetric taper or profile. The differential etch rate may result, for example, from configuration of the EMM layer, or from accompanying insulator layers having different etch rates.
摘要翻译：公开了能够改善未上行的导电互连特征与相邻导电特征之间的短路裕度的技术。所提供的技术特别有用，例如，当光刻注册误差导致相邻的导电特征物理上比预期的更近，但是当这种接近是有意的时也可以使用。在一些实施例中，可以使用电迁移管理材料层（EMM）和一个或多个绝缘体层来实现这些技术，其中提供各种层以实现差分蚀刻速率。特别地，目标着陆焊盘上方的材料的总体蚀刻速率比在靶外着陆焊盘上方的材料的总体蚀刻速度更快，这导致具有不对称锥度或轮廓的自封闭导电互连特征。差分蚀刻速率可以由例如EMM层的构造或者具有不同蚀刻速率的伴随的绝缘体层产生。

54. 发明申请

WO2013101107A1 DOUBLE PATTERNING LITHOGRAPHY TECHNIQUES 审中-公开
标题翻译：双重图案平铺技术
公开(公告)号：WO2013101107A1
公开(公告)日：2013-07-04
申请号：PCT/US2011/067929
申请日：2011-12-29
申请人： INTEL CORPORATION , WALLACE, Charles H. , SIVAKUMAR, Swaminathan , TINGEY, Matthew L. , MUNASINGHE, Chanaka D. , RAHHAL-ORABI, Nadia M.
发明人： WALLACE, Charles H. , SIVAKUMAR, Swaminathan , TINGEY, Matthew L. , MUNASINGHE, Chanaka D. , RAHHAL-ORABI, Nadia M.
IPC分类号： H01L21/027
CPC分类号： H01L21/3088 , H01L21/0337
摘要： Techniques are disclosed for double patterning of a lithographic feature using a barrier layer between the pattern layers. In some cases, the techniques may be implemented with double patterning of a one- or two-dimensional photolithographic feature, for example. In some embodiments, the barrier layer is deposited to protect a first photoresist pattern prior to application of a second photoresist pattern thereon and/or to tailor (e.g., shrink) one or more of the critical dimensions of a trench, hole, or other etchable geometric feature to be formed in a substrate or other suitable surface via lithographic processes. In some embodiments, the techniques may be implemented to generate/print small features (e.g., less than or equal to about 100 nm) including one- and two-dimensional features/structures of varying complexity.
摘要翻译：公开了使用图案层之间的阻挡层对光刻特征进行双重图案化的技术。在一些情况下，例如，可以通过双图案化一维或二维光刻特征来实现这些技术。在一些实施例中，沉积阻挡层以在施加第二光致抗蚀剂图案之前保护第一光致抗蚀剂图案和/或定制（例如，收缩）沟槽，孔或其它可蚀刻的一个或多个临界尺寸通过光刻工艺在衬底或其它合适的表面中形成的几何特征。在一些实施例中，可以实施技术来生成/打印包括不同复杂度的一维和二维特征/结构的小特征（例如，小于或等于约100nm）。

55. 发明申请

WO2013095377A1 SELF-ALIGNED CONTACT METALLIZATION FOR REDUCED CONTACT RESISTANCE 审中-公开
标题翻译：自对准接触金属化，降低接触电阻
公开(公告)号：WO2013095377A1
公开(公告)日：2013-06-27
申请号：PCT/US2011/066134
申请日：2011-12-20
申请人： INTEL CORPORATION , GLASS, Glenn A. , MURTHY, Anand S. , GHANI, Tahir
发明人： GLASS, Glenn A. , MURTHY, Anand S. , GHANI, Tahir
IPC分类号： H01L29/78 , H01L21/28 , H01L21/336
CPC分类号： H01L27/0922 , H01L21/28185 , H01L21/28525 , H01L21/28575 , H01L21/76814 , H01L21/823814 , H01L21/823821 , H01L21/8258 , H01L23/535 , H01L27/0605 , H01L27/0924 , H01L29/0669 , H01L29/0847 , H01L29/16 , H01L29/165 , H01L29/20 , H01L29/267 , H01L29/41725 , H01L29/41783 , H01L29/41791 , H01L29/42392 , H01L29/517 , H01L29/66545 , H01L29/6659 , H01L29/66636 , H01L29/7834 , H01L29/7848 , H01L2924/0002 , H01L2924/00
摘要： Techniques are disclosed for forming low contact resistance transistor devices. A p-type germanium layer is provided between p-type source/drain regions and their respective contact metals, and an n-type III-V semiconductor material layer is provided between n-type source/drain regions and their respective contact metals. The n-type III-V semiconductor material layer may have a small bandgap (e.g.,
摘要翻译：公开了用于形成低接触电阻晶体管器件的技术。 p型锗层设置在p型源极/漏极区及其各自的接触金属之间，n型III-V半导体材料层设置在n型源极/漏极区及其各自的接触金属之间。 n型III-V族半导体材料层可能具有小的带隙（例如，<0.5eV）和/或以其它方式被掺杂以提供期望的导电性，并且p型锗层可以例如用硼掺杂。在III型V材料沉积在n型源极/漏极区域和锗覆盖的p型源极/漏极区域之后，可以执行回蚀工艺以利用n型和p型之间的高度差区域自对准接触类型，并在p型区域上露出p型锗，并在n型区域上稀薄n型III-V材料。这些技术可以用于平面和非平面晶体管架构。

56. 发明申请

WO2013074076A1 MACRO-TRANSISTOR DEVICES 审中-公开
标题翻译：宏器件设备
公开(公告)号：WO2013074076A1
公开(公告)日：2013-05-23
申请号：PCT/US2011/060652
申请日：2011-11-14
申请人： INTEL CORPORATION , HYVONEN, Sami , RIZK, Jad B. , O'MAHONY, Frank
发明人： HYVONEN, Sami , RIZK, Jad B. , O'MAHONY, Frank
IPC分类号： H01L27/00 , H01L21/768
CPC分类号： H01L27/0886 , H01L27/088 , H01L27/1211 , H01L29/42376 , H01L29/66181 , H01L29/785 , H01L29/93 , H01L29/94 , H03L7/099
摘要： Macro-transistor structures are disclosed. In some cases, the macro-transistor structures have the same number of terminals and properties similar to long-channel transistors, but are suitable for analog circuits in deep submicron technologies deep-submicron process nodes. The macro-transistor structures can be implemented, for instance, with a plurality of transistors constructed and arranged in series, and with their gates tied together, generally referred to herein as a transistor stack. One or more of the serial transistors within the stack can be implemented with a plurality of parallel transistors and/or can have a threshold voltage different that is different from the threshold voltages of other transistors in the stack. Alternatively, or in addition, one or more of the serial transistors within the macro-transistor can be statically or dynamically controlled to tune the performance characteristics of the macro-transistor. The macro-transistors can be used in numerous circuits, such as varactors, VCOs, PLLs, and tunable circuits.
摘要翻译：公开了宏观晶体管结构。在一些情况下，宏晶体管结构具有与长沟道晶体管类似的端子和性质相同的数量，但适用于深亚微米技术深亚微米工艺节点中的模拟电路。宏晶体管结构可以例如通过串联构造和布置的多个晶体管实现，并且其栅极连接在一起，这里通常称为晶体管堆叠。堆叠内的一个或多个串联晶体管可以用多个并联晶体管实现和/或可以具有不同于堆叠中其它晶体管的阈值电压的阈值电压。或者或另外，宏晶体管内的一个或多个串联晶体管可以被静态或动态地控制，以调整宏晶体管的性能特性。宏晶体管可用于许多电路，例如变容二极管，VCO，PLL和可调谐电路。

57. 发明申请

WO2013058746A1 ANTIFUSE ELEMENT UTILIZING NON-PLANAR TOPOLOGY 审中-公开
标题翻译：使用非平面拓扑学的抗体元件
公开(公告)号：WO2013058746A1
公开(公告)日：2013-04-25
申请号：PCT/US2011/056760
申请日：2011-10-18
申请人： INTEL CORPORATION , HAFEZ, Walid M. , JAN, Chia-Hong , TSAI, Curtis , PARK, Joodong , YEH, Jeng-Ya D.
发明人： HAFEZ, Walid M. , JAN, Chia-Hong , TSAI, Curtis , PARK, Joodong , YEH, Jeng-Ya D.
IPC分类号： H01L23/62 , H01L21/82 , H01L29/78
CPC分类号： H01L27/11206 , H01L21/823821 , H01L23/5252 , H01L27/0924 , H01L29/7853 , H01L2924/0002 , H01L2924/00
摘要： Techniques for providing non-volatile antifuse memory elements and other antifuse links are disclosed herein. In some embodiments, the antifuse memory elements are configured with non-planar topology such as FinFET topology. In some such embodiments, the fin topology can be manipulated and used to effectively promote lower breakdown voltage transistors, by creating enhanced-emission sites which are suitable for use in lower voltage non-volatile antifuse memory elements. In one example embodiment, a semiconductor antifuse device is provided that includes a non-planar diffusion area having a fin configured with a tapered portion, a dielectric isolation layer on the fin including the tapered portion, and a gate material on the dielectric isolation layer. The tapered portion of the fin may be formed, for instance, by oxidation, etching, and/or ablation, and in some cases includes a base region and a thinned region, and the thinned region is at least 50% thinner than the base region.
摘要翻译：本文公开了用于提供非易失性反熔丝存储元件和其它反熔丝链路的技术。在一些实施例中，反熔丝存储器元件被配置为非平面拓扑，例如FinFET拓扑。在一些这样的实施例中，可以通过产生适合用于较低电压非易失性反熔丝存储器元件的增强发射位点来操纵翅片拓扑并用于有效地促进较低击穿电压晶体管。在一个示例实施例中，提供了一种半导体反熔丝装置，其包括具有锥形部分的翅片的非平面扩散区域，在包括锥形部分的鳍片上的介电隔离层和介电隔离层上的栅极材料。翅片的锥形部分可以例如通过氧化，蚀刻和/或烧蚀形成，并且在一些情况下包括基底区域和变薄区域，并且变薄区域比基底区域薄至少50％。

58. 发明申请

WO2007005743A3 BIDIRECTIONAL HDCP TRANSMISSION MODULE USING SINGLE OPTICAL FIBER 审中-公开
公开(公告)号：WO2007005743A3
公开(公告)日：2007-01-11
申请号：PCT/US2006/025832
申请日：2006-06-30
申请人： OWLINK TECHNOLOGY, INC. , TONG, Xiaolin , TZENG, Shing-Wu, P. , ZHANG, Hua , BLAIR, Randall
发明人： TONG, Xiaolin , TZENG, Shing-Wu, P. , ZHANG, Hua , BLAIR, Randall
IPC分类号： H04B10/12
摘要： Techniques that provide cost effective optical fiber communication links for HDCP transmission systems and the like are provided. A single fiber for bidirectional communication is enabled, without wavelength selective unit to achieve the HDCP transmission. One embodiment of the present invention has a forward channel using a light source (e.g., VCSEL at about 850 nm) in the GHz modulation level (e.g., 1 GHz or greater), and a corresponding photodetector. The backward channel has a light source (e.g., LED at 630 nm) in the MHz modulation level (e.g., 10 MHz or less), and a corresponding photodetector. One application is for realizing a home entertainment system (e.g., DVD player and high definition television) that employs an HDCP-enabled communication link to transmit copy restricted digital content.

59. 发明申请

WO2005125137A2 MULTIUSER DETECTION WITH TARGETED ERROR CORRECTION CODING 审中-公开
标题翻译：多重检测与指定的错误修正编码
公开(公告)号：WO2005125137A2
公开(公告)日：2005-12-29
申请号：PCT/US2004/026254
申请日：2004-08-11
申请人： BAE SYSTEMS INFORMATION AND ELECTRONIC SYSTEMS INTEGRATION INC. , MILLS, Diane, G.
发明人： MILLS, Diane, G.
IPC分类号： H04L27/06
CPC分类号： H04B1/7103 , H03M13/2957 , H03M13/37 , H03M13/63 , H04B1/7105 , H04L1/0048 , H04L1/005 , H04L1/0071 , H04L25/03171
摘要： An error correction decoding (ECC) processing scheme is disclosed that reduces computational complexity normally associated with multiuser detection (e.g., TurboMUD) solutions, without causing degradation in quality of service or decreasing the total throughput. Error correction decoding algorithms are applied only to portions of the estimates that were affected by the immediately previous MUD update process. Even though the MUD and/or ECC updating is targeted so as to reduce complexity of each iteration, all of the estimates are maintained and remain candidates for future updates. As such, there is no negative impact real-time or future performance. This targeting approach can be used in conjunction with many variations of MUD, including full-complexity or reduced complexity, and may include MUD with confidence ordering or voting, and other techniques for facilitating e fficient and effective MUD processing.
摘要翻译：公开了一种降低与多用户检测（例如，TurboMUD）解决方案通常相关联的计算复杂度的纠错解码（ECC）处理方案，而不会降低服务质量或降低总吞吐量。误差校正解码算法仅适用于受即时MUD更新过程影响的估计部分。即使MUD和/或ECC更新是针对性的，以减少每次迭代的复杂性，所有的估计都被维护，并且仍然是未来更新的候选者。因此，实时或未来的表现没有负面影响。这种目标方法可以与MUD的许多变体一起使用，包括完全复杂性或降低的复杂性，并且可以包括具有置信排序或投票的MUD以及用于促进有效和有效的MUD处理的其它技术。

60. 发明申请

WO2005094466A3 GENERATING AND SERVING TILES IN A DIGITAL MAPPING SYSTEM 审中-公开
公开(公告)号：WO2005094466A3
公开(公告)日：2005-10-13
申请号：PCT/US2005/009538
申请日：2005-03-23
申请人： GOOGLE INC. , RASMUSSEN, Jens, Eilstrup , RASMUSSEN, Lars, Eilstrup , MA, Stephen
发明人： RASMUSSEN, Jens, Eilstrup , RASMUSSEN, Lars, Eilstrup , MA, Stephen
IPC分类号： G06G5/00
摘要： Digital tile-based mapping techniques are disclosed that enable efficient online serving of aesthetically pleasing maps. In one particular embodiment, an image tile-based digital mapping system is configured for generating map tiles during an offline session, and serving selected sets of those tiles to a client when requested. Also provided are solutions for handling map labels and other such features in a tile-based mapping system, such as when a map label crosses map file boundaries. Various processing environments (e.g., servers or other computing devices) can be employed in the system.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式