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41. 发明申请

WO01050243A3 FLOW CONTROL FOR I/O RECEPTION OVERLOAD 审中-公开
标题翻译：流量控制与I / O过载招待会
公开(公告)号：WO01050243A3
公开(公告)日：2002-04-18
申请号：PCT/EP2001/000019
申请日：2001-01-03
IPC分类号： G06F13/12
CPC分类号： G06F13/124
摘要： The invention relates to a system that consists of at least two components and that is usually dimensioned in such a manner that the capacity of the components is increasing towards the exterior of the system. If this dimensioning is not fulfilled for any of the components, a bottleneck occurs that may cause a reception overload on the very component that represents the bottleneck. The invention solves this problem by providing a specific kind of flow control.
摘要翻译：由至少两种组分的链的系统通常被定尺寸，使得部件的至Systemäusseren容量变大。这种尺寸不满意的组件上，有一个与Emfangsüberlast的该组件上的风险，这构成了收缩的瓶颈。本发明通过特定类型的流量控制的解决了这个问题。

42. 发明申请

WO00022536A1 AN INTEGRATED MULTIMEDIA SYSTEM 审中-公开
标题翻译：综合多媒体系统
公开(公告)号：WO00022536A1
公开(公告)日：2000-04-20
申请号：PCT/JP1999/005659
申请日：1999-10-14
IPC分类号： G06T1/20 , G06F13/10 , G06F13/12 , G06F13/28 , G06F13/36 , G06F15/78 , G06T15/00
CPC分类号： G06F13/102 , G06F13/124 , G06T15/005
摘要： An integrated multimedia system has a multimedia processor disposed in an integrated circuit. The system comprises a first host processor system which is coupled to the multimedia processor. A second local processor is disposed within the multimedia processor which controls the operation of the multimedia processor. A data transfer switch is disposed within the multimedia processor and coupled to the second processor which transfers data to various modules of the multimedia processor. A fixed function unit is disposed within the multimedia processor, coupled to the second processor and the data transfer switch and configured to perform three dimensional graphic operations. A data streamer is coupled to the data transfer switch, and configured to schedule simultaneous data transfers among a plurality of modules disposed within the multimedia processor in accordance with the corresponding channel allocations. An interface unit is coupled to the data streamer and has a plurality of input/output (I/O) device driver units. A multiplexer is coupled to the interface unit and provides access between a selected number of I/O device driver units and external I/O devices via output pins. A plurality of external I/O devices are coupled to the multimedia processor.
摘要翻译：集成多媒体系统具有设置在集成电路中的多媒体处理器。该系统包括耦合到多媒体处理器的第一主机处理器系统。第二本地处理器被布置在控制多媒体处理器的操作的多媒体处理器内。数据传输开关设置在多媒体处理器内并且耦合到第二处理器，该第二处理器将数据传送到多媒体处理器的各个模块。固定功能单元设置在多媒体处理器内，耦合到第二处理器和数据传输开关，并被配置为执行三维图形操作。数据流器耦合到数据传输交换机，并且被配置为根据相应的信道分配来调度在多媒体处理器内设置的多个模块之间的同时数据传输。接口单元耦合到数据流器并且具有多个输入/输出（I / O）设备驱动器单元。多路复用器耦合到接口单元，并通过输出引脚提供所选数量的I / O设备驱动单元和外部I / O设备之间的访问。多个外部I / O设备耦合到多媒体处理器。

43. 发明申请

WO99048235A1 SYSTEM AND METHOD FOR MULTIPLEXING SERIAL LINKS 审中-公开
标题翻译：用于多重串行链接的系统和方法
公开(公告)号：WO99048235A1
公开(公告)日：1999-09-23
申请号：PCT/US1999/005658
申请日：1999-03-15
IPC分类号： H04J3/00 , G06F3/06 , G06F13/12 , G06F13/40 , H04J3/04 , H04J3/22
CPC分类号： G06F3/0614 , G06F3/0656 , G06F3/0689 , G06F13/124 , G06F13/4022 , H04J3/047
摘要： A plurality of transmitters are multiplexed to a hub through clocked serial links (48). Timing problems that may arise when switching between links (48) are eliminated with a system including a group serial receiver (80) for each link (48) for performing serial to parallel conversion of data sent over the serial link (48), outputting a group clock signal (84) based on the serial clock signal, outputting parallel data (82) clocked by the group clock signal (84), and determining a data enable signal (86) from the serial link (48). A select signal (64) for determining the serial link (48) being read by the hub (60) selects the corresponding group clock (100), parallel data (92), and data enable (96). A load control (102) clocks the selected parallel data (92) into a first-in, first-out buffer (106) using the selected group clock (100) when the selected data enable (96) is asserted. When the selected data enable (96) is not asserted, the load control (102) is held in reset and, hence, is insensitive to irregularities in the selected clock signal (100) due to switching between links (48). Data is clocked from the buffer (106) by a local clock (114).
摘要翻译：多个发射机通过时钟串行链路复用到集线器（48）。当通过包括用于每个链路（48）的组串行接收器（80）的系统来消除在链路（48）之间切换时可能出现的定时问题，用于执行通过串行链路（48）发送的数据的串行到并行转换，输出基于串行时钟信号的组时钟信号（84），输出由组时钟信号（84）定时的并行数据（82），以及从串行链路（48）确定数据使能信号（86）。用于确定由集线器（60）读取的串行链路（48）的选择信号（64）选择对应的组时钟（100），并行数据（92）和数据使能（96）。当选择的数据使能（96）被断言时，负载控制（102）使用所选择的组时钟（100）将选择的并行数据（92）时钟化为先入先出缓冲器（106）。当所选择的数据使能（96）不被置位时，负载控制（102）被保持在复位状态，因此由于链路（48）之间的切换而对所选择的时钟信号（100）中的不规则不敏感。数据由缓冲器（106）由本地时钟（114）计时。

44. 发明申请

WO99016195A1 FULL-DUPLEX COMMUNICATION PROCESSOR 审中-公开
标题翻译：全双工通信处理器
公开(公告)号：WO99016195A1
公开(公告)日：1999-04-01
申请号：PCT/US1998/020003
申请日：1998-09-24
IPC分类号： G06F13/10 , G06F13/12 , H04L12/28 , H04L12/56 , H04L29/06 , H04L29/10 , H04J1/16 , H04B1/44 , H04L12/50 , H04Q11/00
CPC分类号： H04L49/901 , G06F13/124 , H04L12/2801 , H04L29/06 , H04L49/90 , H04L49/9089 , H04L69/12
摘要： A full duplex communication processor (20) simultaneously sends and receives frames of data and commands. Separate transmit (32) and receive (30) protocol engines are controlled by separate sequencers. This enables frames of data to be received and transmitted simultaneously without involving the CPU (40) on a frame-by-frame basis.
摘要翻译：全双工通信处理器（20）同时发送和接收数据帧和数据帧。独立的传输（32）和接收（30）协议引擎由独立的定序器控制。这使得数据帧能够同时接收和发送而不涉及CPU（40）在逐帧的基础上。

45. 发明申请

WO1997034235A1 MULTI-THREADED FIFO POOL BUFFER AND BUS TRANSFER CONTROL SYSTEM 审中-公开
标题翻译：多线程FIFO缓冲区和总线传输控制系统
公开(公告)号：WO1997034235A1
公开(公告)日：1997-09-18
申请号：PCT/US1997003667
申请日：1997-03-06
申请人： DIAMOND MULTIMEDIA SYSTEMS, INC.
发明人： DIAMOND MULTIMEDIA SYSTEMS, INC. , BEGUR, Sridhar , GIFFORD, James, K. , LEWIS, Adrian , SPENCER, Donald, J. , KILBOURN, Thomas, E. , GOCHNAUER, Donald, B.
IPC分类号： G06F13/00
CPC分类号： G06F9/3879 , G06F13/124
摘要： A bus transfer control system manages the transfer of multiple asynchronous data streams through a buffer pool. The bus transfer control system includes a buffer pool having a plurality of memory blocks, wherein each memory block provides for the storage of a plurality of data bytes and a plurality of data transfer devices coupled to the buffer pool to allow the transfer of segments of one or more data streams to be transferred between the plurality of data transfer devices through the buffer pool. A transfer controller maintains status information relating to the status of data in the memory blocks and includes control logic for repeatedly evaluating the status information and providing for the prioritied selection of a first data transfer device and a predetermined one of the memory blocks.
摘要翻译：总线传输控制系统通过缓冲池管理多个异步数据流的传输。总线传输控制系统包括具有多个存储器块的缓冲池，其中每个存储器块提供多个数据字节的存储和耦合到缓冲池的多个数据传送设备，以允许传送一个或更多数据流通过缓冲池在多个数据传送装置之间传送。传送控制器维护与存储器块中的数据状态有关的状态信息，并且包括控制逻辑，用于重复地评估状态信息并提供第一数据传送装置和预定的一个存储块的优先选择。

46. 发明申请

WO1989001202A1 COMMUNICATION PROCESSOR FOR PERSONAL COMPUTER 审中-公开
标题翻译：个人电脑通讯处理器
公开(公告)号：WO1989001202A1
公开(公告)日：1989-02-09
申请号：PCT/US1988002449
申请日：1988-07-20
申请人： FACE TECHNOLOGIES, INC.
发明人： FACE TECHNOLOGIES, INC. , FACE, William, W. , BARNICH, Richard, G.
IPC分类号： G06F09/02
CPC分类号： G06F13/409 , G06F13/124
摘要： A microcomputer is adapted to act as a communications processor (10) for a personal computer (12). The communications processor (10) includes at least two I/O ports, one for insertion into a slot connector of the personal computer (60), and the other so as to be accessible to external connectors (62). The communications processor (10) has a power supply (54) and a back-up battery power supply (58). The communication processor (10) can receive communications from and transmit to remote sources while the personal computer (12) is being used for other purposes. Receiver messages are stored in the RAM (48) of the commmunications processor (10) and are unloaded to the personal computer (12) under control of its keyboard (26) at the operator's convenience. Messages to be transmitted may also be loaded into the communication processor's RAM (48) from the personal computer (12) along with instructions causing them to be transmitted at any convenient time, whether or not the personal computer (12) is then energized or in alternate use.
摘要翻译：微型计算机适于用作个人计算机（12）的通信处理器（10）。通信处理器（10）包括至少两个I / O端口，一个用于插入个人计算机（60）的插槽连接器中，另一个用于外部连接器（62）可访问。通信处理器（10）具有电源（54）和备用电池电源（58）。当个人计算机（12）用于其他目的时，通信处理器（10）可以从远程源接收通信并传送到远程源。接收器消息存储在通信处理器（10）的RAM（48）中，并且在操作者方便的情况下在其键盘（26）的控制下将其卸载到个人计算机（12）。要发送的消息也可以从个人计算机（12）加载到通信处理器的RAM（48）中，同时指示使得它们在任何方便的时间被传送，无论个人计算机（12）是否被激活，或者在备用。

47. 发明申请

WO1986004169A1 PRINTER-TAPE DATA LINK PROCESSOR 审中-公开
标题翻译：打印机数据链接处理器
公开(公告)号：WO1986004169A1
公开(公告)日：1986-07-17
申请号：PCT/US1986000009
申请日：1986-01-06
申请人： BURROUGHS CORPORATION
发明人： BURROUGHS CORPORATION , BUGGERT, Jerrold, E.
IPC分类号： G06F13/12
CPC分类号： G06F13/124
摘要： A peripheral controller (data link processor) controls data transfers between a host computer and a plurality of tape peripheral units and a single printer peripheral unit. A master microprocessor commands three subordinate controllers to permit concurrent data transfers through a buffer memory in both the Read and the Write directions. A dual channel control from the master microprocessor actuates a DMA switch so that data transfers to/from the tape units can be controlled by switching on alternate control lines which regulate the data transfer operations.

48. 发明申请

WO1985005708A1 CONTROL INTEGRATED CIRCUIT 审中-公开
标题翻译：控制集成电路
公开(公告)号：WO1985005708A1
公开(公告)日：1985-12-19
申请号：PCT/JP1985000298
申请日：1985-05-29
申请人： HITACHI, LTD. , FUNABASHI, Tsuneo , IWASAKI, Kazuhiko , YAMAGUCHI, Noboru , SHIMURA, Takanori , TATEZAKI, Junichi
发明人： HITACHI, LTD.
IPC分类号： G06F13/12
CPC分类号： G06F13/385 , G06F13/124
摘要： A control integrated circuit of the invention is based upon a hierarchical processor structure. A microprogram controller (211) is employed for a high-order processor to give sophisticated functions. A plurality of finite-state transition machines (208, 209) are employed for a low-order processor to increase the speed of operation. The control function for an external input/output device is divided and is executed by a plurality of finite-state transition machines (208, 209), the performance thereof being controlled by the microprogram controller (211). According to the present invention, a new control function is processed by adding a finite-state transition machine (210). Namely, the invention provides the general structure of an integrated circuit for controlling various input/output devices.

49. 发明申请

WO1981001064A1 IMPROVEMENTS IN OR RELATING TO DATA COMMUNICATIONS 审中-公开
标题翻译：数据通信的改进或相关
公开(公告)号：WO1981001064A1
公开(公告)日：1981-04-16
申请号：PCT/GB1980000161
申请日：1980-10-09
申请人： BURROUGHS CORP , ROBERTSON M , WARREN R
发明人： BURROUGHS CORP
IPC分类号： G06F03/04
CPC分类号： G06F13/124 , G06F13/38
摘要： A data communications controller for use intermediately between a data processor and a data communications link such as a modem driven landline, relieves the data processor of time consuming supervisory and data preparation tasks normally associated with the use of a data link by means of a block loadable transmit queue (24), an automatic CRC generator (26), an automatic time-fill generator (28) and parity generator (32), a block unloadable receive queue (44), an automatic character load translator (42), an automatic character monitor (40) and a received serial bit queue (34) in conjunction with a byte synchronising detector (36), the operation or non-operation of each of the above elements and, if operational, the manner of that operation being selectable by the data processor.
摘要翻译：用于数据处理器和诸如调制解调器驱动的座机之类的数据通信链路之间的数据通信控制器通过借助于可装载的块来缓解数据处理器与数据链路的使用通常相关的耗时的监督和数据准备任务发送队列（24），自动CRC生成器（26），自动时间填充生成器（28）和奇偶校验生成器（32），块卸载接收队列（44），自动字符加载转换器（42）字符监视器（40）和接收到的串行位队列（34）结合字节同步检测器（36），每个上述元件的操作或不操作，并且如果可操作，该操作的方式可以由数据处理器。

50. 发明申请

WO2018218840A1 电子设备、通道切换的控制方法及控制电路审中-公开
公开(公告)号：WO2018218840A1
公开(公告)日：2018-12-06
申请号：PCT/CN2017/104834
申请日：2017-09-30
申请人：广州视源电子科技股份有限公司 , 广州视睿电子科技有限公司
发明人：陈俊伟
IPC分类号： G06F13/12 , G06F9/48
CPC分类号： G06F9/4881 , G06F13/124
摘要：一种电子设备（300）、通道切换的控制方法及控制电路（130），所述电子设备（300）包括接口模块（330）、切换模块（340）、第一操作系统（310）和第二操作系统（320），接口模块（330）包括至少两个外设接口（331、332、333）；切换模块（340）根据所述第一操作系统（310）的控制指令切换接口模块（330）与第一操作系统（310）或第二操作系统（320）之间的通道；检测到系统切换指令时，控制切换模块（340）连通接口模块（330）与第二操作系统（320）的通道，并确定是否控制切换模块（340）断开接口模块（330）与本操作系统的通道，通过判断外设与第一操作系统（310）或第二操作系统（320）的通信需求输出控制指令，从而能够根据外设的实际使用需求切换通信通道。

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