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41. 发明申请

WO2010002752A1 READ DISTURB MITIGATION IN NON-VOLATILE MEMORY 审中-公开
标题翻译：在非易失性存储器中读取干扰减轻
公开(公告)号：WO2010002752A1
公开(公告)日：2010-01-07
申请号：PCT/US2009/048990
申请日：2009-06-29
申请人： SANDISK CORPORATION , MOKHLESI, Nima , SCHUEGRAF, Klaus
发明人： MOKHLESI, Nima , SCHUEGRAF, Klaus
IPC分类号： G11C16/34
CPC分类号： G11C11/5642 , G11C16/3418 , G11C16/3427 , G11C29/00
摘要： Read disturb is reduced in non-volatile storage. In one aspect, when a read command is received from a host for reading a selected word line, a word line which is not selected for reading is randomly chosen and its storage elements are sensed to determine optimized read compare levels for reading the selected word line. Or, a refresh operation may be indicated for the entire block based on an error correction metric obtained in reading the storage elements of the chosen word line. This is useful especially when the selected word line is repeatedly selected for reading, exposing the other word lines to additional read disturb. In another aspect, when multiple data states are stored, one read compare level is obtained from sensing, e.g., from a threshold voltage distribution, and other read compare levels are derived from a formula.
摘要翻译：非易失性存储器中的读取干扰减少。在一个方面，当从主机接收到用于读取所选择的字线的读取命令时，随机选择未被选择用于读取的字线，并且感测其存储元件以确定用于读取所选字线的优化读取比较电平。或者，可以基于在读取所选字线的存储元件中获得的纠错度量，针对整个块指示刷新操作。特别是当所选字线被重复选择用于读取时，这是有用的，将其它字线暴露于额外的读取干扰。在另一方面，当存储多个数据状态时，通过例如来自阈值电压分布的感测获得一个读取比较电平，并且从公式导出其它读取的比较电平。

42. 发明申请

WO2008118432A1 THREE DIMENSIONAL NAND MEMORY AND METHOD OF MAKING THEREOF 审中-公开
标题翻译：三维NAND存储器及其制作方法
公开(公告)号：WO2008118432A1
公开(公告)日：2008-10-02
申请号：PCT/US2008/003906
申请日：2008-03-26
申请人： SANDISK 3D LLC , MOKHLESI, Nima , SCHEUERLEIN, Roy
发明人： MOKHLESI, Nima , SCHEUERLEIN, Roy
IPC分类号： H01L21/8246 , H01L21/8247 , H01L27/115 , H01L21/336 , H01L29/792 , H01L29/788
CPC分类号： H01L27/115 , G11C16/0483 , H01L27/11556 , H01L27/11568 , H01L29/66825 , H01L29/66833 , H01L29/7883 , H01L29/792
摘要： A monolithic, three dimensional NAND string includes a first memory cell located over a second memory cell. A semiconductor active region of the first memory cell is a first pillar having a square or rectangular cross section when viewed from above, the first pillar being a first conductivity type semiconductor region located between second conductivity type semiconductor regions. A semiconductor active region of the second memory cell is a second pillar having a square or rectangular cross section when viewed from above, the second pillar located under the first pillar, the second pillar being a first conductivity type semiconductor region located between second conductivity type semiconductor regions. One second conductivity type semiconductor region in the first pillar contacts one second conductivity type semiconductor region in the second pillar.
摘要翻译：单片三维NAND串包括位于第二存储器单元上的第一存储单元。第一存储单元的半导体有源区是从上方观察时具有正方形或矩形截面的第一柱，第一柱是位于第二导电型半导体区之间的第一导电型半导体区。第二存储单元的半导体有源区是当从上方观察时具有正方形或矩形横截面的第二柱，位于第一柱下方的第二柱，第二柱是位于第二导电型半导体区域。第一柱中的一个第二导电类型半导体区域接触第二柱中的一个第二导电类型半导体区域。

43. 发明申请

WO2008083161A1 PAGE BY PAGE ECC VARIATION IN A MEMORY DEVICE 审中-公开
标题翻译：在存储器件中逐页ECC变化
公开(公告)号：WO2008083161A1
公开(公告)日：2008-07-10
申请号：PCT/US2007/088830
申请日：2007-12-26
申请人： SANDISK CORPORATION , MOKHLESI, Nima
发明人： MOKHLESI, Nima
IPC分类号： G11C16/04 , G06F11/10
CPC分类号： G06F11/1068
摘要： A method of storing memory device data overhead information in data cells in a row of cells, the row being one of a plurality of rows comprising a unit of data, is disclosed. The method includes storing user data attribute information including error correction code (922) in an overhead portion of a data sector in the row adjacent to a portion of the data sector storing user data (902). Block level data attributes are stored in the overhead portion of the data sector in a location (924) occupied by ECC information in other rows, said row having greater user data integrity and fewer ECC bits than others of said rows.
摘要翻译：公开了一种将存储器件数据开销信息存储在单元行中的数据单元中的方法，该行是包括数据单元的多行之一。该方法包括将包含纠错码（922）的用户数据属性信息存储在与存储用户数据（902）的数据扇区的一部分相邻的行中的数据扇区的开销部分中。块级数据属性被存储在数据扇区的开销部分中，在由其他行中的ECC信息占据的位置（924）中，所述行具有更大的用户数据完整性，并且比其他所述行更少的ECC位。

44. 发明申请

WO2008048813A1 NON-VOLATILE MEMORY WITH DUAL VOLTAGE SELECT GATE STRUCTURE 审中-公开
标题翻译：具有双电压选择门结构的非易失性存储器
公开(公告)号：WO2008048813A1
公开(公告)日：2008-04-24
申请号：PCT/US2007/080746
申请日：2007-10-08
申请人： SANDISK CORPORATION , MOKHLESI, Nima , HIGASHITANI, Masaaki
发明人： MOKHLESI, Nima , HIGASHITANI, Masaaki
IPC分类号： H01L21/28 , H01L21/8247 , H01L27/115 , H01L29/423 , G11C16/04
CPC分类号： H01L21/28273 , G11C11/5628 , G11C16/0483 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A select gate structure (1260) for a non-volatile storage system includes a select gate (1022) and a coupling electrode (1023) which are independently drivable. The coupling electrode is adjacent to a word line in a NAND string and has a voltage (Vces) applied which reduces gate induced drain lowering (GIDL) program disturb of an adjacent unselected non-volatile storage element. In particular, an elevated voltage can be applied to the coupling electrode when the adjacent word line is used for programming. A reduced voltage is applied when a non-adjacent word line is used for programming. The voltage can also be set based on other programming criteria. The select gate is provided by a first conductive region (1230) while the coupling electrode is provided by a second conductive region formed over, and isolated from, the first conductive region.
摘要翻译：用于非易失性存储系统的选择栅极结构（1260）包括独立驱动的选择栅极（1022）和耦合电极（1023）。耦合电极与NAND串中的字线相邻，并且具有施加的电压（Vces），其减小相邻未选择的非易失性存储元件的栅极引起的漏极降低（GIDL）编程干扰。特别地，当相邻字线用于编程时，可以将高电压施加到耦合电极。当使用非相邻字线进行编程时，施加降低的电压。也可以根据其他编程标准设定电压。选择栅极由第一导电区域（1230）提供，而耦合电极由形成在第一导电区域上并与之隔离的第二导电区域提供。

45. 发明申请

WO2008036552A2 ARRAY OF NON-VOLATILE MEMORY CELLS WITH FLOATING GATES FORMED OF SPACERS IN SUBSTRATE TRENCHES 审中-公开
标题翻译：具有在底板中形成间隔物的浮动栅的非易失性记忆细胞阵列
公开(公告)号：WO2008036552A2
公开(公告)日：2008-03-27
申请号：PCT/US2007/078420
申请日：2007-09-13
申请人： SANDISK CORPORATION , MOKHLESI, Nima
发明人： MOKHLESI, Nima
IPC分类号： H01L21/28 , H01L21/8247 , H01L27/115 , H01L29/423
CPC分类号： H01L27/115 , H01L21/28273 , H01L27/11556 , H01L29/42336 , H01L29/7881
摘要： In order to reduce the integrated circuit area that is occupied by an array of a given number of flash memory cells, floating gate charge storage elements are positioned along sidewalls of substrate trenches, preferably being formed of doped polysilicon spacers. An array of dual floating gate memory cells includes cells with this structure, as an example. A NAND array of memory cells is another example of an application of this cell structure. The memory cell and array structures have wide application to various specific NOR and NAND memory cell array architectures.
摘要翻译：为了减少由给定数量的闪存单元的阵列占据的集成电路区域，浮置栅极电荷存储元件沿着衬底沟槽的侧壁定位，优选地由掺杂多晶硅间隔物形成。作为示例，双浮栅存储器单元的阵列包括具有该结构的单元。存储器单元的NAND阵列是该单元结构的应用的另一示例。存储单元和阵列结构广泛地应用于各种特定的NOR和NAND存储器单元阵列架构。

46. 发明申请

WO2008021736A2 NONVOLATILE MEMORIES WITH SHAPED FLOATING GATES 审中-公开
标题翻译：具有形状的浮动门的非易失性存储器
公开(公告)号：WO2008021736A2
公开(公告)日：2008-02-21
申请号：PCT/US2007/075041
申请日：2007-08-02
申请人： SANDISK CORPORATION , MOKHLESI, Nima
发明人： MOKHLESI, Nima
IPC分类号： H01L21/28 , H01L21/8247 , H01L27/115 , H01L29/423
CPC分类号： H01L21/28273 , H01L27/11521 , H01L29/42324
摘要： In a nonvolatile memory using floating gates to store charge, individual floating gates are L-shaped. Orientations of L-shaped floating gates may alternate in the bit line direction and may also alternate in the word line direction. L-shaped floating gates are formed by etching conductive portions using etch masks of different patterns to obtain floating gates of different orientations.
摘要翻译：在使用浮动门来存储电荷的非易失性存储器中，各个浮动门是L形的。 L形浮栅的方向可以在位线方向上交替，并且也可以在字线方向上交替。通过使用不同图案的蚀刻掩模蚀刻导电部分来形成L形浮栅，以获得不同取向的浮动栅极。

47. 发明申请

WO2007149677A2 METHOD FOR NON-REAL TIME REPROGRAMMING OF NON-VOLATILE MEMORY TO ACHIEVE TIGHTER DISTRIBUTION OF THRESHOLD VOLTAGES 审中-公开
标题翻译：非易失性存储器的非实时时间重建方法，用于实现阈值电压的分配
公开(公告)号：WO2007149677A2
公开(公告)日：2007-12-27
申请号：PCT/US2007/069711
申请日：2007-05-25
申请人： SANDISK CORPORATION , MOKHLESI, Nima
发明人： MOKHLESI, Nima
IPC分类号： G11C16/10 , G11C11/56
CPC分类号： G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/3418 , G11C16/3427 , G11C29/00 , G11C2211/5621
摘要： A set of non-volatile storage elements undergoes initial programming, after which a reprogramming, with higher verify levels, is performed in non-real time, such as when a control enters a standby mode, when no other read or write tasks are pending. The reprogramming can program pages in the set one at a time, stopping at a page boundary when another read or write task is pending, and restarting when the control become available again. Status flags can be provided to identify whether a page and/or the set has completed the reprogramming. In another aspect, a higher pass voltage is applied to unselected word lines during the reprogramming. In another aspect, an error count is determined using a default set of read voltages, and an alternative set of read voltages is selected if the count exceeds a threshold.
摘要翻译：一组非易失性存储元件经历初始编程，此后，具有较高验证级别的重新编程以非实时的方式执行，例如当控制进入待机模式时，当没有其他读取或写入任务未决时。重新编程可以一次编程一组中的页面，当另一个读取或写入任务正在等待时停止在页面边界，并在控件再次可用时重新启动。可以提供状态标志以识别页面和/或集合是否已经完成重新编程。在另一方面，在重新编程期间，对未选择的字线施加更高的通过电压。在另一方面，使用默认读取电压集来确定错误计数，并且如果计数超过阈值，则选择一组替代的读取电压。

48. 发明申请

WO2007076451A3 BODY EFFECT SENSING METHOD FOR NON-VOLATILE MEMORIES 审中-公开
公开(公告)号：WO2007076451A3
公开(公告)日：2007-07-05
申请号：PCT/US2006/062513
申请日：2006-12-21
申请人： SANDISK CORPORATION , MOKHLESI, Nima , LUTZE, Jeffrey W.
发明人： MOKHLESI, Nima , LUTZE, Jeffrey W.
IPC分类号： G11C11/56
摘要： The present invention presents a scheme for sensing memory cells. Selected memory cells are discharged through their channels to ground and then have a voltage level placed on the traditional source and another voltage level placed on the control gate, and allowing the cell bit line to charge up. The bit line of the memory cell will then charge up until the bit line voltage becomes sufficiently high to shut off any further cell conduction. The rise of the bit line voltage will occur at a rate and to a level dependent upon the data state of the cell, and the cell will then shut off when the bit line reaches a high enough level such that the body effect affected memory cell threshold is reached, at which point the current essentially shuts off. A particular embodiment performs multiple such sensing sub-operations, each with a different control gate voltage, but with multiple states being sensed in each operation by charging the previously discharged cells up through their source.

49. 发明申请

WO2007033019A1 CREATING A DIELECTRIC LAYER USING ALD TO DEPOSIT MULTIPLE COMPONENTS 审中-公开
标题翻译：使用ALD创建一个介质层以沉积多个组件
公开(公告)号：WO2007033019A1
公开(公告)日：2007-03-22
申请号：PCT/US2006/035058
申请日：2006-09-08
申请人： SANDISK CORPORATION , MOKHLESI, Nima
发明人： MOKHLESI, Nima
IPC分类号： C23C16/455 , C23C16/40 , H01L21/314 , H01L21/28
CPC分类号： H01L21/28273 , C23C16/40 , C23C16/45529 , H01L21/02178 , H01L21/02181 , H01L21/02194 , H01L21/0228 , H01L21/3141 , H01L21/3142 , H01L21/31616 , H01L21/31645 , H01L27/115 , H01L27/11521 , H01L29/42324
摘要： A dielectric layer is created for use with non-volatile memory and/or other devices. The dielectric layer is created using atomic layer deposition to deposit multiple components whose mole fractions change as a function of depth in the dielectric layer in order to create a rounded bottom of a conduction band profile for the dielectric layer.
摘要翻译：创建用于与非易失性存储器和/或其他设备一起使用的介电层。使用原子层沉积产生电介质层以沉积其摩尔分数随电介质层中深度的函数而变化的多个组分，以形成用于电介质层的导带轮廓的圆形底部。

50. 发明申请

WO2007033003A1 ATOMIC LAYER DEPOSITION WITH NITRIDATION AND OXIDATION 审中-公开
标题翻译：原子层沉积与氧化和氧化
公开(公告)号：WO2007033003A1
公开(公告)日：2007-03-22
申请号：PCT/US2006/035006
申请日：2006-09-08
申请人： SANDISK CORPORATION , MOKHLESI, Nima
发明人： MOKHLESI, Nima
IPC分类号： H01L21/314 , H01L21/316 , H01L21/318 , C23C16/455
CPC分类号： H01L51/102 , C23C16/308 , C23C16/45529 , G11C11/5621 , G11C16/0483 , H01L21/28194 , H01L21/28273 , H01L21/3141 , H01L21/3142 , H01L21/3143 , H01L21/31645 , H01L21/318 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11543 , H01L29/42324 , H01L29/517 , H01L29/7883
摘要： A dielectric layer is created for use with non-volatile memory and/or other devices. The dielectric layer is created using atomic layer deposition to deposit multiple components whose mole fractions change as a function of depth in the dielectric layer in order to create a rounded bottom of a conduction band profile for the dielectric layer. In one embodiment, after deposition of the precursors and a purge step, the atomic layer deposition cycle includes a nitridation step that is followed by or overlapped by an oxidation step.
摘要翻译：创建用于与非易失性存储器和/或其他设备一起使用的介电层。使用原子层沉积产生电介质层以沉积其摩尔分数随电介质层中深度的函数而变化的多个组分，以形成用于电介质层的导带轮廓的圆形底部。在一个实施方案中，在沉积前体和吹扫步骤之后，原子层沉积循环包括随后氧化步骤或与氧化步骤重叠的氮化步骤。

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