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31. 发明申请

WO2006056951A1 INTEGRATED CIRCUIT SELF-TEST ARCHITECTURE 审中-公开
标题翻译：集成电路自检结构
公开(公告)号：WO2006056951A1
公开(公告)日：2006-06-01
申请号：PCT/IB2005/053883
申请日：2005-11-23
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , PELGROM, Marcel , VEENDRICK, Hendricus, J., M.
发明人： PELGROM, Marcel , VEENDRICK, Hendricus, J., M.
IPC分类号： G01R31/3185 , G01R31/3167
CPC分类号： G01R31/318536 , G01R31/3167
摘要： An integrated circuit (1) comprises a monitor (Ml, M3, M3) operable to produce monitor data in dependence upon a measured parameter of the integrated circuit (1); and a self test controller (28) connected to receive monitor data from the monitor (Ml, M2, M3). The self-test controller is also operable to output self test data from the integrated circuit. The monitor includes an output shift register (SRl, SR2, SR3) and is operable to output monitor data through the shift register (SRl, SR2, SR3). Such a system enables simplified communication of system self test results on an integrated circuit.
摘要翻译：集成电路（1）包括可操作以根据集成电路（1）的测量参数产生监视数据的监视器（M1，M3，M3）; 以及连接以从监视器（M1，M2，M3）接收监视数据的自检控制器（28）。自检控制器还可以从集成电路输出自检数据。监视器包括输出移位寄存器（SR1，SR2，SR3），并且可操作以通过移位寄存器（SR1，SR2，SR3）输出监视数据。这样的系统能够简化集成电路系统自检结果的通信。

32. 发明申请

WO2004077083A1 VORRICHTUNG SOWIE VERFAHREN ZUR TOLERANZANALYSE VON DIGITALEN UND/ODER DIGITALISIERTEN MESSWERTEN 审中-公开
标题翻译：装置和方法用于数字和/或数字化测的容差分析
公开(公告)号：WO2004077083A1
公开(公告)日：2004-09-10
申请号：PCT/DE2004/000175
申请日：2004-02-04
申请人： INFINEON TECHNOLOGIES AG , OBERLE, Hans-Dieter , SATTLER, Sebastian
发明人： OBERLE, Hans-Dieter , SATTLER, Sebastian
IPC分类号： G01R31/3167
CPC分类号： G01R31/31707 , G01R31/31703 , G01R31/3187 , G06F7/026
摘要： Eine elektrische Toleranzanalyseschaltung von digitalen und digitalisierten Messwerten weist Eingänge zum Empfang eines Messwerts (χ p ),eines Referenzwerts (χ i ) und eines Toleranzwerts (Δχ q ) sowie einen Ausgang zum Aussenden eines Ausgangswerts (χ a ) auf. Die elektrische Toleranzanalyseschaltung verfügt weiterhin über eine Überprüfungseinrichtung (42, 43) zum Überprüfen des Messwerts (χ p ) anhand wenigstens eines vorgebbaren Toleranzkriteriums und über eine Ausgabeeinrichtung zur Ausgabe eines Ausgangswerts (χ a ), der sich aus dem Zustand der Überprüfungseinrichtung (42, 43) ergibt, und zwar in Abhängigkeit davon, ob der Messwert (χ p ) das jeweils vorgegebene Toleranzkriterium erfüllt oder nicht.
摘要翻译：数字和数字化测量值的电路容差分析具有用于接收测量值（芯片），参考值（商务局）和公差值（Deltachiq）和用于发射上的输出值（奇异）的输出的输入。电容差分析电路还具有一个检测装置（42，43），用于至少一个预先确定的容差指标的基础上测得的值（芯片）的检查和输出装置，用于输出从所述测试设备（42，43）的产率的状态延伸的输出值（甲）根据所测得的值（芯片）是否满足所述相应的预定容差指标或没有。

33. 发明申请

WO01092899A1 SAMPLING DIGITIZER, METHOD FOR SAMPLING DIGITIZING, AND SEMICONDUCTOR INTEGRATED CIRCUIT TEST DEVICE WITH SAMPLING DIGITIZER 审中-公开
标题翻译：采样数字化仪，采样数字化方法和采样数字化仪的半导体集成电路测试装置
公开(公告)号：WO01092899A1
公开(公告)日：2001-12-06
申请号：PCT/JP2001/004480
申请日：2001-05-29
IPC分类号： G01R13/34 , G01R31/3167
CPC分类号： G01R13/345
摘要： A sampling digitizer, comprising a sampling head (11), a clock generating part (12), a digitizer (13), and a trigger circuit (14), wherein clock signals from the clock generating part (12) are supplied also to a delay element (15) to switch a changeover switch (16), using trigger signals from the trigger circuit, from an output from the delay element (15) to a clock signal not passing through the delay element (15) so as to supply the clock signals to the sampling head (11).
摘要翻译：一种采样数字转换器，包括采样头（11），时钟产生部分（12），数字转换器（13）和触发电路（14），其中来自时钟发生部分（12）的时钟信号也被提供给延迟元件（15），使用来自触发电路的触发信号，从延迟元件（15）的输出到不通过延迟元件（15）的时钟信号切换转换开关（16），以便提供时钟信号到采样头（11）。

34. 发明申请

WO0179863A2 METHOD AND APPARATUS FOR TESTING SIGNAL PATHS BETWEEN AN INTEGRATED CIRCUIT WAFER AND A WAFER TESTER 审中-公开
标题翻译：用于测试集成电路波形与波形测试仪之间的信号波形的方法和装置
公开(公告)号：WO0179863A2
公开(公告)日：2001-10-25
申请号：PCT/US0110030
申请日：2001-03-27
申请人： FORMFACTOR INC
发明人： WHITTEN RALPH G , ELDRIDGE BENJAMIN N
IPC分类号： G01R27/02 , G01R31/28 , G01R31/3167 , H01L21/66 , G01R
CPC分类号： G01R31/3167
摘要： Signal paths within an interconnect structure linking input/output (I/O) ports of an integrated circuit (IC) tester and test points of an IC die on a wafer are tested for continuity, shorts and resistance by using the interconnect structure to access a similar arrangement of test points on a reference wafer. Conductors in the reference wafer interconnect groups of test points. The tester may then test the continuity of signal paths through the interconnect structure by sending test signals between pairs of its ports through those signal paths and the interconnecting conductors within the reference wafer. A parametric test unit within the tester can also determine impedances of the signal paths through the interconnect structure by comparing magnitudes of voltage drops across pairs of its I/O ports to magnitudes of currents it transmits between the I/O port pairs.
摘要翻译：通过使用互连结构来访问集成电路（IC）测试器的输入/输出（I / O）端口和晶片上的IC芯片的测试点的互连结构中的信号路径被测试为连续性，短路和电阻在参考晶片上测试点的类似排列。测试点参考晶圆互连组中的导体。然后，测试者可以通过在参考晶片内的这些信号路径和互连导体之间通过在其端口对之间发送测试信号来测试通过互连结构的信号路径的连续性。测试仪中的参数测试单元还可以通过将I / O端口对之间的电压降幅度与I / O端口对之间传输的电流大小进行比较，来确定通过互连结构的信号路径的阻抗。

35. 发明申请

WO00028707A1 POINT-TO-POINT LINK IMPLEMENTED OVER A BROADCAST NETWORK 审中-公开
标题翻译：通过广播网络实现的点对点链路
公开(公告)号：WO00028707A1
公开(公告)日：2000-05-18
申请号：PCT/US1999/016202
申请日：1999-07-16
IPC分类号： G01R31/3183 , G01R31/30 , G01R31/316 , G01R31/3167 , H04L12/66 , H04L12/24 , H04L12/28 , H04M3/30
CPC分类号： G01R31/30 , G01R31/3167
摘要： A telecommunication test network including both a broadcast network and a point-to-point network is disclosed. The test network includes a programmable test system controller coupled to the broadcast network, a plurality of remote measurement units coupled to the point-to-point network, and a gateway computer linking the broadcast and point-to-point networks. The test system controller is programmed to establish communication channels with the remote measurement units, thereby enabling the test system controller to control the remote units and to analyze parameters measured by the remote units. These communication channels are established using standard protocols and without requiring custom programming in the gateway computer.
摘要翻译：公开了包括广播网络和点对点网络的电信测试网络。测试网络包括耦合到广播网络的可编程测试系统控制器，耦合到点对点网络的多个远程测量单元以及链接广播和点对点网络的网关计算机。测试系统控制器被编程为与远程测量单元建立通信通道，从而使测试系统控制器能够控制远程单元并分析由远程单元测量的参数。这些通信信道是使用标准协议建立的，而不需要网关计算机中的定制编程。

36. 发明申请

WO99053330A1 HIGH SPEED, REAL-TIME, STATE INTERCONNECT FOR AUTOMATIC TEST EQUIPMENT 审中-公开
标题翻译：用于自动测试设备的高速，实时，状态互连
公开(公告)号：WO99053330A1
公开(公告)日：1999-10-21
申请号：PCT/US1999/008130
申请日：1999-04-13
IPC分类号： G01R31/28 , G01R31/3167 , G01R31/319
CPC分类号： G01R31/31921 , G01R31/3167 , G01R31/31907 , G01R31/3191
摘要： A tester is disclosed in which state coherency is maintained between functional blocks of the tester by way of a novel state distribution and recombination network. The network includes a plurality of nodes configured to provide point-to-point links can be adjusted by selecting a suitable node configuration and by programming delay circuitry included in each node. The network therefore maintains state coherence between the functional blocks by ensuring that delays throughout the test system are both deterministic and adjustable. The tester is particularly useful for testing complex, mixed-signal semiconductor devices.
摘要翻译：公开了一种测试器，其中通过新的状态分布和重组网络在测试仪的功能块之间维持状态一致性。网络包括配置成提供点对点链路的多个节点可以通过选择合适的节点配置并通过编程包括在每个节点中的延迟电路进行调整。因此，网络通过确保整个测试系统的延迟都是确定性的和可调节的来维持功能块之间的状态一致性。该测试仪特别适用于测试复杂的混合信号半导体器件。

37. 发明申请

WO9825153A3 MEASUREMENT INSTRUMENT AMPLITUDE CALIBRATION 审中-公开
标题翻译：测量仪器振幅校准
公开(公告)号：WO9825153A3
公开(公告)日：1998-08-27
申请号：PCT/US9722408
申请日：1997-12-03
申请人： TERADYNE INC
发明人： BECKER JAMES H , COOP KENNETH F
IPC分类号： G01R31/3167 , G01R31/319 , G01R31/3193 , G01R35/00
CPC分类号： G01R35/005 , G01R31/3167 , G01R31/3191 , G01R31/3193
摘要： An electronic circuit tester, having an amplitude calibration feature, for accurately measuring signals produced by an electronic device under test, including a plurality of channels, data acquisition circuitry, and internal calibration source, and a digital filter. The internal calibration source is calibrated to a known standard. The tester then uses the internal calibration source to measure a signal amplitude error introduced by the channels and data acquisition circuitry. Next, the digital filter is automatically adjusted to correct the signal amplitude error, thereby presenting corrected data samples to a test computer for subsequent analysis.

38. 发明申请

WO2022226036A2 AUDIO SIGNAL PROCESSING AND SUPER-RESOLUTION ANALYSIS 审中-公开
公开(公告)号：WO2022226036A2
公开(公告)日：2022-10-27
申请号：PCT/US2022/025498
申请日：2022-04-20
申请人： GRAPHAUDIO, INC.
发明人： OSMANOVIC, Nermin , WILSON, Lorance , FOWLER, Burt
IPC分类号： G01R31/3167 , G01R19/00
摘要： The present application relates systems, devices, and methods for providing objective quality classifications and/or assessments of analog electrical audio signals. Such classifications and assessments are helpful for objectively evaluating the performance of certain audio hardware, for example, audio converters, amplifiers, etc. Embodiments of the present application provide exemplary devices, hardware, and methods.

39. 发明申请

WO2019241600A3 INTEGRATED COMMUNICATION LINK TESTING 审中-公开
公开(公告)号：WO2019241600A3
公开(公告)日：2019-12-19
申请号：PCT/US2019/037114
申请日：2019-06-13
申请人： TEKTRONIX, INC.
发明人： HOJABRI, Pirooz , O'BRIEN, Joshua , MARTIN, Gregory, A. , SATARZADEH, Patrick , HOVAKIMYAN, Karen
IPC分类号： G01R31/3167 , G01R31/317
摘要： A test and measurement device includes an input configured to receive an analog signal from a Device Under Test (DUT), an Analog to Digital Converter (ADC) coupled to the input and structured to convert the analog signal to a digital signal, a receiver implemented in a first Field Programmable Gate Array (FPGA) and structured to accept the digital signal and perform signal analysis on the digital signal, a transmitter implemented in a second FPGA and structured to generate a digital output signal, and a Digital to Analog Converter (DAC) coupled to the transmitter and structured to convert the digital output signal from the transmitter to an analog signal, and structured to send the analog signal to the DUT. The receiver and the transmitter are coupled together by a high speed data link over which data about the current testing environment may be shared.

40. 发明申请

WO2018044519A1 APPARATUS AND METHOD FOR IN SITU ANALOG SIGNAL DIAGNOSTIC AND DEBUGGING WITH CALIBRATED ANALOG-TO-DIGITAL CONVERTER 审中-公开
标题翻译：用于原位模拟信号诊断和调试以及校准的模拟数字转换器的设备和方法
公开(公告)号：WO2018044519A1
公开(公告)日：2018-03-08
申请号：PCT/US2017/046111
申请日：2017-08-09
申请人： QUALCOMM INCORPORATED
发明人： SONG, Deqiang , KONG, Xiaohua , PANDITA, Bupesh , GAO, Zhuo
IPC分类号： G01R31/316 , H03M1/10 , H03M1/12 , G01R31/3167
CPC分类号： H03M1/06 , G01R31/2884 , G01R31/3167 , H03M1/1009 , H03M1/12
摘要： An integrated circuit (IC) chip includes an on-chip analog signal monitoring circuit for monitoring a set of analog signals generated by one or more mixed signal cores within the IC chip, converting the analog signals into digital signals, storing the digital signals in an on-chip memory, and providing the digital signals to a test equipment upon request. The analog signal monitoring signal includes an on-chip reference generator for generating precise voltages and/or currents, a switching network for routing a selected reference signal to an analog-to-digital converter (ADC) for calibration purpose and for routing a selected analog signal from one of the mixed signal cores to the ADC for digitizing purposes. The IC chip further includes an on-chip memory for storing the digitized analog signals for subsequent accessing by a test equipment for analysis. The IC chip includes a digital analog test point (ATP) for outputting the digitized analog signals.
摘要翻译：集成电路（IC）芯片包括片上模拟信号监视电路，用于监视由IC芯片内的一个或多个混合信号内核产生的一组模拟信号，将模拟信号转换为数字信号信号，将数字信号存储在片上存储器中，并根据请求将数字信号提供给测试设备。模拟信号监视信号包括用于产生精确电压和/或电流的片上参考发生器，用于将选定参考信号路由到模数转换器（ADC）以用于校准目的并用于路由选定模拟信号的开关网络信号从一个混合信号内核传送到ADC以进行数字化。 IC芯片还包括片上存储器，用于存储数字化模拟信号，以供测试设备随后访问以供分析。 IC芯片包括一个用于输出数字化模拟信号的数字模拟测试点（ATP）。

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