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31. 发明申请

WO2008016849A3 METHOD AND APPARATUS FOR PREFETCHING NON-SEQUENTIAL INSTRUCTION ADDRESSES 审中-公开
标题翻译：用于预置非顺序指令地址的方法和装置
公开(公告)号：WO2008016849A3
公开(公告)日：2008-04-10
申请号：PCT/US2007074598
申请日：2007-07-27
申请人： QUALCOMM INC , STEMPEL BRIAN MICHAEL , SARTORIUS THOMAS ANDREW , SMITH RODNEY WAYNE
发明人： STEMPEL BRIAN MICHAEL , SARTORIUS THOMAS ANDREW , SMITH RODNEY WAYNE
IPC分类号： G06F9/38
CPC分类号： G06F9/3804 , G06F9/3806
摘要： A processor performs a prefetch operation on non-sequential instruction addresses. If a first instruction address misses in an instruction cache and accesses a higher-order memory as part of a fetch operation, and a branch instruction associated with the first instruction address or an address following the first instruction address is detected and predicted taken, a prefetch operation is performed using a predicted branch target address, during the higher-order memory access. If the predicted branch target address hits in the instruction cache during the prefetch operation, associated instructions are not retrieved, to conserve power. If the predicted branch target address misses in the instruction cache during the prefetch operation, a higher-order memory access may be launched, using the predicted branch instruction address. In either case, the first instruction address is re-loaded into the fetch stage pipeline to await the return of instructions from its higher-order memory access.
摘要翻译：处理器对非顺序指令地址执行预取操作。如果第一指令地址在指令高速缓存中未命中并作为提取操作的一部分访问较高阶存储器，并且与第一指令地址或第一指令地址之后的地址相关联的分支指令被检测并被预测得到，则预取在高阶存储器访问期间使用预测的分支目标地址来执行操作。如果在预取操作期间预测的分支目标地址在指令高速缓存中命中，则不检索相关联的指令以节省电力。如果在预取操作期间预测的分支目标地址在指令高速缓存中未命中，则可以使用预测的分支指令地址来启动更高阶的存储器访问。在任何一种情况下，第一个指令地址都会被重新载入到提取阶段的流水线中，以等待指令从其高阶内存访问中返回。

32. 发明申请

WO2007124307A3 VIRTUALLY-TAGGED INSTRUCTION CACHE WITH PHYSICALLY-TAGGED BEHAVIOR 审中-公开
标题翻译：带有物理标签行为的VIRTUALLY-TAGGED指令高速缓存
公开(公告)号：WO2007124307A3
公开(公告)日：2007-12-27
申请号：PCT/US2007066802
申请日：2007-04-17
申请人： QUALCOMM INC , SARTORIUS THOMAS ANDREW , SMITH RODNEY WAYNE , STREETT DAREN EUGENE
发明人： SARTORIUS THOMAS ANDREW , SMITH RODNEY WAYNE , STREETT DAREN EUGENE
IPC分类号： G06F12/08 , G06F12/10
CPC分类号： G06F12/1063 , G06F12/0891 , G06F2212/1056 , G06F2212/683
摘要： An instruction cache system having a virtually tagged instruction cache which, from a software program perspective, operates as if it were a physically tagged instruction cache is disclosed. The instruction cache system also includes a means for address translation which is responsive to an address translation invalidate instruction and a control logic circuit. The control logic circuit is configured to invalidate an entry in the virtually tagged instruction cache in response to the address translation invalidate instruction.
摘要翻译：一种具有虚拟标记的指令高速缓存的指令高速缓存系统，其从软件程序的角度来看，如同它是物理标记的指令高速缓存一样被操作。指令高速缓存系统还包括响应于地址转换无效指令和控制逻辑电路的地址转换装置。控制逻辑电路被配置为响应于地址转换无效指令使虚拟标记的指令高速缓存中的条目无效。

33. 发明申请

WO2007085011A3 EFFICIENT MEMORY HIERARCHY MANAGEMENT 审中-公开
标题翻译：有效的记忆层次管理
公开(公告)号：WO2007085011A3
公开(公告)日：2007-10-04
申请号：PCT/US2007060815
申请日：2007-01-22
申请人： QUALCOMM INC , MORROW MICHAEL WILLIAM , SARTORIUS THOMAS ANDREW
发明人： MORROW MICHAEL WILLIAM , SARTORIUS THOMAS ANDREW
IPC分类号： G06F9/38 , G06F12/08
CPC分类号： G06F9/3802 , G06F12/0848
摘要： In a processor, there are situations where instructions and some parts of a program may reside in a data cache prior to execution of the program. Hardware and software techniques are provided for fetching an instruction in the data cache after having a miss in an instruction cache to improve the processor's performance. If an instruction is not present in the instruction cache, an instruction fetch address is sent as a data fetch address to the data cache. If there is valid data present in the data cache at the supplied instruction fetch address, the data actually is an instruction and the data cache entry is fetched and supplied as an instruction to the processor complex. An additional bit may be included in an instruction page table to indicate on a miss in the instruction cache that the data cache should be checked for the instruction.
摘要翻译：在处理器中，在执行程序之前，存在指令和程序的某些部分驻留在数据高速缓存中的情况。提供了硬件和软件技术，用于在指令高速缓存中缺少提取处理器性能之后，在数据高速缓存中取指令。如果指令高速缓存中不存在指令，则将指令提取地址作为数据提取地址发送到数据高速缓存。如果在提供的指令获取地址处存在数据高速缓存中的有效数据，则数据实际上是指令，并且将数据高速缓存条目作为指令提取并提供给处理器复合体。在指令页表中可以包括额外的位，以指示在指令高速缓存中不应该对该指令检查数据高速缓存。

34. 发明申请

WO2006094196A3 METHOD AND APPARATUS FOR POWER REDUCTION IN AN HETEROGENEOUSLY- MULTI-PIPELINED PROCESSOR 审中-公开
标题翻译：多异构管道加工器中减少功率的方法和装置
公开(公告)号：WO2006094196A3
公开(公告)日：2007-02-01
申请号：PCT/US2006007607
申请日：2006-03-03
申请人： QUALCOMM INC , COLLOPY THOMAS K , SARTORIUS THOMAS ANDREW
发明人： COLLOPY THOMAS K , SARTORIUS THOMAS ANDREW
IPC分类号： G06F9/38
CPC分类号： G06F9/3867 , G06F9/3836 , G06F9/3851 , G06F9/3857 , G06F9/3875 , G06F9/3885
摘要： A processor includes a common instruction decode front end, e.g. fetch and decode stages, and a heterogeneous set of processing pipelines. A lower performance pipeline has fewer stages and may utilize lower speed/power circuitry. A higher performance pipeline has more stages and utilizes faster circuitry. The pipelines share other processor resources, such as an instruction cache, a register file stack, a data cache, a memory interface, and other architected registers within the system. In disclosed examples, the processor is controlled such that processes requiring higher performance run in the higher performance pipeline, whereas those requiring lower performance utilize the lower performance pipeline, in at least some instances while the higher performance pipeline is effectively inactive or even shut-off to minimize power consumption. The configuration of the processor at any given time, that is to say the pipeline(s) currently operating, may be controlled via several different techniques.
摘要翻译：处理器包括公共指令解码前端，例如，提取和解码阶段，以及一组异构的处理流水线。较低性能的管道具有较少的级数，并且可以利用较低速度/功率电路。更高性能的管道具有更多的阶段并且利用更快的电路。管道共享其他处理器资源，例如指令高速缓存，寄存器堆栈，数据高速缓存，存储器接口和系统内的其他架构寄存器。在所公开的示例中，处理器被控制，使得需要更高性能的处理在较高性能流水线中运行，而在较低性能流水线的那些需求较低的性能流水线中，至少在某些情况下使用较低性能流水线，而较高性能流水线有效地不活动或甚至切断以最小化功耗。处理器在任何给定时间的配置，也就是当前操作的流水线，可以通过几种不同的技术进行控制。

35. 发明申请

WO2014150727A3 METHOD, APPARATUSES AND PROGRAM PRODUCT TO SAVE AND STORE SYSTEM MEMORY MANAGEMENT UNIT CONTEXTS 审中-公开
标题翻译：方法，设备和程序产品来保存和存储系统内存管理单元
公开(公告)号：WO2014150727A3
公开(公告)日：2014-12-11
申请号：PCT/US2014024083
申请日：2014-03-12
申请人： QUALCOMM INC
发明人： ZENG THOMAS M , TOUZNI AZZEDINE , SARTORIUS THOMAS ANDREW
IPC分类号： G06F12/10 , G06F12/12 , G06T1/60
CPC分类号： G06F3/0631 , G06F3/0604 , G06F3/0673 , G06F12/10 , G06F12/12 , G06T1/60
摘要： A wireless mobile device includes a graphic processing unit (GPU) that has a system memory management unit (MMU) for saving and restoring system MMU translation contexts. The system MMU is coupled to a memory and the GPU. The system MMU includes a set of hardware resources. The hardware resources may be context banks, with each of the context banks having a set of hardware registers. The system MMU also includes a hardware controller that is configured to restore a hardware resource associated with an access stream of content issued by an execution thread of the GPU. The associated hardware resource may be restored from the memory into a physical hardware resource when the hardware resource associated with the access stream of content is not stored within one of the hardware resources.
摘要翻译：无线移动设备包括具有用于保存和恢复系统MMU转换上下文的系统存储器管理单元（MMU）的图形处理单元（GPU）。系统MMU耦合到存储器和GPU。系统MMU包括一组硬件资源。硬件资源可以是上下文库，其中每个上下文库具有一组硬件寄存器。系统MMU还包括硬件控制器，其被配置为恢复与由GPU的执行线程发布的内容的访问流相关联的硬件资源。当与内容的访问流相关联的硬件资源不被存储在硬件资源之一内时，相关联的硬件资源可以从存储器恢复为物理硬件资源。

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