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21. 发明申请

WO2017195025A3 AN INTEGRATED CIRCUIT WITH COMPENSATION FOR ERRORS INDUCED BY SELF-HEATING IN COMPONENTS 审中-公开
标题翻译：补偿组件中的自加热引起的错误的集成电路
公开(公告)号：WO2017195025A3
公开(公告)日：2017-11-16
申请号：PCT/IB2017/000596
申请日：2017-05-09
申请人： ANALOG DEVICES GLOBAL
发明人： DEMPSEY, Dennis A. , COLN, Michael C.W.
IPC分类号： H03M1/06 , H03M1/74
摘要： Many electronic circuits rely on the ratio of one component to other components being well defined. Current flow in component can warm the component causing its electrical properties to change, for example the resistance of a resistor may increase due to self heating as a result of current flow. The present disclosure provides a way to reduce temperature variation between components so as to reduce electrical mismatch between them or the consequences of such mismatch. This is important as even a change of resistance of, for example, 20 - 50 ppm in a resistor can result in non-linearity exceeding the least significant bit value of a 16 bit digital to analog converter.
摘要翻译：许多电子电路依赖于一个组件与其他组件的比率被明确定义。组件中的电流可以加热组件，导致其电特性改变，例如电阻器的电阻可能由于电流的流动而由于自身发热而增加。本公开提供了一种减少组件之间的温度变化的方式，以减少它们之间的电失配或这种失配的后果。这一点很重要，因为即使电阻的阻值变化（例如20 - 50 ppm）也会导致非线性超过16位数模转换器的最低有效位值。

22. 发明申请

WO2017058639A1 INTERPOLATION IN NON-UNIFORM SAMPLING ANALOG-TO-DIGITAL CONVERTERS 审中-公开
标题翻译：非均匀采样模拟数字转换器中的插值
公开(公告)号：WO2017058639A1
公开(公告)日：2017-04-06
申请号：PCT/US2016/053197
申请日：2016-09-22
申请人： GOOGLE INC.
发明人： RICH, Mark , MACK, Michael, Peter , KACZYNSKI, Brian
IPC分类号： H03M1/12 , H03M1/06
CPC分类号： H03M1/0639 , H03M1/1265
摘要： A radio frequency receiver includes an antenna that receives an analog signal comprising modulated encoded information. An analog signal generator generates a supplemental analog signal characterized by an amplitude sufficient to trigger a voltage threshold in a non-uniform sampling analog-to-digital converter. A mixer mixes the received signal and the supplemental signal. A non-uniform sampling analog-to-digital converter receives the mixed signal and produces a series of non-uniformly sampled {amplitude, time} tuples representing the mixed signal. The converter removes the supplemental signal from the series of {amplitude, time} tuples to produce a series of non-uniformly sampled {amplitude, time} tuples representative of the mixed signal without the supplemental signal. The converter interpolates the series of non-uniformly sampled {amplitude, time} tuples to form a series of samples periodic in time representative of the analog input signal. A digital signal processor (DSP) demodulates the interpolated series and decode the digital information from the demodulated series.
摘要翻译：射频接收机包括接收包括调制编码信息的模拟信号的天线。模拟信号发生器产生补充模拟信号，其特征在于足以在非均匀采样模数转换器中触发电压阈值的幅度。混频器将接收的信号和补充信号混合。非均匀采样模数转换器接收混合信号并产生表示混合信号的一系列不均匀采样的{振幅，时间}元组。该转换器从一系列{振幅，时间}元组中去除补充信号，以产生代表混合信号的一系列不均匀采样的{幅度，时间}元组，而没有补充信号。转换器内插一系列不均匀采样的{振幅，时间}元组，以形成代表模拟输入信号的时间周期的一系列采样。数字信号处理器（DSP）对内插序列进行解调，并从解调的系列解码数字信息。

23. 发明申请

WO2017053019A1 CLOSED LOOP LINEARIZED VCO-BASED ADC 审中-公开
标题翻译：闭环线性化基于VCO的ADC
公开(公告)号：WO2017053019A1
公开(公告)日：2017-03-30
申请号：PCT/US2016/049244
申请日：2016-08-29
申请人： QUALCOMM INCORPORATED
发明人： ROHAM, Masoud , ZARGHAM, Mohammad Meysam , LU, Li
IPC分类号： H03M1/06 , G01K7/16 , H03K3/0231 , H03L7/099 , H03M1/08 , H03M1/60
CPC分类号： H03M1/60 , G01K7/16 , H03K21/38 , H03M1/0612 , H03M1/0678 , H03M1/089
摘要： A device and method for analog to digital conversion is disclosed. The device can have a first amplifier operable to receive an input voltage and output a first control signal. The device can also have a first voltage-controlled oscillator (VCO) operably coupled to the first amplifier and configured to output a first signal based on the first control signal, the first signal having a sensor frequency. The device can also have a first switched-capacitor resistor operably coupled to the first VCO and to the first amplifier, the first switched-capacitor resistor configured to receive and be controlled by the sensor frequency. The device can also have a sensor counter operably coupled to the first VCO and configured produce a sensor count based on the sensor frequency. The device can also have a register configured provide a digital output proportional to the input voltage based on the sensor count.
摘要翻译：公开了一种用于模数转换的装置和方法。该装置可以具有可操作以接收输入电压并输出第一控制信号的第一放大器。该装置还可以具有可操作地耦合到第一放大器并被配置为基于第一控制信号输出第一信号的第一压控振荡器（VCO），第一信号具有传感器频率。该器件还可以具有可操作地耦合到第一VCO和第一放大器的第一开关电容器电阻器，第一开关电容器电阻器被配置为接收并由传感器频率控制。该装置还可以具有可操作地耦合到第一VCO并且被配置的传感器计数器基于传感器频率产生传感器计数。该器件还可以配置寄存器，以提供与输入电压成比例的数字输出，这取决于传感器数量。

24. 发明申请

WO2017034733A1 CALIBRATING FOR ON-RESISTANCE MISMATCH OF DIGITAL-TO-ANALOG CONVERTER (DAC) SWITCHES 审中-公开
标题翻译：数模转换器（DAC）开关的耐电阻校准校准
公开(公告)号：WO2017034733A1
公开(公告)日：2017-03-02
申请号：PCT/US2016/044034
申请日：2016-07-26
申请人： QUALCOMM INCORPORATED
发明人： TANG, Dongyang , DHANASEKARAN, Vijayakumar
IPC分类号： H03M1/06 , G05F3/24 , H03K17/06 , H03F1/30 , H03F3/30
CPC分类号： H03M1/66 , G05F3/24 , H03F1/301 , H03F3/3022 , H03F2200/453 , H03K17/063 , H03M1/0612 , H03M1/808
摘要： Certain aspects of the present disclosure provide methods and apparatus for setting a voltage level for controlling at least one of a first switch or a second switch, such that an on-resistance of the first switch matches an on-resistance of the second switch. One example circuit generally includes a third switch configured to replicate the first switch and a first cascode device connected in cascode with the third switch; a first amplifier configured to drive the first cascode device; a fourth switch configured to replicate the second switch; a second cascode device connected in cascode with the fourth switch; a second amplifier configured to drive the second cascode device; and a third amplifier configured to compare a voltage at a node coupled to the first and second cascode devices with a reference potential and to control the third switch based on the comparison to set the voltage level.
摘要翻译：本公开的某些方面提供了用于设置用于控制第一开关或第二开关中的至少一个的电压电平的方法和装置，使得第一开关的导通电阻与第二开关的导通电阻相匹配。一个示例电路通常包括被配置为复制第一开关的第三开关和与第三开关并联连接的第一共源共用器件; 第一放大器，被配置为驱动所述第一共源共用器件; 配置为复制所述第二开关的第四开关; 与第四开关串联连接的第二共源共用器件; 第二放大器，被配置为驱动所述第二共源共用器件; 以及第三放大器，被配置为将耦合到所述第一和第二共源共栅器件的节点处的电压与参考电位进行比较，并且基于所述比较来控制所述第三开关以设置所述电压电平。

25. 发明申请

WO2017029595A1 METHOD AND SYSTEM FOR IMPROVING SPURIOUS FREE DYNAMIC RANGE OF SIGNAL PROCESSING SYSTEMS 审中-公开
标题翻译：改善信号处理系统的自由动态范围的方法和系统
公开(公告)号：WO2017029595A1
公开(公告)日：2017-02-23
申请号：PCT/IB2016/054861
申请日：2016-08-12
申请人： CSIR
发明人： GOUWS, Marcel
IPC分类号： H04B1/12 , H04B1/04 , H03M1/06
CPC分类号： H04B1/0007 , H04B1/0475 , H04B1/12
摘要： This invention relates to a system and method for processing signals in a signal processing system so as at least to ameliorate spurious signals generated in said signal processing system during processing of signals. The method, which is implemented by the system in accordance with the invention, typically comprises receiving a signal of unknown and arbitrary frequency within the operating frequency range of the signal processing system, wherein the input signal comprises at least a fundamental signal. The method then comprises generating, in one signal processing path, a compensation signal with same amplitude and phase as the spurious signal. The compensation signal is then subtracted from the received input signal or added out of phase to the received input signal, in another signal processing path. In this way, the spurious signal is cancelled from the received signal and/or the received signal is pre-distorted to account for spurious signals generated during further processing in the signal processing system.
摘要翻译：本发明涉及一种用于处理信号处理系统中的信号的系统和方法，以至少在处理信号期间改善在所述信号处理系统中产生的寄生信号。由根据本发明的系统实现的方法通常包括在信号处理系统的工作频率范围内接收未知和任意频率的信号，其中输入信号至少包括基本信号。该方法然后包括在一个信号处理路径中产生与伪信号相同幅度和相位的补偿信号。然后，在另一个信号处理路径中，从接收的输入信号中减去补偿信号，或者将其相位相加到接收的输入信号。以这种方式，寄生信号从接收信号中消除和/或接收到的信号被预失真以考虑在信号处理系统中进一步处理期间产生的寄生信号。

26. 发明申请

WO2017008550A1 额外环路延迟补偿电路、方法、存储介质和模数转换器审中-公开
公开(公告)号：WO2017008550A1
公开(公告)日：2017-01-19
申请号：PCT/CN2016/079799
申请日：2016-04-20
申请人：深圳市中兴微电子技术有限公司
发明人：郑宇亮
IPC分类号： H03M3/00 , H03M1/06
CPC分类号： H03M1/06 , H03M3/00
摘要：一种ELD补偿电路，该电路用于对连续时间Δ-Σ模数转换器的ELD时间进行ELD补偿，该电路包括：延时模块（200）和补偿模块（201）；其中，延时模块（200）配置为在预设的多个延时时间中选择一个延时时间，基于所选择的延时时间将自身接收的信号延时输出；补偿模块（201）配置为根据延时模块（200）延时输出的信号进行ELD补偿。一种ELD补偿方法、计算机存储介质和连续时间Δ-Σ模数转换器。

27. 发明申请

WO2016108601A1 아날로그-디지털 변환기의 출력 신호 처리 장치 및 방법 审中-公开
标题翻译：用于处理模拟数字转换器输出信号的装置和方法
公开(公告)号：WO2016108601A1
公开(公告)日：2016-07-07
申请号：PCT/KR2015/014450
申请日：2015-12-29
申请人： 주식회사 쏠리드
发明人： 김형호 , 서광남 , 김도윤
IPC分类号： H03M1/06 , H03M1/12
CPC分类号： G01G23/10 , G01G3/1414 , G06F3/05 , H03D7/125 , H03D7/1441 , H03M1/0626 , H03M1/12 , H03M1/747 , H04B1/0483 , H04L25/03038 , H04L27/2647
摘要： 본 발명의 기술적 사상에 의한 일 양태에 따른 아날로그-디지털 변환기의 출력 신호 처리 장치는, 입력된 아날로그-디지털 변환기 출력 신호에서 불요파 성분이 존재하는 대역이 직류 성분이 존재하는 대역으로 이동되도록 아날로그-디지털 변환기 출력 신호를 주파수 변환하는 제1 주파수 변환부와, 제1 주파수 변환부의 출력 신호에서 직류 성분이 존재하는 대역으로 이동된 불요파 성분을 제거하는 불요파 성분 차단부, 및 불요파 성분 차단부의 출력 신호를 아날로그-디지털 변환기 출력 신호의 원 주파수로 복원하는 제2 주파수 변환부를 포함한다.
摘要翻译：根据本发明的技术方案的一个方面，用于处理模拟数字转换器的输出信号的装置包括：第一频率转换单元，用于转换输入的模数转换器输出信号的频率，使得在输入的模拟数字转换器输出信号，其中存在杂散波分量的频带移动到存在直流分量的频带; 用于从第一频率转换单元的输出信号中消除已经移动到存在直流分量的频带的寄生波分量的寄生波分量阻塞单元; 以及第二频率转换单元，用于将寄生波分量阻挡单元的输出信号恢复到模数转换器输出信号的原始频率。

28. 发明申请

WO2016029050A1 REDUCING SIGNAL DEPENDENCE FOR CDAC REFERENCE VOLTAGE 审中-公开
标题翻译：降低CDAC参考电压信号依赖性
公开(公告)号：WO2016029050A1
公开(公告)日：2016-02-25
申请号：PCT/US2015/046161
申请日：2015-08-20
申请人： QUALCOMM INCORPORATED
发明人： MIRHAJ, Seyed Arash , WADHWA, Sameer , ALLADI, Dinesh Jagannath , YAMAMOTO, Kentaro , WEN, Xiaoke , ENSAFDARAN, Masoud , CHEN, Weihua
IPC分类号： H03M1/06
CPC分类号： H03M1/72 , H03M1/0612 , H03M1/66 , H03M1/804 , H03M1/806
摘要： Reducing signal dependence for a reference voltage of a CDAC includes: splitting a decoupling capacitor into a plurality of capacitors smaller in size than a size of the decoupling capacitor; isolating at least one of the plurality of capacitors from a sampling buffer coupled to the reference voltage during a conversion phase; and supplying an appropriate amount of charge needed to replenish charge drawn by capacitors in the CDAC at each conversion step using a charge pump to pump in a dummy charge to the CDAC so that resulting configurations of the CDAC draw substantially similar amount of charge for each code change of the each conversion step.
摘要翻译：降低对CDAC的参考电压的信号依赖性包括：将去耦电容器分成尺寸小于去耦电容器的尺寸的多个电容器; 在转换阶段期间将耦合到参考电压的采样缓冲器中的至少一个电容器隔离; 并且在每个转换步骤中使用电荷泵提供在CDAC中由电容器吸收的电荷所需的适当量的电荷，以将虚拟电荷泵送到CDAC，使得CDAC的所得结构为每个代码绘制基本相似的电荷量更改每个转换步骤。

29. 发明申请

WO2015160769A1 POST CONVERSION MIXING 审中-公开
标题翻译：后转换混合
公开(公告)号：WO2015160769A1
公开(公告)日：2015-10-22
申请号：PCT/US2015/025699
申请日：2015-04-14
申请人： NIENABER II, David, K.
发明人： NIENABER II, David, K.
IPC分类号： H03M1/06
CPC分类号： H04B1/1036 , H04B1/0003 , H04B1/0014 , H04B1/10 , H04B1/109 , H04B1/16 , H04B1/44 , H04L25/4906 , H04L27/0006 , H04L27/14
摘要： An input signal having at least one modulated signal is captured. At least four analog sample streams are generated from the input signal. Each analog sample stream is generated by sampling the input signal at a frequency substantially equal to the frequency at which each other analog sample stream is generated and at a phase separate from that at which each other analog sample stream is generated. For each analog sample stream, multiple analog samples of the analog sample stream are combined to create a bandwidth adjusted signal. The bandwidth adjusted signals are jointly representative of the input signal.
摘要翻译：捕获具有至少一个调制信号的输入信号。从输入信号产生至少四个模拟采样流。每个模拟采样流通过以与产生每个其它模拟采样流的频率基本相等的频率并且与产生每个其它模拟采样流的频率分开的阶段对输入信号进行采样而产生。对于每个模拟采样流，组合模拟采样流的多个模拟样本以产生带宽调整信号。带宽调整后的信号共同代表输入信号。

30. 发明申请

WO2015035352A1 SAMPLING INPUT STAGE WITH MULTIPLE CHANNELS 审中-公开
标题翻译：采用多通道采样输入级
公开(公告)号：WO2015035352A1
公开(公告)日：2015-03-12
申请号：PCT/US2014/054666
申请日：2014-09-09
申请人： MICROCHIP TECHNOLOGY INCORPORATED
发明人： MEACHAM, Daniel, R. , PANIGADA, Andrea , SHIH, David
IPC分类号： G11C27/02 , H03M1/12 , H03M1/06
CPC分类号： H03M1/08 , G11C27/02 , G11C27/024 , H03M1/066 , H03M1/1033 , H03M1/12 , H03M1/1205 , H03M1/122 , H03M1/1225 , H03M1/167 , H03M1/36
摘要： An analog input stage has m differential input channels, wherein m>l. The analog input stage is configured to select one of the m differential input channels and provide an output signal. The analog input stage has n identical selection units each having m differential channel inputs and one differential output, wherein n is at least 2111"1. Each selection unit is operable to be coupled to any of the differential input channels through respective differential multiplexer units, wherein the multiplexor units are driven to select one of the differential input channels and couple the selected differential channel input through a butterfly switch unit with the differential output of the selection unit. The differential output signals of the n selection units are combined whereby unwanted crosstalk from channels other than a selected channel are removed by cancellation.
摘要翻译：模拟输入级具有m个差分输入通道，其中m> 1。模拟输入级被配置为选择m个差分输入通道之一并提供输出信号。模拟输入级具有n个相同的选择单元，每个具有m个差分通道输入和一个差分输出，其中n至少为2111“1，每个选择单元可操作以通过相应的差分多路复用器单元耦合到任何差分输入通道，其中驱动所述多路复用器单元以选择所述差分输入通道之一并通过蝶形开关单元与所述选择单元的差分输出耦合所选择的差分通道输入，所述n个选择单元的差分输出信号被组合，通过取消除去选定频道以外的频道。

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