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21. 发明申请

WO2014164358A1 METHOD AND SEMICONDUCTOR APPARATUS FOR REDUCING POWER WHEN TRANSMITTING DATA BETWEEN DEVICES IN THE SEMICONDUCTOR APPARATUS 审中-公开
标题翻译：用于在半导体装置中的器件之间传输数据时减少功率的方法和半导体装置
公开(公告)号：WO2014164358A1
公开(公告)日：2014-10-09
申请号：PCT/US2014/022110
申请日：2014-03-07
申请人： QUALCOMM INCORPORATED
发明人： JUNG, Chulmin , YOON, Sei Seung , TERZIOGLU, Esin , ANANTHANARAYANAN, Hari , BOYNAPALLI, Venugopal
IPC分类号： G11C7/10 , G06F13/42
CPC分类号： H03K17/002 , G11C7/02 , G11C7/10 , G11C7/1006
摘要： A semiconductor apparatus is provided herein for reducing power when transmitting data between a first device and a second device in the semiconductor apparatus. Additional circuitry is added to the semiconductor apparatus to create a communication system that decreases a number of state changes for each signal line of a data bus between the first device and the second device for all communications. The additional circuitry includes a decoder coupled to receive and convert a value from the first device for transmission over the data bus to an encoder that provides a recovered (i.e., re-encoded) version of the value to the second device. One or more multiplexers may also be included in the additional circuitry to support any number of devices.
摘要翻译：本发明提供一种半导体装置，用于在半导体装置中的第一装置和第二装置之间传输数据时降低功率。将另外的电路添加到半导体装置中以创建通信系统，其减少用于所有通信的第一设备和第二设备之间的数据总线的每个信号线的状态变化的数量。附加电路包括解码器，其耦合以接收和转换来自第一设备的值，用于通过数据总线传输到向第二设备提供值的恢复（即重新编码）版本的编码器。一个或多个多路复用器也可以包括在附加电路中以支持任何数量的设备。

22. 发明申请

WO2019160607A1 STAGGERED SELF ALIGNED GATE CONTACT 审中-公开
公开(公告)号：WO2019160607A1
公开(公告)日：2019-08-22
申请号：PCT/US2018/067046
申请日：2018-12-21
申请人： QUALCOMM INCORPORATED
发明人： LIM, Hyeokjin , CHEN, Xiangdong , HIREMATH, Renukprasad , LI, Rui , BOYNAPALLI, Venugopal
IPC分类号： H01L21/8234 , H01L21/8238 , H01L23/528 , H01L27/02 , H01L27/088 , H01L27/092
摘要： A semiconductor die includes a first diffusion region and a plurality of gates extending across the diffusion region. The plurality of gates are substantially parallel to each other. An interconnect layer above the diffusion region and plurality of gates includes a plurality of signal traces extending in a direction substantially perpendicular to the gates. At least two of the plurality of signal traces are located directly above the diffusion region such that at intersections of two gates with two separate signal traces are in the active transistor region, that is the portion of the gate extending over the diffusion region. Gate contacts coupling the two gates to the two separate signal traces are staggered by coupling to different signal traces.

23. 发明申请

WO2018125546A1 MULTIPLE VIA STRUCTURE FOR HIGH PERFORMANCE STANDARD CELLS 审中-公开
公开(公告)号：WO2018125546A1
公开(公告)日：2018-07-05
申请号：PCT/US2017/065429
申请日：2017-12-08
申请人： QUALCOMM INCORPORATED
发明人： SAHU, Satyanarayana , CHEN, Xiangdong , BOYNAPALLI, Venugopal , LIM, Hyeokjin , MALABRY, Mickael , GUPTA, Mukul
IPC分类号： H01L27/02 , H01L23/528 , H01L27/118
摘要： A MOS device of an IC includes pMOS and nMOS transistors. The MOS device further includes a first Mx layer interconnect extending in a first direction and coupling the pMOS and nMOS transistor drains together, and a second M x layer interconnect extending in the first direction and coupling the pMOS and nMOS transistor drains together. The first and second M x layer interconnects are parallel. The MOS device further includes a first M x+1 layer interconnect extending in a second direction orthogonal to the first direction. The first M x+1 layer interconnect is coupled to the first M x layer interconnect and the second M x layer interconnect. The MOS device further includes a second M x+1 layer interconnect extending in the second direction. The second M x+1 layer interconnect is coupled to the first M x layer interconnect and the second M x layer interconnect. The second M x+1 layer interconnect is parallel to the first M x+1 layer interconnect.

24. 发明申请

WO2018106372A1 A PULSE-STRETCHER CLOCK GENERATOR CIRCUIT AND CLOCK GENERATION METHOD FOR HIGH SPEED MEMORY SUBSYSTEMS 审中-公开
公开(公告)号：WO2018106372A1
公开(公告)日：2018-06-14
申请号：PCT/US2017/060213
申请日：2017-11-06
申请人： QUALCOMM INCORPORATED
发明人： KUMAR, Dorav , NARAYANAN, Venkat , ZAFAR, Bilal , RASOULI, Seid Hadi , BOYNAPALLI, Venugopal
IPC分类号： G11C7/22 , G06F13/16
摘要： The apparatus provided includes a memory. The memory is configured to receive a memory clock. The apparatus also includes a single stage logic gate configured to generate the memory clock from a reference clock. The memory clock is a gated clock. Additionally, the memory clock has a wider pulse width than the reference clock. In an example, the single stage logic gate comprises a pull-up circuit configured to pull-up the memory clock, and a pull-down circuit coupled to pull-down the memory clock. In an example, the pull-up and the pull-down circuits are configured to be controlled by the reference clock, a delayed reference clock, and a gating signal. An example further includes a delay circuit configured to generate the delayed reference clock from the reference clock. An example further includes a latch configured to generate the gating signal.

25. 发明申请

WO2017218360A1 A STANDARD CELL ARCHITECTURE FOR PARASITIC RESISTANCE REDUCTION 审中-公开
标题翻译：用于降低寄生虫抗性的标准细胞结构
公开(公告)号：WO2017218360A1
公开(公告)日：2017-12-21
申请号：PCT/US2017/036865
申请日：2017-06-09
申请人： QUALCOMM INCORPORATED
发明人： CHEN, Xiangdong , LIM, Hyeokjin Bruce , SAHU, Satyanarayana , BOYNAPALLI, Venugopal
IPC分类号： H01L27/02 , H01L23/528 , H01L27/118
CPC分类号： H01L29/0646 , H01L23/528 , H01L23/535 , H01L27/0207 , H01L27/11807 , H01L2027/11875
摘要： A MOS IC (300) includes a first contact interconnect (330) in a first standard cell (302a) that extends in a first direction and contacts a first MOS transistor source (310) and a voltage source (342). Still further, the MOS IC includes a first double diffusion break extending along a first boundary (344) in the first direction of the first standard cell and a second standard cell (302b). The MOS IC also includes a second contact interconnect (360) extending over a portion of the first double diffusion break. In an aspect, the second contact interconnect is within both the first standard cell and the second standard cell and coupled to the voltage source. Additionally, the MOS IC includes a third contact interconnect (362) extending in a second direction orthogonal to the first direction and coupling the first contact interconnect and the second contact interconnect together.
摘要翻译： MOS IC（300）包括在第一标准单元（302a）中的第一接触互连（330），其在第一方向上延伸并接触第一MOS晶体管源极（310）和电压源（342）。另外，MOS IC包括沿着第一标准单元的第一方向上的第一边界（344）和第二标准单元（302b）延伸的第一双扩散中断。 MOS IC还包括在第一双扩散分裂的一部分上延伸的第二接触互连（360）。在一个方面，第二接触互连在第一标准单元和第二标准单元两者内并耦合到电压源。此外，MOS IC包括在与第一方向正交的第二方向上延伸并且将第一接触互连和第二接触互连耦合在一起的第三接触互连（362）。

26. 发明申请

WO2017151293A1 LOW-AREA LOW CLOCK-POWER FLIP-FLOP 审中-公开
标题翻译：低面积低功耗FLIP-FLOP
公开(公告)号：WO2017151293A1
公开(公告)日：2017-09-08
申请号：PCT/US2017/017459
申请日：2017-02-10
申请人： QUALCOMM INCORPORATED
发明人： RASOULI, Seid Hadi , CHEN, Xiangdong , BOYNAPALLI, Venugopal
IPC分类号： H03K3/012 , H03K3/3562
CPC分类号： H03K3/012 , H03K3/356104 , H03K3/35625
摘要： In one example, the apparatus includes a first AND gate, a second AND gate, a first NOR gate, a second NOR gate, a third NOR gate, a first inverter, and a second inverter. The first AND gate output is coupled to the first NOR gate first input. The first NOR gate output is coupled to the second NOR gate first input. The second NOR gate output is coupled to the first NOR gate second input. The first inverter output is coupled to the first AND gate second input and the second NOR gate second input. The second AND gate first input is coupled to the first inverter output. The third NOR gate first input is coupled to the second NOR gate output. The third NOR gate second input is coupled to the second AND gate output. The second inverter output is coupled to the second AND gate second input.
摘要翻译：在一个示例中，该装置包括第一与门，第二与门，第一或非门，第二或非门，第三或非门，第一反相器和第二反相器。第一与门输出耦合到第一或非门第一输入。第一或非门输出端耦合到第二或非门第一输入端。第二或非门输出耦合到第一或非门第二输入。第一反相器输出端耦合到第一与门第二输入端和第二或非门第二输入端。第二与门的第一输入端耦合到第一反相器输出端。第三NOR门第一输入端连接到第二NOR门输出端。第三或非门第二输入端耦合到第二与门输出端。第二个反相器输出端连接到第二个与门第二个输入端。

27. 发明申请

WO2017053065A1 SOURCE SEPARATED CELL 审中-公开
标题翻译：源分离细胞
公开(公告)号：WO2017053065A1
公开(公告)日：2017-03-30
申请号：PCT/US2016/050571
申请日：2016-09-07
申请人： QUALCOMM INCORPORATED
发明人： SAHU, Satyanarayana , CHEN, Xiangdong , BOYNAPALLI, Venugopal , LIM, Hyeokjin Bruce , GUPTA, Mukul , KANG, Hananel , KAO, Chih-lung , GUTTAL, Radhika
IPC分类号： H01L27/02 , H01L27/088 , H01L21/8234 , H01L27/092
CPC分类号： H03K19/0948 , H01L21/823481 , H01L23/528 , H01L27/0207 , H01L27/088 , H01L27/0886 , H01L27/092 , H01L27/0924
摘要： A MOS device includes a first MOS transistor having a first MOS transistor source, a first MOS transistor drain, and a first MOS transistor gate. The MOS device also includes a second MOS transistor having a second MOS transistor source, a second MOS transistor drain, and a second MOS transistor gate. The second MOS transistor source and the first MOS transistor source are coupled to a first voltage source. The MOS device includes a third MOS transistor having a third MOS transistor gate, the third MOS transistor gate between the first MOS transistor source and the third MOS transistor source, the third MOS transistor further having a third MOS transistor source and a third MOS transistor drain, the third MOS transistor source being coupled to the first MOS transistor source, the third MOS transistor drain being coupled to the second MOS transistor source, the third MOS transistor gate floating.
摘要翻译： MOS器件包括具有第一MOS晶体管源极，第一MOS晶体管漏极和第一MOS晶体管栅极的第一MOS晶体管。 MOS器件还包括具有第二MOS晶体管源极，第二MOS晶体管漏极和第二MOS晶体管栅极的第二MOS晶体管。第二MOS晶体管源和第一MOS晶体管源耦合到第一电压源。 MOS器件包括具有第三MOS晶体管栅极的第三MOS晶体管，第一MOS晶体管源极和第三MOS晶体管源极之间的第三MOS晶体管栅极，第三MOS晶体管还具有第三MOS晶体管源极和第三MOS晶体管漏极所述第三MOS晶体管源耦合到所述第一MOS晶体管源，所述第三MOS晶体管漏极耦合到所述第二MOS晶体管源，所述第三MOS晶体管栅极浮置。

28. 发明申请

WO2011109771A1 SYSTEM AND METHOD OF TESTING AN ERROR CORRECTION MODULE 审中-公开
标题翻译：系统和测试错误校正模块的方法
公开(公告)号：WO2011109771A1
公开(公告)日：2011-09-09
申请号：PCT/US2011/027286
申请日：2011-03-04
申请人： QUALCOMM INCORPORATED , RAO, Hari M. , NAZAR, Shahzad , BOYNAPALLI, Venugopal
发明人： RAO, Hari M. , NAZAR, Shahzad , BOYNAPALLI, Venugopal
IPC分类号： G11C29/02
CPC分类号： G11C29/02
摘要： In an embodiment, a method of testing an error correction scheme includes selectively observing and controlling data at one or more intermediate test points within an error correction circuit. Erroneous data may be selectively injected at a first intermediate test point and data related to the erroneous data may be observed at a second intermediate test point.
摘要翻译：在一个实施例中，测试纠错方案的方法包括在误差校正电路内的一个或多个中间测试点选择性地观察和控制数据。可以在第一中间测试点选择性地注入错误数据，并且可以在第二中间测试点观察与错误数据相关的数据。

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