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21. 发明申请

WO2016209278A1 HIGH ELECTRON MOBILITY TRANSISTORS WITH LOCALIZED SUB-FIN ISOLATION 审中-公开
标题翻译：具有局部分散分离的高电子移动晶体管
公开(公告)号：WO2016209278A1
公开(公告)日：2016-12-29
申请号：PCT/US2015/038069
申请日：2015-06-26
申请人： INTEL CORPORATION
发明人： RACHMADY, Willy , METZ, Matthew V. , DEWEY, Gilbert , MOHAPATRA, Chandra S. , KAVALIEROS, Jack T. , MURTHY, Anand S. , GHANI, Tahir , RAHHAL-ORABI, Nadia M. , GARDNER, Sanaz K.
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/78609 , H01L29/0673 , H01L29/42392 , H01L29/66522 , H01L29/66742 , H01L29/66795 , H01L29/785 , H01L29/78681 , H01L29/78696
摘要： Crystalline heterostructures including an elevated fin structure extending from a sub-fin structure over a substrate. Devices, such as III-V transistors, may be formed on the raised fin structures while silicon-based devices (e.g., transistors) may be formed in other regions of the silicon substrate. A sub-fin isolation material localized to a transistor channel region of the fin structure may reduce source-to-drain leakage through the sub-fin, improving electrical isolation between source and drain ends of the fin structure. Subsequent to heteroepitaxially forming the fin structure, a portion of the sub-fin may be laterally etched to undercut the fin. The undercut is backfilled with sub-fin isolation material. A gate stack is formed over the fin. Formation of the sub-fin isolation material may be integrated into a self-aligned gate stack replacement process.
摘要翻译：结晶异质结构包括从基底上的亚鳍结构延伸的翅片结构。诸如III-V晶体管的器件可以形成在凸起鳍结构上，而硅基器件（例如，晶体管）可以形成在硅衬底的其它区域中。位于翅片结构的晶体管沟道区域的子鳍片隔离材料可以减少通过子鳍片的源极到漏极泄漏，从而改善翅片结构的源极和漏极端之间的电隔离。在异质外延形成翅片结构之后，副翅片的一部分可以被横向蚀刻以切割翅片。底切用亚翅片隔离材料回填。栅极堆叠形成在鳍上。子鳍隔离材料的形成可以集成到自对准的栅堆叠替换工艺中。

22. 发明申请

WO2016209253A8 TRANSISTOR FIN FORMATION VIA CLADDING ON SACRIFICIAL CORE 审中-公开
标题翻译：通过牺牲芯上的包层形成晶体管鳍
公开(公告)号：WO2016209253A8
公开(公告)日：2016-12-29
申请号：PCT/US2015/037921
申请日：2015-06-26
申请人： INTEL CORPORATION
发明人： GLASS, Glenn A. , MURTHY, Anand S. , AUBERTINE, Daniel B. , GHANI, Tahir , KAVALIEROS, Jack T. , CHU-KUNG, Benjamin , MOHAPATRA, Chandra S. , JAMBUNATHAN, Karthik , DEWEY, Gilbert , RACHMADY, Willy
IPC分类号： H01L29/78 , H01L21/336
摘要： Techniques are disclosed for customization of fin-based transistor devices to provide a diverse range of channel configurations and/or material systems, and within the same integrated circuit die. In accordance with an embodiment, sacrificial fins are cladded and then removed thereby leaving the cladding layer as a pair of standalone fins. Once the sacrificial fin areas are filled back in with a suitable insulator, the resulting structure is fin-on-insulator. The new fins can be configured with any materials by using such a cladding-on-core approach. The resulting fin-on-insulator structure is favorable, for instance, for good gate control while eliminating or otherwise reducing sub-channel source-to-drain (or drain-to-source) leakage current. In addition, parasitic capacitance from channel-to-substrate is significantly reduced. The sacrificial fins can be thought of as cores and can be implemented, for example, with material native to the substrate or a replacement material that enables low-defect exotic cladding materials combinations.
摘要翻译：公开了用于定制基于鳍片的晶体管器件以提供多种通道配置和/或材料系统以及在同一集成电路管芯内的技术。根据一个实施例，牺牲散热片被包覆并且然后被去除，从而留下包层作为一对独立的散热片。一旦牺牲翅片区域用合适的绝缘体填满，所得到的结构就是绝缘体上的鳍片。通过使用这种核心包层方法，新翅片可以用任何材料配置。例如，对于良好的栅极控制，同时消除或以其他方式减少子沟道源极至漏极（或漏极至源极）泄漏电流而言，所得到的绝缘体上鳍状物结构是有利的。另外，通道到衬底的寄生电容显着降低。牺牲鳍可以被认为是核心，并且可以被实施，例如，利用基板本身的材料或替代材料来实现低缺陷的异质包层材料组合。

23. 发明申请

WO2016209253A1 TRANSISTOR FIN FORMATION VIA CLADDING ON SACRIFICAL CORE 审中-公开
标题翻译：晶体管熔化形成通过密封核的分离
公开(公告)号：WO2016209253A1
公开(公告)日：2016-12-29
申请号：PCT/US2015/037921
申请日：2015-06-26
申请人： INTEL CORPORATION
发明人： GLASS, Glenn A. , MURTHY, Anand S. , AUBERTINE, Daniel B. , GHANI, Tahir , KAVALIEROS, Jack T. , CHU-KUNG, Benjamin , MOHAPATRA, Chandra S. , JAMBUNATHAN, Karthik , DEWEY, Gilbert , RACHMADY, Willy
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L27/1211 , H01L21/76224 , H01L21/845 , H01L29/0649 , H01L29/0673 , H01L29/161 , H01L29/20 , H01L29/66545 , H01L29/66795 , H01L29/78
摘要： Techniques are disclosed for customization of fin-based transistor devices to provide a diverse range of channel configurations and/or material systems, and within the same integrated circuit die. In accordance with an embodiment, sacrificial fins are cladded and then removed thereby leaving the cladding layer as a pair of standalone fins. Once the sacrificial fin areas are filled back in with a suitable insulator, the resulting structure is fin-on-insulator. The new fins can be configured with any materials by using such a cladding-on-core approach. The resulting fin-on-insulator structure is favorable, for instance, for good gate control while eliminating or otherwise reducing sub-channel source-to-drain (or drain-to-source) leakage current. In addition, parasitic capacitance from channel-to-substrate is significantly reduced. The sacrificial fins can be thought of as cores and can be implemented, for example, with material native to the substrate or a replacement material that enables low-defect exotic cladding materials combinations.
摘要翻译：公开了用于定制鳍式晶体管器件以提供不同范围的通道配置和/或材料系统以及在同一集成电路管芯内的技术。根据一个实施例，牺牲翅片被包覆然后去除，从而使包层作为一对独立的翅片。一旦牺牲翅片区域被合适的绝缘体填充回来，所得到的结构是绝缘体上的鳍。新的散热片可以通过使用这种包芯方法来配置任何材料。所产生的绝缘体上的结构是有利的，例如，为了良好的栅极控制，同时消除或以其它方式减少子沟道源极到漏极（或漏极 - 源极）泄漏电流。此外，从通道到衬底的寄生电容显着降低。牺牲翅片可以被认为是核心，并且可以例如用基材原生的材料或能够实现低缺陷异质包覆材料组合的替代材料来实现。

24. 发明申请

WO2016209210A1 INDIUM-RICH NMOS TRANSISTOR CHANNELS 审中-公开
标题翻译： INDIUM-RICH NMOS晶体管通道
公开(公告)号：WO2016209210A1
公开(公告)日：2016-12-29
申请号：PCT/US2015/037141
申请日：2015-06-23
申请人： INTEL CORPORATION
发明人： MOHAPATRA, Chandra S. , MURTHY, Anand S. , GLASS, Glenn A. , GHANI, Tahir , RACHMADY, Willy , KAVALIEROS, Jack T. , DEWEY, Gilbert , METZ, Matthew V. , KENNEL, Harold W.
IPC分类号： H01L29/78
CPC分类号： H01L29/785 , H01L27/0886 , H01L29/1054 , H01L29/125 , H01L29/205 , H01L29/66795 , H01L29/775
摘要： Techniques are disclosed for forming high mobility NMOS fin-based transistors having an indium-rich channel region electrically isolated from the sub-fin by an aluminum-containing layer. The aluminum aluminum-containing layer may be provisioned within an indium-containing layer that includes the indium-rich channel region, or may be provisioned between the indium-containing layer and the sub-fin. The indium concentration of the indium-containing layer may be graded from an indium-poor concentration near the aluminum-containing barrier layer to an indium-rich concentration at the indium-rich channel layer. The indium-rich channel layer is at or otherwise proximate to the top of the fin, according to some example embodiments. The grading can be intentional and/or due to the effect of reorganization of atoms at the interface of indium-rich channel layer and the aluminum-containing barrier layer. Numerous variations and embodiments will be appreciated in light of this disclosure.
摘要翻译：公开了用于形成具有通过含铝层与子鳍电隔离的富铟沟道区的高迁移率的NMOS鳍状晶体管的技术。含铝的铝层可以设置在包含富铟沟道区域的含铟层内，或者可以在含铟层和副散热片之间设置。含铟层的铟浓度可以从富含铟的沟道层的含铝阻挡层附近的铟 - 贫的浓度分级为富铟浓度。根据一些示例性实施例，富铟通道层处于或接近翅片的顶部。分级可以是有意的和/或由于在富铟沟道层和含铝阻挡层的界面处重组原子的作用。根据本公开将理解许多变型和实施例。

25. 发明申请

WO2018004630A1 A FINFET TRANSISTOR HAVING A DOPED SUBFIN STRUCTURE TO REDUCE CHANNEL TO SUBSTRATE LEAKAGE 审中-公开
标题翻译：具有掺杂亚基结构以减少通道至基板泄漏的FINFET晶体管
公开(公告)号：WO2018004630A1
公开(公告)日：2018-01-04
申请号：PCT/US2016/040559
申请日：2016-06-30
申请人： INTEL CORPORATION
发明人： DEWEY, Gilbert , METZ, Matthew V. , RACHMADY, Willy , MURTHY, Anand S. , MOHAPATRA, Chandra S. , GHANI, Tahir , MA, Sean T. , KAVALIEROS, Jack T.
IPC分类号： H01L29/78 , H01L21/02 , H01L29/66 , H01L21/8234
CPC分类号： H01L29/1054 , H01L29/66 , H01L29/66795 , H01L29/785 , H01L29/7851
摘要： An apparatus is described. The apparatus includes a FINFET device having a channel. The channel is composed of a first semiconductor material that is epitaxially grown on a subfin structure beneath the channel. The subfin structure is composed of a second semiconductor material that is different than the first semiconductor material. The subfin structure is epitaxially grown on a substrate composed of a third semiconductor material that is different than the first and second semiconductor materials. The subfin structure has a doped region to substantially impede leakage currents between the channel and the substrate.
摘要翻译：描述了一种装置。该装置包括具有通道的FINFET器件。沟道由在沟道下方的亚鳍结构上外延生长的第一半导体材料组成。该子鳍状结构由与第一半导体材料不同的第二半导体材料构成。该子鳍状结构在由与第一和第二半导体材料不同的第三半导体材料构成的衬底上外延生长。该子结构具有掺杂区域以基本上阻止沟道和衬底之间的泄漏电流。

26. 发明申请

WO2017218014A1 FIELD EFFECT TRANSISTORS WITH GATE ELECTRODE SELF-ALIGNED TO SEMICONDUCTOR FIN 审中-公开
标题翻译：具有自对准于半导体鳍的栅电极的场效应晶体管
公开(公告)号：WO2017218014A1
公开(公告)日：2017-12-21
申请号：PCT/US2016/038208
申请日：2016-06-17
申请人： INTEL CORPORATION
发明人： MA, Sean T. , METZ, Matthew V. , RACHMADY, Willy , DEWEY, Gilbert , MOHAPATRA, Chandra S. , KAVALIEROS, Jack T. , MURTHY, Anand S. , GHANI, Tahir
IPC分类号： H01L29/78 , H01L29/423
CPC分类号： H01L29/785 , H01L29/1054 , H01L29/66545 , H01L29/66795 , H01L29/7848 , H01L29/7853
摘要： Monolithic FETs including a fin of a first semiconductor composition disposed on a sub-fin of a second composition. In some examples, an InGaAs fin is grown over GaAs sub-fin. The sub-fin may be epitaxially grown from a seeding surface disposed within a trench defined in an isolation dielectric. The sub-fin may be planarized with the isolation dielectric. The fin may then be epitaxially grown from the planarized surface of the sub-fin. A gate stack may be disposed over the fin with the gate stack contacting the planarized surface of the isolation dielectric so as to be self-aligned with the interface between the fin and sub-fin. Other embodiments may be described and/or claimed.
摘要翻译：包括设置在第二组合物的子鳍上的第一半导体组合物的鳍状物的单片式FET。在一些示例中，InGaAs鳍片生长在GaAs子鳍片之上。子鳍状物可以从设置在隔离电介质中限定的沟槽内的播种表面外延生长。子鳍状物可以用隔离电介质平坦化。然后可以从子鳍状物的平坦表面外延生长鳍状物。栅叠层可以设置在鳍上方，栅叠层接触隔离电介质的平坦化表面以便与鳍和子鳍之间的界面自对准。其他实施例可以被描述和/或要求保护。

27. 发明申请

WO2017052619A1 HIGH MOBILITY FIELD EFFECT TRANSISTORS WITH A RETROGRADED SEMICONDUCTOR SOURCE/DRAIN 审中-公开
标题翻译：具有复位半导体源/漏极的高移动场效应晶体管
公开(公告)号：WO2017052619A1
公开(公告)日：2017-03-30
申请号：PCT/US2015/052345
申请日：2015-09-25
申请人： INTEL CORPORATION
发明人： DEWEY, Gilbert , RACHMADY, Willy , METZ, Matthew V. , MOHAPATRA, Chandra S. , MA, Sean T. , KAVALIEROS, Jack T. , MURTHY, Anand S. , GHANI, Tahir
IPC分类号： H01L29/78 , H01L21/8238 , H01L21/336
CPC分类号： H01L29/201 , B82Y10/00 , H01L21/823807 , H01L21/8258 , H01L27/0924 , H01L29/0673 , H01L29/42356 , H01L29/42392 , H01L29/66469 , H01L29/775
摘要： Monolithic FETs including a channel region of a first semiconductor material disposed over a substrate. While a mask, such as a gate stack or sacrificial gate stack, is covering the channel region, an impurity-doped compositionally graded semiconductor is grown, for example on at least a drain end of the channel region to introduce a carrier-blocking conduction band offset and/or a wider band gap within the drain region of the transistor. In some embodiments, the compositional grade induces a carrier-blocking band offset of at least 0.25 eV. The wider band gap and/or band offset contributes to a reduced gate induced drain leakage (GIDL). The impurity-doped semiconductor may be compositionally graded back down from the retrograded composition to a suitably narrow band gap material providing good ohmic contact. In some embodiments, the impurity-doped compositionally graded semiconductor growth is integrated into a gate-last, source/drain regrowth finFET fabrication process.
摘要翻译：整体FET包括设置在衬底上的第一半导体材料的沟道区。虽然诸如栅极堆叠或牺牲栅极堆叠的掩模覆盖沟道区域，但是例如在沟道区域的至少漏极端上生长杂质掺杂的组成梯度半导体以引入载流子阻挡导带偏移和/或晶体管的漏极区域内的更宽的带隙。在一些实施方案中，组成级别诱导至少0.25eV的载流子阻挡带偏移。较宽的带隙和/或带偏移有助于降低栅极感应漏极泄漏（GIDL）。掺杂杂质的半导体可以从退化的组合物组分地退化到提供良好的欧姆接触的合适的窄带隙材料。在一些实施例中，杂质掺杂的组成渐变的半导体生长被集成到栅极 - 末端，源/漏再生长finFET制造工艺中。

28. 发明申请

WO2017052608A1 HIGH-ELECTRON-MOBILITY TRANSISTORS WITH COUNTER-DOPED DOPANT DIFFUSION BARRIER 审中-公开
标题翻译：具有倒计数铒扩散阻挡层的高电子移动晶体管
公开(公告)号：WO2017052608A1
公开(公告)日：2017-03-30
申请号：PCT/US2015/052299
申请日：2015-09-25
申请人： INTEL CORPORATION
发明人： MOHAPATRA, Chandra S. , KENNEL, Harold W. , METZ, Matthew V. , DEWEY, Gilbert , RACHMADY, Willy , MURTHY, Anand S. , KAVALIEROS, Jack T. , GHANI, Tahir
IPC分类号： H01L29/778
CPC分类号： H01L29/66795 , H01L21/02381 , H01L21/0243 , H01L21/02455 , H01L21/02494 , H01L21/02538 , H01L21/02639
摘要： III-V compound semiconductor devices, such transistors, may be formed in active regions of a III-V semiconductor material disposed over a silicon substrate. A counter-doped portion of a III-V semiconductor material provides a diffusion barrier retarding diffusion of silicon from the substrate into III-V semiconductor material where it might otherwise behave as electrically active amphoteric contaminate in the III-V material. In some embodiments, counter-dopants (e.g., acceptor impurities) are introduced in-situ during epitaxial growth of a base portion of a sub-fin structure. With the counter-doped region limited to a base of the sub-fin structure, risk of the counter-dopant atoms thermally diffusing into an active region of a III-V transistor is mitigated.
摘要翻译：可以在配置在硅衬底上的III-V半导体材料的有源区中形成这种晶体管的III-V族化合物半导体器件。 III-V半导体材料的反掺杂部分提供硅从衬底到III-V半导体材料的扩散阻挡扩散扩散，否则其可能在III-V材料中表现为电活性两性污染物。在一些实施方案中，在辅助翅片结构的基底部分的外延生长期间原位引入反掺杂剂（例如，受主杂质）。由于反掺杂区域限于亚鳍结构的基极，减轻了对掺杂剂原子热扩散到III-V晶体管的有源区的风险。

29. 发明申请

WO2016209285A1 PSEUDOMORPHIC INGAAS ON GAAS FOR GATE-ALL-AROUND TRANSISTORS 审中-公开
标题翻译：用于全息环绕晶体管的GAAS上的PSEUDOMORPHIC INGAAS
公开(公告)号：WO2016209285A1
公开(公告)日：2016-12-29
申请号：PCT/US2015/038105
申请日：2015-06-26
申请人： INTEL CORPORATION , MOHAPATRA, Chandra S. , MURTHY, Anand S. , GLASS, Glenn A. , RACHMADY, Willy , DEWEY, Gilbert , KAVALIEROS, Jack T. , GHANI, Tahir , METZ, Matthew V.
发明人： MOHAPATRA, Chandra S. , MURTHY, Anand S. , GLASS, Glenn A. , RACHMADY, Willy , DEWEY, Gilbert , KAVALIEROS, Jack T. , GHANI, Tahir , METZ, Matthew V.
IPC分类号： H01L21/762 , H01L21/336 , H01L29/78
CPC分类号： H01L29/66522 , H01L21/30612 , H01L21/762 , H01L29/0653 , H01L29/0673 , H01L29/42392 , H01L29/66469 , H01L29/6653 , H01L29/66545 , H01L29/66553 , H01L29/66742 , H01L29/6681 , H01L29/775 , H01L29/78 , H01L29/7853 , H01L29/78681 , H01L29/78696
摘要： A non-planar gate all-around device and method of fabrication thereby are described. In one embodiment, a multi-layer stack is formed by selectively depositing the entire epi-stack in an STI trench. The channel layer is grown pseudomorphically over a buffer layer. A cap layer is grown on top of the channel layer. In an embodiment, the height of the STI layer remains higher than the channel layer until the formation of the gate. A gate dielectric layer is formed on and all-around each channel nanowire. A gate electrode is formed on the gate dielectric layer and surrounding the channel nanowire.
摘要翻译：描述了非平面栅极全面器件及其制造方法。在一个实施例中，通过在STI沟槽中选择性地沉积整个外延堆叠来形成多层堆叠。通道层在缓冲层上伪造生长。覆盖层生长在沟道层的顶部。在一个实施例中，STI层的高度保持高于沟道层直到形成栅极。在每个通道纳米线上形成栅极电介质层。栅电极形成在栅介质层上并且围绕沟道纳米线。

30. 发明申请

WO2016105412A1 APPARATUS AND METHODS OF FORMING FIN STRUCTURES WITH ASYMMETRIC PROFILE 审中-公开
标题翻译：使用不对称轮廓形成精细结构的装置和方法
公开(公告)号：WO2016105412A1
公开(公告)日：2016-06-30
申请号：PCT/US2014/072349
申请日：2014-12-24
申请人： INTEL CORPORATION , RACHMADY, Willy , METZ, Matthew V. , MOHAPATRA, Chandra S. , DEWEY, Gilbert , KAVALIEROS, Jack T. , MURTHY, Anand S. , RAHHAL-ORABI, Nadia M. , GHANI, Tahir , GLASS, Glenn A.
发明人： RACHMADY, Willy , METZ, Matthew V. , MOHAPATRA, Chandra S. , DEWEY, Gilbert , KAVALIEROS, Jack T. , MURTHY, Anand S. , RAHHAL-ORABI, Nadia M. , GHANI, Tahir , GLASS, Glenn A.
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7853 , H01L21/02532 , H01L21/02694 , H01L21/30625 , H01L21/76224 , H01L29/0653 , H01L29/1054 , H01L29/42392 , H01L29/66795 , H01L29/785 , H01L29/78696
摘要： An embodiment includes a microelectronic device comprising: a substrate comprising a raised portion and a non-raised portion, wherein a dielectric material is disposed adjacent the raised portion, an epitaxial sub-fin structure disposed on the raised portion, wherein a bottom portion of the epitaxial sub-fin structure comprises an asymmetric profile, and an epitaxial fin device structure disposed on the sub-fin structure. Other embodiments are described herein.
摘要翻译：一种实施方式包括微电子器件，其包括：衬底，其包括凸起部分和非凸起部分，其中电介质材料邻近所述凸起部分设置，外延子鳍结构设置在所述凸起部分上，其中，外延子鳍结构包括非对称轮廓，以及设置在子鳍结构上的外延翅片装置结构。本文描述了其它实施例。

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