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21. 发明申请

WO2007124472A8 PATTERNING SUB-LITHOGRAPHIC FEATURES WITH VARIABLE WIDTHS 审中-公开
标题翻译：绘制具有可变宽度的次平面特征
公开(公告)号：WO2007124472A8
公开(公告)日：2008-11-13
申请号：PCT/US2007067184
申请日：2007-04-23
申请人： IBM , YANG HAINING S
发明人： YANG HAINING S
IPC分类号： H01L21/311
CPC分类号： H01L21/0337 , H01L21/0334 , H01L21/3086 , H01L21/3088 , H01L21/76229 , H01L21/84 , H01L27/0207 , H01L27/11 , H01L27/1104 , H01L27/1203 , Y10S438/942 , Y10S438/947 , Y10S977/887
摘要： A method of processing a substrate of a device comprises the as following steps. Form a cap layer (14) over the substrate (12). Form a dummy layer (DL) over the cap layer (14), the cap layer having a top surface. Etch the dummy layer (DL) forming patterned dummy elements (DA, DB, DC) of variable widths and exposing sidewalls (3ON, 31N, 32N, 33N) of the dummy elements and portions of the top surface of the cap layer (14) aside from the dummy elements. Deposit a spacer layer (18C) over the device covering the patterned dummy elements (DA, DB, DC) and exposed surfaces of the cap layer (14). Etch back the spacer layer (18C) forming sidewall spacers (30N, 31N, 32N, 33N) aside from the sidewalls of the patterned dummy elements (DA, DB, DC) spaced above a minimum spacing and forming super-wide spacers between sidewalls of the patterned dummy elements spaced less than the minimum spacing. Strip the patterned dummy elements. Expose portions of the substrate aside from the sidewall spacers (30N, 31N, 32N, 33N). Pattern exposed portions of the substrate (12) by etching into the substrate.
摘要翻译：处理装置的基板的方法包括以下步骤。在衬底（12）上形成覆盖层（14）。在盖层（14）上形成虚拟层（DL），盖层具有顶表面。蚀刻形成可变宽度的图案化虚拟元件（DA，DB，DC）的虚拟层（DL），并且暴露虚拟元件的侧壁（3ON，31N，32N，33N）和盖层（14）的顶表面的部分，除了虚拟元素。在覆盖图案化的虚设元件（DA，DB，DC）的设备和覆盖层（14）的暴露表面上的元件上沉积间隔层（18C）。将间隔层（18C）刻蚀到形成侧壁间隔物（30N，31N，32N，33N）之外，其间距图案化的虚设元件（DA，DB，DC）的侧壁间隔开最小间隔，并形成超宽间隔物图案化的虚拟元件间隔小于最小间距。剥去图案的虚拟元素。将侧衬垫（30N，31N，32N，33N）的一部分露出。通过蚀刻到衬底中衬底（12）的图案曝光部分。

22. 发明申请

WO2008094746A2 SUB-LITHOGRAPHIC INTERCONNECT PATTERNING USING SELF-ASSEMBLING POLYMERS 审中-公开
标题翻译：亚光刻互连图案使用自组装聚合物
公开(公告)号：WO2008094746A2
公开(公告)日：2008-08-07
申请号：PCT/US2008/050973
申请日：2008-01-14
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , LI, Wai-Kin , YANG, Haining, S.
发明人： LI, Wai-Kin , YANG, Haining, S.
CPC分类号： H01L21/31144 , H01L21/0337 , H01L21/0338 , H01L21/76816 , Y10S438/947 , Y10S977/888 , Y10S977/895 , Y10S977/90
摘要： The present invention is directed to the formation of sublithographic features in a semi conduct or structure using self-assembling polymers The self-assembling polymers are formed in openings in a hard mask, annealed and then etched, followed by etching of the underlying dielectric material. At least one subiithograpliic feature is formed according to this method. Abo disclosed is an intermediate semiconductor structure in which at least one interconnect wiring feature has a dimension that is defined by a self-assembled block copolymer.
摘要翻译：本发明涉及使用自组装聚合物在半导体或结构中形成亚光刻特征自组装聚合物在硬掩模中的开口中形成，退火然后蚀刻，随后通过蚀刻下面的介电材料。至少有一个subiithograpliic功能根据此方法形成。 Abo公开了一种中间半导体结构，其中至少一个互连布线特征具有由自组装嵌段共聚物限定的尺寸。

23. 发明申请

WO2007127769A3 HIGH PERFORMANCE 3D FET STRUCTURES, AND METHODS FOR FORMING THE SAME USING PREFERENTIAL CRYSTALLOGRAPHIC ETCHING 审中-公开
公开(公告)号：WO2007127769A3
公开(公告)日：2007-11-08
申请号：PCT/US2007/067360
申请日：2007-04-25
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , DYER, Thomas, W. , YANG, Haining, S.
发明人： DYER, Thomas, W. , YANG, Haining, S.
IPC分类号： H01L27/12 , H01L27/01 , H01L29/00 , H01L29/04 , H01L31/036
摘要： The present invention relates to high performance three-dimensional (3D) field effect transistors (FETs). Specifically, a 3D semiconductor structure having a bottom surface (20A) oriented along one of a first set of equivalent crystal planes { 100} and multip additional surfaces (20B) oriented along a second, different set of equivalent crystal planes can be used to form a high performance 3 FET with carrier channels oriented along the second, different set of equivalent crystal planes. More importantly, such a 3D semiconductor structure can be readily formed over the same substrate (12) with an additional 3D semiconductor structure having a bottom surface and multiple additional surfaces all oriented along the first set of equivalent crystal planes. The additional 3D semiconductor structure can be used to form an additional 3D FET, which is complementary to the above-described 3D FET and has carrier channels oriented along the first set of equivalent crystal planes.

24. 发明申请

WO2007127769A2 HIGH PERFORMANCE 3D FET STRUCTURES, AND METHODS FOR FORMING THE SAME USING PREFERENTIAL CRYSTALLOGRAPHIC ETCHING 审中-公开
标题翻译：高性能3D FET结构及其使用优选结晶蚀刻形成其的方法
公开(公告)号：WO2007127769A2
公开(公告)日：2007-11-08
申请号：PCT/US2007067360
申请日：2007-04-25
申请人： IBM , DYER THOMAS W , YANG HAINING S
发明人： DYER THOMAS W , YANG HAINING S
IPC分类号： H01L21/8232 , H01L29/76
CPC分类号： H01L21/823807 , H01L21/823821 , H01L27/0922 , H01L27/1211 , H01L29/04 , H01L29/66795 , H01L29/7853
摘要： The present invention relates to high performance three-dimensional (3D) field effect transistors (FETs). Specifically, a 3D semiconductor structure having a bottom surface oriented along one of a first set of equivalent crystal planes and multiple additional surfaces oriented along a second, different set of equivalent crystal planes can be used to form a high performance 3D FET with carrier channels oriented along the second, different set of equivalent crystal planes. More importantly, such a 3D semiconductor structure can be readily formed over the same substrate with an additional 3D semiconductor structure having a bottom surface and multiple additional surfaces all oriented along the first set of equivalent crystal planes. The additional 3D semiconductor structure can be used to form an additional 3D FET, which is complementary to the above-described 3D FET and has carrier channels oriented along the first set of equivalent crystal planes.
摘要翻译：本发明涉及高性能三维（3D）场效应晶体管（FET）。具体而言，可以使用具有沿着第一组等效晶面中的一个取向的底表面和沿着第二不同组的等效晶面取向的多个附加表面的3D半导体结构，以形成具有载体通道定向的高性能3D FET 沿着第二个不同组的等效晶面。更重要的是，这种3D半导体结构可以容易地在具有底表面和多个附加表面的附加3D半导体结构的同一衬底上形成，所述另外的三维半导体结构全部沿着第一组等效晶面取向。附加的3D半导体结构可以用于形成附加的3D FET，其与上述3D FET互补，并且具有沿着第一组等效晶面取向的载流子通道。

25. 发明申请

WO2005017964A3 STRUCTURE AND METHOD OF MAKING STRAINED SEMICONDUCTOR CMOS TRANSISTORS HAVING LATTICE-MISMATCHED SOURCE AND DRAIN REGIONS 审中-公开
公开(公告)号：WO2005017964A3
公开(公告)日：2005-02-24
申请号：PCT/US2004/025152
申请日：2004-08-04
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , CHEN, Huajie , CHIDAMBARRAO, Dureseti , GLUSCHENKOV, Oleg, G. , STEEGEN, An, L. , YANG, Haining, S.
发明人： CHEN, Huajie , CHIDAMBARRAO, Dureseti , GLUSCHENKOV, Oleg, G. , STEEGEN, An, L. , YANG, Haining, S.
IPC分类号： H01L31/0328
摘要： A p-type field effect transistor (PFET) (10) and an n-type field effect transistor (NFET) (12) of an integrated circuit are provided. A first strain is applied to the channel region (20) of the PFET (10) but not the NFET (12) via a lattice-mismatched semiconductor layer such as silicon germanium disposed in source and drain regions (111) of only the PFET (10) and not of the NFET.(12) A process of making the PFET (10) and NFET (12) is provided. Trenches are etched in the areas to become the source and drain regions (111) of the PFET and a lattice-mismatched silicon germanium layer (121) is grown epitaxially therein to apply a strain to the channel region of the PFET adjacent thereto. A layer of silicon (14) can be grown over the silicon germanium layer (121) and a salicide (68) formed from the layer of silicon to provide low-resistance source and drain regions (111).

26. 发明申请

WO2005017964A2 STRUCTURE AND METHOD OF MAKING STRAINED SEMICONDUCTOR CMOS TRANSISTORS HAVING LATTICE-MISMATCHED SOURCE AND DRAIN REGIONS 审中-公开
标题翻译：制造具有不匹配的源和漏区的应变半导体CMOS晶体管的结构和方法
公开(公告)号：WO2005017964A2
公开(公告)日：2005-02-24
申请号：PCT/US2004025152
申请日：2004-08-04
申请人： IBM , CHEN HUAJIE , CHIDAMBARRAO DURESETI , GLUSCHENKOV OLEG G , STEEGEN AN L , YANG HAINING S
发明人： CHEN HUAJIE , CHIDAMBARRAO DURESETI , GLUSCHENKOV OLEG G , STEEGEN AN L , YANG HAINING S
IPC分类号： H01L21/20 , H01L21/336 , H01L21/8238 , H01L21/84 , H01L27/092 , H01L27/12 , H01L
CPC分类号： H01L21/84 , H01L21/02532 , H01L21/02636 , H01L21/823807 , H01L21/823814 , H01L27/0922 , H01L27/1203 , H01L29/165 , H01L29/6656 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： A p-type field effect transistor (PFET) and an n-type field effect transistor (NFET) of an integrated circuit are provided. A first strain is applied to the channel region of the PFET but not the NFET via a lattice-mismatched semiconductor layer such as silicon germanium disposed in source and drain regions of only the PFET and not of the NFET. A process of making the PFET and NFET is provided. Trenches are etched in the areas to become the source and drain regions of the PFET and a lattice-mismatched silicon germanium layer is grown epitaxially therein to apply a strain to the channel region of the PFET adjacent thereto. A layer of silicon can be grown over the silicon germanium layer and a salicide formed from the layer of silicon to provide low-resistance source and drain regions.
摘要翻译：提供集成电路的p型场效应晶体管（PFET）和n型场效应晶体管（NFET）。第一应变施加到PFET的沟道区，而不是NFET通过位于仅仅PFET而不是NFET的源极和漏极区域中的晶格不匹配的半导体层，例如硅锗。提供制造PFET和NFET的工艺。在区域中蚀刻沟槽以成为PFET的源极和漏极区域，并且将晶格失配的硅锗层外延生长以向与其相邻的PFET的沟道区域施加应变。可以在硅锗层上生长一层硅层，并从硅层形成硅化物以提供低电阻源极和漏极区域。

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