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    • 11. 发明申请
    • CLASS-D AMPLIFIER CIRCUITS
    • CLASS-D放大器电路
    • WO2015059471A1
    • 2015-04-30
    • PCT/GB2014/053150
    • 2014-10-22
    • WOLFSON MICROELECTRONICS LTD
    • LESSO, John PaulIDO, Toru
    • H03F3/217
    • H03F3/2171H03F1/0211H03F3/187H03F3/217H03F2200/165H03F2200/171H03F2200/333H03F2200/351H03G1/0088
    • This application describes methods and apparatus for Class-D amplifier circuits (300) with improved power efficiency. The circuit has an output stage (102) with at least first and second switches and a modulator (104) that receives an input signal to be amplified, S IN , and a first clock signal f SW . The modulator controls the duty cycles of the first and second switches, within a switching cycle based on the input signal, wherein the switching cycle has a switching frequency based on the first clock signal. A frequency controller (301) controls the frequency of the first clock signal in response to an indication of the amplitude of the input signal so as to provide a first switching frequency at a first input signal amplitude and a second, lower, switching frequency at a second, lower, input signal amplitude. A lower switching frequency can be tolerated at low signal amplitudes and varying the switching frequency in this way thus maintains stability whilst reducing switching power losses.
    • 本申请描述了具有改善的功率效率的D类放大器电路(300)的方法和装置。 电路具有至少具有第一和第二开关的输出级(102)和接收待放大的输入信号SIN和第一时钟信号fSW的调制器(104)。 调制器基于输入信号在开关周期内控制第一和第二开关的占空比,其中开关周期具有基于第一时钟信号的开关频率。 频率控制器(301)响应于输入信号的幅度的指示来控制第一时钟信号的频率,以便在第一输入信号幅度和第二输入信号的第二开关频率 第二,较低的输入信号幅度。 在低信号幅度下可以容忍较低的开关频率,并且以这种方式改变开关频率,从而在降低开关功率损耗的同时保持稳定性。