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11. 发明申请

WO2019066961A1 MULTI-LAYER CRYSTALLINE BACK GATED THIN FILM TRANSISTOR 审中-公开
公开(公告)号：WO2019066961A1
公开(公告)日：2019-04-04
申请号：PCT/US2017/054589
申请日：2017-09-29
申请人： INTEL CORPORATION
发明人： LE, Van H. , SHARMA, Abhishek A. , DEWEY, Gilbert , MILLARD, Kent , KAVALIEROS, Jack , SHIVARAMAN, Shriram , TRONIC, Tristan A. , GARDNER, Sanaz , WEBER, Justin R. , GHANI, Tahir , TAN, Li Huey , LIN, Kevin
IPC分类号： H01L27/108
摘要： Described is an apparatus which comprises: a gate comprising a metal; a first layer adjacent to the gate, the first layer comprising a dielectric material; a second layer adjacent to the first layer, the second layer comprising a second material; a third layer adjacent to the second layer, the third layer comprising a third material including an amorphous metal oxide; a fourth layer adjacent to the third layer, the fourth layer comprising a fourth material, wherein the fourth and second materials are different than the third material; a source partially adjacent to the fourth layer; and a drain partially adjacent to the fourth layer.

12. 发明申请

WO2018125165A1 RESONATOR STRUCTURE ENCAPSULATION 审中-公开
公开(公告)号：WO2018125165A1
公开(公告)日：2018-07-05
申请号：PCT/US2016/069315
申请日：2016-12-29
申请人： INTEL CORPORATION , LIN, Kevin , JUN, Kimin , MOHAMMED, Edris
发明人： LIN, Kevin , JUN, Kimin , MOHAMMED, Edris
IPC分类号： H03H9/25 , H03H9/145 , H03H9/205 , H03H3/02
摘要： The RF filters used in conventional mobile devices often include resonator structures, which often require free-standing air-gap structure to prevent mechanical vibrations of the resonator from being damped by a bulk material. A method for fabricating a resonator structure comprises depositing a non-conformal thin-film to the resonator structure to seal air gap cavities in the resonator structure.

13. 发明申请

WO2018125109A1 SUBTRACTIVE PLUG ETCHING 审中-公开
公开(公告)号：WO2018125109A1
公开(公告)日：2018-07-05
申请号：PCT/US2016/069083
申请日：2016-12-29
申请人： INTEL CORPORATION
发明人： LIN, Kevin , BRISTOL, Robert L. , CHANDHOK, Manish
IPC分类号： H01L21/768
CPC分类号： H01L21/76885 , H01L21/76801 , H01L21/76834 , H01L21/76883 , H01L21/76897
摘要： In an example, there is disclosed a method of manufacturing an integrated circuit, including: depositing a metal interconnect layer on an interlayer dielectric (ILD) including an ILD material, including a first interconnect and a second interconnect; depositing a first cross grating having a first dielectric material; depositing a second cross grating having a second dielectric material, the second cross grating substantially perpendicular to the first cross grating; subtractively etching a plug pattern between the first interconnect and the second interconnect; filling the plug pattern with a plug dielectric material; and depositing a via to electrically couple the second interconnect to a different layer.

14. 发明申请

WO2018063272A1 GRAPHENE NANORIBBON INTERCONNECTS AND INTERCONNECT LINERS 审中-公开
标题翻译：石墨烯纳米带互连和互连衬底
公开(公告)号：WO2018063272A1
公开(公告)日：2018-04-05
申请号：PCT/US2016/054627
申请日：2016-09-30
申请人： INTEL CORPORATION
发明人： LIN, Kevin , CAUDILLO, Roman , BOJARSKI, Stephanie A. , MAESTRE CARO, Aranzazu , TORRES, Jessica M. , CHAWLA, Jasmeet S.
IPC分类号： H01L21/768 , H01L29/16
CPC分类号： H01L23/53276 , H01L21/768 , H01L29/16
摘要： Graphitic barrier layers for metal interconnects are described. The graphitic barrier layers are substantially conformal to a metal feature portion of an interconnect and have thicknesses in a range from 0.3 nanometers (nm) to 2 nm. This thickness is much less than the thickness of conventional diffusion barriers (e.g., tantalum nitride) which are in a range of from 5 nm to 10 nm. The thinner graphitic barrier layer improves the conductivity of the metal interconnect because proportionately more conductive metal can be deposited in the interconnect compared to conventionally (e.g., tantalum-based) lined interconnects. Furthermore, unlike conventional barriers layers which are poor electrical conductors, graphitic is conductive. This also improves the electrical conductivity of the interconnect as a whole.
摘要翻译：描述了用于金属互连的石墨阻挡层。石墨阻挡层基本上与互连的金属特征部分共形并具有0.3纳米（nm）至2nm范围内的厚度。该厚度远小于常规扩散阻挡层（例如氮化钽）的厚度，其范围为5nm至10nm。较薄的石墨阻挡层改善了金属互连的导电性，因为与常规（例如，基于钽的）内衬互连相比，可以在互连中沉积更多的导电金属。而且，不同于导电性差的传统阻挡层，石墨是导电的。这也提高了整个互连的导电性。

15. 发明申请

WO2017204820A1 DAMASCENE PLUG AND TAB PATTERNING WITH PHOTOBUCKETS FOR BACK END OF LINE (BEOL) SPACER-BASED INTERCONNECTS 审中-公开
标题翻译： DAMASCENE插头和电脑插头用于线后端（BEOL）基于间隔器的互连
公开(公告)号：WO2017204820A1
公开(公告)日：2017-11-30
申请号：PCT/US2016/034617
申请日：2016-05-27
申请人： INTEL CORPORATION
发明人： LIN, Kevin , BRISTOL, Robert L. , SCHENKER, Richard E.
IPC分类号： H01L21/768 , H01L21/02
CPC分类号： H01L21/76816 , H01L21/0334 , H01L21/7682 , H01L21/76877 , H01L23/528
摘要： Damascene plug and tab patterning with photobuckets for back end of line (BEOL) spacer-based interconnects is described. In an example, a back end of line (BEOL) metallization layer for a semiconductor structure includes an inter-layer dielectric (ILD) layer disposed above a substrate. A plurality of conductive lines is disposed in the ILD layer along a first direction. A conductive tab is disposed in the ILD layer. The conductive tab couples two of the plurality of conductive lines along a second direction orthogonal to the first direction.
摘要翻译：描述了用于后端行线（BEOL）间隔件互连的带有光桶的镶嵌插头和标签图案化。在一个实例中，用于半导体结构的线后端（BEOL）金属化层包括设置在衬底上方的层间电介质（ILD）层。多个导线沿着第一方向设置在ILD层中。导电接头布置在ILD层中。导电接线片沿垂直于第一方向的第二方向连接多条导线中的两条导线。

16. 发明申请

WO2017111847A1 TECHNIQUES FOR FORMING ELECTRICALLY CONDUCTIVE FEATURES WITH IMPROVED ALIGNMENT AND CAPACITANCE REDUCTION 审中-公开
标题翻译：形成具有改善的对准和电容降低的导电特性的技术
公开(公告)号：WO2017111847A1
公开(公告)日：2017-06-29
申请号：PCT/US2015/000413
申请日：2015-12-24
申请人： INTEL CORPORATION
发明人： LIN, Kevin , SCHENKER, Richard, E. , CHANDHOK, Manish , BIELEFELD, Jeffery
IPC分类号： H01L21/768
CPC分类号： H01L21/76834 , H01L21/76816 , H01L21/76832 , H01L21/76885 , H01L21/76897 , H01L23/53295
摘要： Techniques are disclosed for forming electrically conductive features with improved alignment and capacitance reduction. In accordance with some embodiments, individual conductive features may be formed over a semiconductor substrate by a damascene process. For a given feature, first and second barrier layers (conformal or otherwise) may be disposed along sidewalls thereof, and a helmet-like hardmask body may be disposed over a top surface thereof. Additional conductive features can be formed between existing features, using the barrier layers as alignment spacers, thereby halving (or otherwise reducing) feature pitch. A layer of another hardmask material may be disposed over the additionally formed features. That layer and the helmet-like hardmask bodies may be of different material composition, providing for etch selectivity with respect to one another. Additional layer(s) can be formed over the resultant topography, exploiting the hardmask etch selectivity in forming interconnects for adjacent integrated circuit layers.
摘要翻译：公开了用于形成具有改进的对准和电容减小的导电特征的技术。根据一些实施例，可以通过镶嵌工艺在半导体衬底上形成各个导电特征。对于给定的特征，第一和第二阻挡层（保形或其他）可以沿其侧壁布置，并且头盔状硬掩模主体可以布置在其顶表面上方。可以在现有特征之间形成额外的导电特征，使用阻挡层作为对准间隔件，由此使特征间距减半（或以其他方式减小）。一层另一种硬掩模材料可以设置在附加形成的特征上。该层和头盔状硬掩模主体可以具有不同的材料组成，从而相对于彼此提供蚀刻选择性。附加层可以形成在合成地形上，利用硬掩模蚀刻选择性形成用于相邻集成电路层的互连。

17. 发明申请

WO2017052559A1 METHODS, APPARATUSES AND SYSTEMS FOR INTEGRATED CIRCUIT STRUCTURES WITH A REPLACEMENT INTER-LAYER DIELECTRIC (ILD) 审中-公开
标题翻译：具有替代层间电介质（ILD）的集成电路结构的方法，装置和系统
公开(公告)号：WO2017052559A1
公开(公告)日：2017-03-30
申请号：PCT/US2015/052003
申请日：2015-09-24
申请人： INTEL CORPORATION
发明人： SINGH, Kanwaljit , LIN, Kevin , CHAWLA, Jasmeet, S. , SCHENKER, Richard
IPC分类号： H01L21/31
CPC分类号： H01L21/76816 , H01L21/0337 , H01L21/31144 , H01L21/76807 , H01L21/76834 , H01L21/76885 , H01L21/76897
摘要： Embodiments of the present disclosure describe techniques and configurations associated with an integrated circuit (IC) structure with a replacement inter-layer dielectric (ILD) layer disposed on a first ILD layer. A sacrificial layer may be formed on the first ILD layer. Trenches may be patterned and formed in the sacrificial layer such that the trenches are disposed on the first ILD layer. Vias may be patterned and formed in the first ILD layer below the trenches. After formation of the trenches, the sacrificial layer may be removed, and the replacement ILD layer (e.g., a second ILD layer) may be formed on the first ILD layer between the trenches. Other embodiments may be described and/or claimed.
摘要翻译：本公开的实施例描述了与集成电路（IC）结构相关联的技术和配置，其中置换在第一ILD层上的置换层间电介质（ILD）层。可以在第一ILD层上形成牺牲层。沟槽可以被图案化并形成在牺牲层中，使得沟槽设置在第一ILD层上。可以在沟槽下方的第一ILD层中图案化并形成通孔。在形成沟槽之后，可以去除牺牲层，并且可以在沟槽之间的第一ILD层上形成置换的ILD层（例如，第二ILD层）。可以描述和/或要求保护其他实施例。

18. 发明申请

WO2015026333A1 A DISPLAY APPARATUS INCLUDING MEMS DEVICES 审中-公开
标题翻译：包括MEMS器件的显示设备
公开(公告)号：WO2015026333A1
公开(公告)日：2015-02-26
申请号：PCT/US2013/055843
申请日：2013-08-20
申请人： INTEL CORPORATION , LIN, Kevin , ANDRYSCO, Nathan R.
发明人： LIN, Kevin , ANDRYSCO, Nathan R.
IPC分类号： G02B5/08 , G02B26/08
CPC分类号： G02F1/19 , G02B26/0841
摘要： Embodiments of the present disclosure provide techniques and configurations for a display apparatus. In one embodiment, the apparatus may include one or more micro-electro-mechanical system (MEMS) devices. The MEMS device may include a first electrode including a partially reflective surface, a second electrode including a partially or completely reflective surface and disposed substantially parallel to the first electrode, and an analog actuation arrangement coupled to the first electrode, the second electrode or both the first and second electrodes to cause movement of the first electrode from a start position to a selected position of a plurality of end positions, responsive to a selected application of an actuation voltage, to cause the MEMS device to selectively output a reflection of a light in a selected wavelength, or no reflection of the light. Other embodiments may be described and/or claimed.
摘要翻译：本公开的实施例提供了用于显示装置的技术和配置。在一个实施例中，该装置可以包括一个或多个微机电系统（MEMS）装置。 MEMS器件可以包括包括部分反射表面的第一电极，包括部分或完全反射表面并且基本上平行于第一电极设置的第二电极，以及耦合到第一电极，第二电极或两者的模拟致动装置第一和第二电极，以响应于所选择的致动电压的应用，使第一电极从起始位置移动到多个端部位置的选定位置，以使MEMS器件选择性地输出光的反射选择的波长，或没有光的反射。可以描述和/或要求保护其他实施例。

19. 发明申请

WO2019132879A1 COMPENSATION OF RESISTANCE IN THIN FILM RESISTOR 审中-公开
公开(公告)号：WO2019132879A1
公开(公告)日：2019-07-04
申请号：PCT/US2017/068540
申请日：2017-12-27
申请人： INTEL CORPORATION
发明人： MCKUBRE, Nicholas J. , LIN, Kevin
IPC分类号： H01L21/768 , H01L21/3205 , H01L49/02
摘要： An apparatus is provided which includes: a first line and a second line, the first line and the second line separated by a space therebetween. In an example, a dielectric material and a third line is in the space between the first and second lines. A top surface of the third line may be coplanar with top surfaces of the first and second lines. The apparatus may further include a substrate. The first and second lines may be on the substrate, and the third line may be over a thickness of the dielectric material on the substrate. An interconnect structure may be over the dielectric material, where the interconnect structure may be in contact with a first of the first, second or third lines, and in contact with a second of the first, second, or third lines.

20. 发明申请

WO2018236354A1 METAL SPACER-BASED APPROACHES FOR CONDUCTIVE INTERCONNECT AND VIA FABRICATION AND STRUCTURES RESULTING THEREFROM 审中-公开
公开(公告)号：WO2018236354A1
公开(公告)日：2018-12-27
申请号：PCT/US2017/038379
申请日：2017-06-20
申请人： INTEL CORPORATION , LIN, Kevin , SCHENKER, Richard E. , BRISTOL, Robert L. , KABIR, Nafees A. , VREELAND, Richard F.
发明人： LIN, Kevin , SCHENKER, Richard E. , BRISTOL, Robert L. , KABIR, Nafees A. , VREELAND, Richard F.
IPC分类号： H01L21/768
摘要： Metal spacer-based approaches for conductive interconnect and via fabrication is described. In an example, an integrated circuit structure includes a plurality of alternating first and second conductive lines along a same direction of a back end of line (BEOL) metallization layer in an inter-layer dielectric (ILD) structure above a substrate. Each of the plurality of alternating first and second conductive lines is recessed relative to an uppermost surface of the ILD structure. The ILD structure includes a plurality of first and second ILD lines alternating with the alternating first and second conductive lines. A first hardmask component is on and aligned with the first conductive lines. A second hardmask component is on an aligned with the second conductive lines. A conductive via is in an opening in the first hardmask component and on one of the first conductive lines.

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