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11. 发明申请

WO2008070250A2 SOFTWARE IMPLEMENTATION OF MATRIX INVERSION IN A WIRELESS COMMUNICATION SYSTEM 审中-公开
标题翻译：无线通信系统中矩阵反演的软件实现
公开(公告)号：WO2008070250A2
公开(公告)日：2008-06-12
申请号：PCT/US2007/079305
申请日：2007-09-24
申请人： SANDBRIDGE TECHNOLOGIES INC. , SIMA, Mihai , IANCU, Daniel , YE, Hua , MOUDGILL, Mayan
发明人： SIMA, Mihai , IANCU, Daniel , YE, Hua , MOUDGILL, Mayan
IPC分类号： H04Q7/20
CPC分类号： G06F17/16 , G06F9/30014 , G06F9/30036 , G06F9/30101 , G06F9/3851 , G06F9/3867 , G06F9/3885 , G06F9/3895
摘要： A digital signal processor is provided in a wireless communication device, wherein the processor comprises a vector unit, first and second registers coupled to and accessible by the vector unit; and an instruction set configured to perform matrix inversion of a matrix of channel values by coordinate rotation digital computer instructions using the vector unit and the first and second registers.
摘要翻译：在无线通信设备中提供数字信号处理器，其中所述处理器包括向量单元，耦合到所述向量单元并由所述向量单元访问的第一和第二寄存器; 以及指令集，其被配置为通过使用向量单元和第一和第二寄存器的坐标旋转数字计算机指令来执行信道值矩阵的矩阵求逆。

12. 发明申请

WO2006020729A2 METHOD FOR RECOGNITION OF ACYCLIC INSTRUCTION PATTERNS 审中-公开
标题翻译：用于识别ACYCLIC指令模式的方法
公开(公告)号：WO2006020729A2
公开(公告)日：2006-02-23
申请号：PCT/US2005/028463
申请日：2005-08-11
申请人： SANDBRIDGE TECHNOLOGIES, INC. , MOUDGILL, Mayan , KOTLYAR, Vladimir
发明人： MOUDGILL, Mayan , KOTLYAR, Vladimir
IPC分类号： G06F9/44
CPC分类号： G06F8/443
摘要： A method which determines by an optimizing compiler whether any variable in the given program equals to the given acyclic mathematical function f(x,y,...) applied to the given variables x, y, ... in the program. In one embodiment, the method includes expressing the bits of the value of the function f(x,y,..) as a Boolean function of the bits of the inputs x, y, ...; expressing, for every variable v and program statement s, the value taken by v when s is executed as a Boolean function V(s,v)(x, y, ...) of the bits of x, y, ...; and expressing, for every statement s, the condition under which the statement is executed as a Boolean function C(s)(x, y, ...) of the bits of the inputs x, y, .... Finally, a determination is made using a Boolean satisfiability oracle of whether, for the given variable v and program statement s, the following Boolean expression holds: C(s)(x,y,...) P> V(s,v)(x,y...)=f(x,y,...). In a second embodiment, the method includes expressing the value of f(x,y,...) as a plurality of functions f j (x,y,..) having the corresponding predicate P j (x,y,..); expressing, for every variable v and program statement s, the value taken by v when s is executed as a plurality of functions V j (s,v)(x,y,...), one for each predicate P j (x,y,..); and expressing, for every statement s, the condition under which the statement is executed as a plurality of functions C j (s)(x,y,...), one for each predicate P j (x,y,..). Finally, a determination is of whether for the given variable v and program statement s, V j (s,v)(x,y,...)=f j (x,y,..) whenever the predicate P j (x,y,..) and the condition C j (s)(x,y,...) are true.
摘要翻译：一种通过优化编译器确定给定程序中的任何变量是否等于给定的非循环数学函数f（x，y，...）的方法，该函数应用于程序中的给定变量x，y，...。在一个实施例中，该方法包括将函数f（x，y，...）的值的位表示为输入x，y，...的位的布尔函数; 表示对于每个变量v和程序语句s，当s作为x，y，...的位的布尔函数V（s，v）（x，y，...）执行时，由v取得的值 ; 并且对于每个陈述s，表达作为输入x，y，...的位的布尔函数C（s，x，y，...）执行语句的条件。最后，a 对于给定的变量v和程序语句s，以下布尔表达式是否成立：C（s）（x，y，...）P> V（s，v）（x ，Y ...）= F（X，Y，...）。在第二实施例中，该方法包括将f（x，y，...）的值表示为具有相应谓词P'的多个函数f（x，y，...） SUB>Ĵ（X，Y，...）; 表示对于每个变量v和程序语句s，当s被执行为多个函数V S（s，v）（x，y，...）时，由v采取的值对于每个谓词P＆lt; j＆gt;（x，y，...）; 并且对于每个陈述s，表示执行该语句作为多个函数C（x，y，...）的条件，对于每个谓词P _{Ĵ（X，Y，...）。最后，确定对于给定变量v和程序语句s，V j（s，v）（x，y，...）= f j j （x，y，...）和（x，y，...）（x，y，...）（x，y，...）。）是真的。}

13. 发明申请

WO2005099383A2 PROCESSOR HAVING COMPOUND INSTRUCTION AND OPERATION FORMATS 审中-公开
标题翻译：具有化合物指导和操作格式的处理器
公开(公告)号：WO2005099383A2
公开(公告)日：2005-10-27
申请号：PCT/US2005/011613
申请日：2005-04-07
申请人： SANDBRIDGE TECHNOLOGIES, INC. , GLOSSNER, C. John , HOKENEK, Erdem , MOUDGILL, Mayan , SCHULTE, Michael, J.
发明人： GLOSSNER, C. John , HOKENEK, Erdem , MOUDGILL, Mayan , SCHULTE, Michael, J.
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30145 , G06F9/30036 , G06F9/30167 , G06F9/3853
摘要： A processor comprises a memory, an instruction decoder coupled to the memory for decoding instructions retrieved therefrom, and a plurality of execution units for executing the decoded instructions. One or more of the instructions are in a compound instruction format in which a single instruction comprises multiple operation fields, with one or more of the operation fields each comprising at least an operation code field and a function field. The operation code field and the function field together specify a particular operation to be performed by one or more of the execution units.
摘要翻译：处理器包括存储器，耦合到存储器的用于解码从其中检索的指令的指令解码器，以及用于执行解码指令的多个执行单元。一个或多个指令是复合指令格式，其中单个指令包括多个操作字段，其中一个或多个操作字段各自至少包括操作码字段和功能字段。操作代码字段和功能字段一起指定由一个或多个执行单元执行的特定操作。

14. 发明申请

WO2005069775A2 A METHOD OF REED-SOLOMON ENCODING AND DECODING 审中-公开
标题翻译：一种解决方案编码和解码
公开(公告)号：WO2005069775A2
公开(公告)日：2005-08-04
申请号：PCT/US2004/041011
申请日：2004-12-08
申请人： SANDBRIDGE TECHNOLOGIES, INC. , IANCU, Daniel , MOUDGILL, Mayan , GLOSSNER, John
发明人： IANCU, Daniel , MOUDGILL, Mayan , GLOSSNER, John
IPC分类号： H03M13/15
CPC分类号： H03M13/159 , H03M13/1515
摘要： A Reed-Solomon encoder method includes appending N zeros to a data block and performing a successive Homer reduction of the polynomial P(x) whose coefficients are the data of the data block plus the zeros. The remainders β (i) are multiplied by corresponding polynomial coefficients D (i) (x) and sum of all the resulting products. The sum of the products is appended to the data block as parity symbols to form a codeword. A ReedSolomon decoder method includes calculating syndromes as the dot product of the codeword with syndrome vectors. If the syndromes equal 0, decode the codeword by merely removing the parity symbols. If the syndromes do not equal 0, correct the codeword by forming and solving an error locator polynomial for error locations, forming and solving an error magnitude polynomial for error magnitudes at the locations and correcting the error in the codeword. The codeword is decoded by removing the parity symbols. The methods are performed in software.
摘要翻译： Reed-Solomon编码器方法包括将N个零附加到数据块并且执行其系数是数据块的数据加上零的多项式P（x）的连续荷马缩小。剩余的β<（i）>乘以相应的多项式系数D（i）>（x）和所得到的所有乘积的总和。将产品的总和作为奇偶校验符号附加到数据块以形成码字。 ReedSolomon解码器方法包括计算综合征作为码字与积分矢量的点积。如果综合征等于0，则通过仅删除奇偶校验符号对码字进行解码。如果综合征不等于0，则通过形成和求解错误位置的误差定位多项式来纠正码字，形成和求解用于位置处的误差幅度的误差幅度多项式并校正码字中的误差。通过去除奇偶校验符号对码字进行解码。这些方法是用软件执行的。

15. 发明申请

WO2010017263A1 HALTABLE AND RESTARTABLE DMA ENGINE 审中-公开
标题翻译：易燃和可重启的DMA发动机
公开(公告)号：WO2010017263A1
公开(公告)日：2010-02-11
申请号：PCT/US2009/052794
申请日：2009-08-05
申请人： SANDBRIDGE TECHNOLOGIES, INC. , MOUDGILL, Mayan , WANG, Shenghong
发明人： MOUDGILL, Mayan , WANG, Shenghong
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： A method is described for operation of a DMA engine. Copying is initiated for transfer of a first number of bytes from first source memory locations to first destination memory locations. Then, a halt instruction is issued before the first number of bytes are copied. After copying is stopped, a second number of bytes is established, encompassing those bytes remaining to be copied. After the transfer is halted, a quantity of the second number of bytes is identified. Quantity information is then generated and stored. Second source memory locations are identified to indicate where the second number of bytes are stored. Second source memory location information is then generated and stored. Second destination memory locations are then identified to indicate where the second number of bytes are to be transferred. Second destination memory location information is then generated and stored.
摘要翻译：描述了用于DMA引擎的操作的方法。启动复制以将第一数量的字节从第一源存储器位置传送到第一目的地存储器位置。然后，在第一个字节数被复制之前发出停止指令。复制停止后，建立第二个字节数，包含剩下的要复制的字节。传输停止后，识别出第二个字节数量。然后生成和存储数量信息。识别第二源存储器位置以指示第二数量的字节存储在哪里。然后生成并存储第二源存储器位置信息。然后识别第二目的地存储器位置以指示要传送第二数量字节的位置。然后生成并存储第二目的地存储器位置信息。

16. 发明申请

WO2009067283A3 METHOD FOR IMPLEMENTING PERIODIC BEHAVIORS USING A SINGLE REFERENCE 审中-公开
公开(公告)号：WO2009067283A3
公开(公告)日：2009-05-28
申请号：PCT/US2008/074646
申请日：2008-08-28
申请人： SANDBRIDGE TECHNOLOGIES, INC. , MOUDGILL, Mayan
发明人： MOUDGILL, Mayan
IPC分类号： G06F9/48
摘要： A method for processing information is described. The method includes providing a phase reference, Φ i , where the phase reference comprises N distinct values, expressed as Φ i , = Φ 0 ...Φ N-1 . A reset signal is received. The phase reference, Φ 0 , is initialized in response to receipt of the reset signal. The phase reference values are repeatedly advanced from Φ 0 through Φ N-1 . The process then includes enabling at least one function at a predetermined phase reference value Φ A , wherein Φ Α ε {Φ 0 ...Φ N-1 } •

17. 发明申请

WO2008060948A2 METHOD AND SYSTEM FOR PARALLELIZATION OF PIPELINED COMPUTATIONS 审中-公开
标题翻译：用于流水线计算的并行化的方法和系统
公开(公告)号：WO2008060948A2
公开(公告)日：2008-05-22
申请号：PCT/US2007/084113
申请日：2007-11-08
申请人： SANDBRIDGE TECHNOLOGIES, INC. , KOTLYAR, Vladimir , MOUDGILL, Mayan , POGUDIN, Yuriy, M.
发明人： KOTLYAR, Vladimir , MOUDGILL, Mayan , POGUDIN, Yuriy, M.
IPC分类号： G06F19/00
CPC分类号： G06F9/5066 , G06F9/3826 , G06F9/3885 , G06F9/5027
摘要： A method of parallelizing a pipeline includes stages operable on a sequence of work items. The method includes allocating an amount of work for each work item, assigning at least one stage to each work item, partitioning the at least one stage into at least one team, partitioning the at least one team into at least one gang, and assigning the at least one team and the at least one gang to at least one processor. Processors, gangs, and teams are juxtaposed near one another to minimize communication losses.
摘要翻译：并行化流水线的方法包括可在一系列工作项目上操作的阶段。该方法包括为每个工作项目分配工作量，为每个工作项目分配至少一个阶段，将至少一个阶段划分成至少一个团队，将至少一个团队划分成至少一个团伙，以及将至少一个团队和至少一个团伙到至少一个处理器。处理器，帮派和团队彼此并置，以尽量减少通信损失。

18. 发明申请

WO2006071385A2 DATA FILE STORING MULTIPLE DATA TYPES WITH CONTROLLED DATA ACCESS 审中-公开
标题翻译：数据文件存储具有受控数据访问的多种数据类型
公开(公告)号：WO2006071385A2
公开(公告)日：2006-07-06
申请号：PCT/US2005/041419
申请日：2005-11-15
申请人： SANDBRIDGE TECHNOLOGIES, INC. , HOKENEK, Erdem , MOUDGILL, Mayan , GLOSSNER, C.,John , SCHULTE, Michael, J.
发明人： HOKENEK, Erdem , MOUDGILL, Mayan , GLOSSNER, C.,John , SCHULTE, Michael, J.
IPC分类号： G06F15/00
CPC分类号： G06F9/30112
摘要： A method and apparatus for efficiently storing multiple data types in a computer’s register or data file. A single data file can store data with a variety of sizes and number formats, including integers, fractions, and mixed numbers. The register file is partitioned into fields, such that only the relevant portions of the register file are read or written.
摘要翻译：一种用于在计算机的寄存器或数据文件中有效地存储多种数据类型的方法和装置。单个数据文件可以存储具有各种大小和数字格式的数据，包括整数，分数和混合数。寄存器文件被分割成字段，使得仅读取或写入寄存器文件的相关部分。

19. 发明申请

WO2005101221A1 MULTITHREADED PROCESSOR WITH MULTIPLE CONCURRENT PIPELINES PER THREAD 审中-公开
标题翻译：多通道加工器，每个螺纹多个并流管道
公开(公告)号：WO2005101221A1
公开(公告)日：2005-10-27
申请号：PCT/US2005/011614
申请日：2005-04-07
申请人： SANDBRIDGE TECHNOLOGIES, INC. , HOKENEK, Erdem , MOUDGILL, Mayan , SCHULTE, Michael, J. , GLOSSNER, C., John
发明人： HOKENEK, Erdem , MOUDGILL, Mayan , SCHULTE, Michael, J. , GLOSSNER, C., John
IPC分类号： G06F15/00
CPC分类号： G06F9/3851 , G06F9/30036 , G06F9/30101 , G06F9/30123 , G06F9/3893
摘要： A multithreaded processor comprises a plurality of hardware thread units, an instruction decoder coupled to the thread units for decoding instructions received therefrom, and a plurality of execution units for executing the decoded instructions. The multithreaded processor is configured for controlling an instruction issuance sequence for threads associated with respective ones of the hardware thread units. On a given processor clock cycle, only a designated one of the threads is permitted to issue one or more instructions, but the designated thread that is permitted to issue instructions varies over a plurality of clock cycles in accordance with the instruction issuance sequence. The instructions are pipelined in a manner which permits at least a given one of the threads to support multiple concurrent instruction pipelines.
摘要翻译：多线程处理器包括多个硬件线程单元，耦合到用于解码从其接收的指令的线程单元的指令解码器，以及用于执行解码指令的多个执行单元。多线程处理器被配置为用于控制与相应硬件线程单元相关联的线程的指令发布序列。在给定的处理器时钟周期中，仅允许指定的一个线程发出一个或多个指令，但是允许发出指令的指定线程根据指令发布顺序在多个时钟周期内变化。这些指令以允许至少给定的一个线程支持多个并行指令流水线的方式流水线化。

20. 发明申请

WO2003090055A1 POWER CONTROL OF A PROCESSOR USING HARDWARE STRUCTURES CONTROLLED BY A COMPILER WITH AN ACCUMULATED INSTRUCTION PROFILE 审中-公开
标题翻译：使用具有累积指令配置文件的编译器控制的硬件结构的处理器的功率控制
公开(公告)号：WO2003090055A1
公开(公告)日：2003-10-30
申请号：PCT/US2002/012086
申请日：2002-04-19
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , ALTMAN, Erik, R. , GLOSSNER, Clair, John, III , HOKENEK, Erdem , MELTZER, David , MOUDGILL, Mayan
发明人： ALTMAN, Erik, R. , GLOSSNER, Clair, John, III , HOKENEK, Erdem , MELTZER, David , MOUDGILL, Mayan
IPC分类号： G06F1/32
CPC分类号： G06F9/30083 , G06F1/3203 , G06F1/3243 , G06F8/4432 , Y02D10/152 , Y02D10/41
摘要： A microprocessor includes a logic circuit. A selection device is coupled to the logic circuit, and the selection device procides switching of on/off states of the logic circuit based on a stored logical value. A program instruction is included which sets the stored logical value control the on/off states of the logic circuit based on anticipated usage of the logical circuit in accordance with an instruction sequence of the microprocessor.
摘要翻译：微处理器包括逻辑电路。选择装置耦合到逻辑电路，并且选择装置基于存储的逻辑值来触发逻辑电路的导通/截止状态的切换。包括一个程序指令，其根据微处理器的指令序列，根据逻辑电路的预期使用情况设置存储的逻辑值来控制逻辑电路的开/关状态。

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