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91. 发明申请

WO01078489A2 A TRANSCEIVER METHOD AND SIGNAL THEREFOR EMBODIED IN A CARRIER WAVE FOR A FRAME-BASED COMMUNICATIONS NETWORK 审中-公开
标题翻译：用于基于帧的通信网络的载波波形中的收发器方法和信号
公开(公告)号：WO01078489A2
公开(公告)日：2001-10-25
申请号：PCT/US2001/010882
申请日：2001-04-04
IPC分类号： H04J3/06 , H04L1/00 , H04L1/08 , H04L1/12 , H04L1/18 , H04L12/413 , H04M11/00 , H04M11/06
CPC分类号： H04L1/0005 , H04L1/0003 , H04L1/0006 , H04L1/0009 , H04L1/0025 , H04L1/0061 , H04L1/0072 , H04L1/08 , H04L1/18 , H04L1/1809 , H04L1/1848 , H04L1/1877 , H04L1/1883 , H04L1/1887 , H04L1/20 , H04L12/40032 , H04L12/4013 , H04L12/40136 , H04L12/40156 , H04L12/40163 , H04L12/403 , H04L12/4035 , H04L12/407 , H04L12/413 , H04L12/417 , H04L2001/0093 , H04L2001/125 , H04M11/00 , H04M11/06 , Y02D50/10
摘要： A transceiver method and signal therefor embodied in a carrier wave for sending information from transmit stations to receive stations over a transmission medium of a frame-based communications network. The information is sent in transmit frames having a frame format comprising a fixed rate header, followed by a variable rate payload, followed by a fixed rate trailer. The fixed rate header includes a preamble. The preamble has a repetition of four symbol sequences for facilitating power estimation, gain control, baud frequency offset estimation, equalizer training, carrier sensing and collision detection. The preamble also includes a frame control field. The frame control field has scrambler control information for frame scrambling initialization, a priority field to determine the absolute priority a transmit frame will have when determining access to the transmission medium, a payload encoding field which determines constellation encoding of payload bits in the variable rate payload, and a header check sequence for providing a cyclic redundancy check. The variable rate payload is transmitted pursuant to dynamic adjustable frame encoding parameters for improving transmission performance for a transmit frame being transmitted from a transmitting station to a receiving station. The header also includes a destination address field, a source address field and an ethertype field.
摘要翻译：一种用于在基于帧的通信网络的传输介质上从发射站向接收站发送信息的载波中的收发器方法及其信号。信息以具有包括固定速率报头的帧格式的发送帧发送，随后是可变速率有效载荷，随后是固定速率预告。固定速率报头包括前导码。前导码具有用于促进功率估计，增益控制，波特率频率偏移估计，均衡器训练，载波侦听和冲突检测的四个符号序列的重复。前导码还包括帧控制字段。帧控制字段具有用于帧加扰初始化的加扰器控制信息，确定发送帧在确定对传输介质的访问时将具有的绝对优先级的优先级字段，确定可变速率有效载荷中的有效载荷比特的星座编码的有效载荷编码字段以及用于提供循环冗余校验的报头检查序列。根据动态可调节帧编码参数发送可变速率有效载荷，以改善从发射站发送到接收站的发射帧的传输性能。报头还包括目的地址字段，源地址字段和以太类型字段。

92. 发明申请

WO1998015088A1 LOW COST REDUNDANT COMMUNICATIONS SYSTEM 审中-公开
标题翻译：低成本冗余通信系统
公开(公告)号：WO1998015088A1
公开(公告)日：1998-04-09
申请号：PCT/US1997017632
申请日：1997-09-29
申请人： HONEYWELL INC.
发明人： HONEYWELL INC. , BIRKEDAHL, Byron, F. , EDDY, Brett, A. , HOYME, Kenneth, P.
IPC分类号： H04L12/40
CPC分类号： H04L12/40013 , G05D1/0077 , G06F11/2007 , H04L12/40 , H04L12/40189 , H04L12/407 , H04L12/413 , H04L69/40 , H04L2012/4028
摘要： A communications system capable of providing enhanced data integrity and reliability through redundant buses (107R, 107L, 107LB), and a network interface controller for use therewith are disclosed. Redundant conductors (107) conforming to well-known ethernet standards interconnect electronics components. Each component communicates with the conductors (107) through a single network interface card (NIC). Each NIC comprises an ethernet compliant transceiver (101A-C) for each ethernet conductor (107) in communication with the component. Microcontrollers (112) embedded in each NIC synchronously and deterministically place data on the ethernet conductors (107) according to a timing scheme stored in a non-volatile memory (113) means. A heartbit/power monitor (114) is also provided to ensure that data cannot be transmitted in the event of a microcontroller (112) failure. Through the inventive elements presented herein, the communications system provides a high degree of redundancy and fault-tolerance and is therefore well-suited to critical applications in avionics communication.
摘要翻译：公开了能够通过冗余总线（107R，107L，107LB）提供增强的数据完整性和可靠性的通信系统以及与其一起使用的网络接口控制器。符合众所周知的以太网标准的冗余导体（107）互连电子元件。每个组件通过单个网络接口卡（NIC）与导体（107）通信。每个NIC包括与组件通信的每个以太网导体（107）的以太网兼容收发器（101A-C）。根据存储在非易失性存储器（113）中的定时方案，嵌入在每个NIC中的微控制器（112）同步并确定地将数据放置在以太网导体（107）上。还提供了心跳/功率监视器（114）以确保在微控制器（112）发生故障的情况下无法发送数据。通过本文提出的发明内容，通信系统提供高度的冗余度和容错性，因此非常适合于航空电子通信中的关键应用。

93. 发明申请

WO9601540A3 SIGNAL PROCESSING SYSTEM 审中-公开
标题翻译：信号处理系统
公开(公告)号：WO9601540A3
公开(公告)日：1996-02-22
申请号：PCT/IB9500531
申请日：1995-06-29
申请人： PHILIPS ELECTRONICS NV , PHILIPS NORDEN AB
发明人： BLOKS RUDOLF HENRICUS JOHANNES , VLOT MARNIX CLAUDIUS
IPC分类号： H04J3/24 , H04L7/00 , H04L12/40 , H04L12/407 , H04L12/417 , H04L12/64 , H04N7/24 , H04N7/26 , H04N7/50 , H04N7/52 , H04N7/58
CPC分类号： H04L12/40058 , H04J3/247 , H04L12/40117 , H04L12/407 , H04L12/417 , H04L12/64 , H04L12/6418 , H04L2012/6435 , H04L2012/6456 , H04L2012/6483 , H04L2012/6489 , H04N19/42 , H04N19/61 , H04N21/4135 , H04N21/4305 , H04N21/4307 , H04N21/4342 , H04N21/43632
摘要： A signal processing system comprising a source apparatus coupled to a destination apparatus, the source apparatus being arranged for supplying the destination apparatus with a signal comprising video data, a time-stamp and synchronization data representing a time-value of an instant of said supplying, the destination apparatus being arranged for receiving the signal, synchronizing a time-value of a clock in accordance with the synchronization data, detecting when the time-value of the clock corresponds to the time-stamp and for thereupon presenting the video data at an output, the system being characterized, in that it comprises a bus operable according to a time-slot allocation protocol, the source apparatus supplying the signal to the destination apparatus via the bus, the source apparatus comprising a first interface unit for buffering the signal until an allocated time-slot is available on the bus, the source apparatus setting the synchronization data according to an instant the signal is supplied to the first interface unit, the destination apparatus comprising a buffer, for buffering the signal prior to synchronizing the time-value of the clock for a predetermined interval, at least equal to a maximum wait-interval for the allocation of a time-slot on the bus, has elapsed after the instant the signal is supplied to the first interface unit.

94. 发明申请

WO1996001540A2 SIGNAL PROCESSING SYSTEM 审中-公开
标题翻译：信号处理系统
公开(公告)号：WO1996001540A2
公开(公告)日：1996-01-18
申请号：PCT/IB1995000531
申请日：1995-06-29
申请人： PHILIPS ELECTRONICS N.V. , PHILIPS NORDEN AB
发明人： PHILIPS ELECTRONICS N.V. , PHILIPS NORDEN AB , BLOKS, Rudolf, Henricus, Johannes , VLOT, Marnix, Claudius
IPC分类号： H04N07/58
CPC分类号： H04L12/40058 , H04J3/247 , H04L12/40117 , H04L12/407 , H04L12/417 , H04L12/64 , H04L12/6418 , H04L2012/6435 , H04L2012/6456 , H04L2012/6483 , H04L2012/6489 , H04N19/42 , H04N19/61 , H04N21/4135 , H04N21/4305 , H04N21/4307 , H04N21/4342 , H04N21/43632
摘要： A signal processing system comprising a source apparatus coupled to a destination apparatus, the source apparatus being arranged for supplying the destination apparatus with a signal comprising video data, a time-stamp and synchronization data representing a time-value of an instant of said supplying, the destination apparatus being arranged for receiving the signal, synchronizing a time-value of a clock in accordance with the synchronization data, detecting when the time-value of the clock corresponds to the time-stamp and for thereupon presenting the video data at an output, the system being characterized, in that it comprises a bus operable according to a time-slot allocation protocol, the source apparatus supplying the signal to the destination apparatus via the bus, the source apparatus comprising a first interface unit for buffering the signal until an allocated time-slot is available on the bus, the source apparatus setting the synchronization data according to an instant the signal is supplied to the first interface unit, the destination apparatus comprising a buffer, for buffering the signal prior to synchronizing the time-value of the clock for a predetermined interval, at least equal to a maximum wait-interval for the allocation of a time-slot on the bus, has elapsed after the instant the signal is supplied to the first interface unit.
摘要翻译：一种信号处理系统，包括耦合到目的地设备的源设备，所述源设备被布置为向目的地设备提供包括视频数据的信号，时间戳和表示所述供应时刻的时间值的同步数据，目的地装置被布置成用于接收信号，根据同步数据同步时钟的时间值，检测时钟的时间值对应于时间标记，并且随后在输出端呈现视频数据所述系统的特征在于，其包括可根据时隙分配协议操作的总线，所述源装置经由所述总线向所述目的地装置提供所述信号，所述源装置包括用于缓冲所述信号的第一接口单元，直到分配的时隙在总线上可用，源设备根据时刻设置同步数据提供给第一接口单元，目的地设备包括缓冲器，用于在将时钟的时间值同步预定间隔之前缓冲信号，至少等于用于分配时间的最大等待间隔在信号被提供给第一接口单元之后经过了总线上的时隙。

95. 发明申请

WO1995003658A1 BUS MANAGEMENT SYSTEM 审中-公开
标题翻译：总线管理系统
公开(公告)号：WO1995003658A1
公开(公告)日：1995-02-02
申请号：PCT/JP1994001188
申请日：1994-07-19
申请人： SONY CORPORATION , MATSUNO, Katsumi , KUBOTA, Ichiro , HAYASHI, Minobu , SHIMA, Hisato
发明人： SONY CORPORATION
IPC分类号： H04L12/40
CPC分类号： H04L12/407 , H04L12/40013 , H04L12/40032 , H04L12/40052 , H04L12/40058 , H04L12/40065 , H04L12/40117 , H04L12/403 , H04L12/44 , H04L12/6418 , H04L41/00
摘要： A bus management node (11) is provided with a used-channel register REG1 and bus capacity register REG2. Before starting synchronous communication, each node (12) transmits a read instruction to the registers REG1 and REG2 to read their contents so as to check for available channels and bus capacity. When an unused channel exists and a bus capacity remains, the node (12) transmits a write instruction to the registers REG1 and REG2 so that the number of used channels and the capacity of used buses can be respectively stored in the registers REG1 and REG2. Therefore, buses can be managed by a simple method in a system which performs synchronous communication among a plurality of nodes connected to the buses.
摘要翻译：总线管理节点（11）具有使用信道寄存器REG1和总线容量寄存器REG2。在开始同步通信之前，每个节点（12）将读指令发送到寄存器REG1和REG2以读取它们的内容，以便检查可用信道和总线容量。当存在未使用的信道并且总线容量保持时，节点（12）向寄存器REG1和REG2发送写入指令，使得所使用的信道的数量和所使用的总线的容量可以分别存储在寄存器REG1和REG2中。因此，可以通过在连接到总线的多个节点之间执行同步通信的系统中的简单方法来管理总线。

96. 发明申请

WO1994023516A1 MEDIA ACCESS PROTOCOL FOR TDM BUS NETWORK 审中-公开
标题翻译：媒体访问协议用于TDM总线网络
公开(公告)号：WO1994023516A1
公开(公告)日：1994-10-13
申请号：PCT/US1994003502
申请日：1994-03-31
申请人： HONEYWELL INC.
发明人： HONEYWELL INC. , DRISCOLL, Kevin, R.
IPC分类号： H04L12/40
CPC分类号： H04L12/4015 , H04L12/4035 , H04L12/407
摘要： A media access protocol provides a fixed frame length and limited arbitration among certain predetermined users by providing limited arbitration during certain fixed time slots of a table driven proportional access system.
摘要翻译：媒体访问协议通过在表驱动比例访问系统的某些固定时隙期间提供有限仲裁来在某些预定用户之间提供固定的帧长度和有限的仲裁。

97. 发明申请

WO1985005745A1 DATA TRANSMISSION METHOD AND APPARATUS 审中-公开
标题翻译：数据传输方法和设备
公开(公告)号：WO1985005745A1
公开(公告)日：1985-12-19
申请号：PCT/GB1985000229
申请日：1985-05-29
申请人： MESH DATA LIMITED , SQUIBB, Nigel, John , TAYLOR, Paul, Stuart
发明人： MESH DATA LIMITED
IPC分类号： H04B01/66
CPC分类号： H04L12/40136 , H04J13/16 , H04J14/005 , H04L12/407
摘要： A method of increasing the data transmission capacity of a cable type communication system comprises providing spread sprectum (pseudo-noise) apparatus connected or coupled to the cable for simultaneous communication therethrough with the existing communication equipment without interference with the latter. There is also disclosed a local area network computer system employing radiated spread spectrum signals using a common code sequence.
摘要翻译：一种增加电缆型通信系统的数据传输能力的方法包括提供连接或耦合到电缆的扩展支架（伪噪声）装置，用于与现有的通信设备同时通信，而不会与之干扰。还公开了使用公共码序列使用辐射扩频信号的局域网计算机系统。

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