专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2018118262A1 FINE-FEATURED TRACES FOR INTEGRATED CIRCUIT PACKAGE SUPPORT STRUCTURES 审中-公开
公开(公告)号：WO2018118262A1
公开(公告)日：2018-06-28
申请号：PCT/US2017/061051
申请日：2017-11-10
申请人： INTEL CORPORATION
发明人： FERGUSON, Shelby , OUYANG, Gong , AOKI, Russell S. , ZHANG, Zhichao , XIAO, Kai
IPC分类号： H05K1/02 , H05K1/18 , H05K3/34
CPC分类号： H01L23/345 , H01L23/49816 , H01L23/49838 , H01L2224/16225
摘要： Disclosed herein are fine-featured traces for integrated circuit (IC) package support structures, and related systems, devices, and methods. For example, a device may include a printed circuit board (PCB) having an insulating material and a heater trace on the insulating material. In some embodiments, the heater trace may have a section with a width less than 3.5 mils. In some embodiments, a section of the heater trace may be adjacent to a burned portion of the insulating material.

2. 发明申请

WO2019066952A1 TUNABLE PASSIVE SEMICONDUCTOR ELEMENTS 审中-公开
公开(公告)号：WO2019066952A1
公开(公告)日：2019-04-04
申请号：PCT/US2017/054564
申请日：2017-09-29
申请人： INTEL CORPORATION
发明人： ZHANG, Zhichao , AYGUN, Kemal , MEKONNEN, Yidnekachew S.
IPC分类号： H01L25/07 , H01L23/498 , H01L23/00 , H01L25/16
摘要： Passive semiconductor components and switches may be formed directly in, on, about, or across each of two or more semiconductor dies included in a stacked-die semiconductor package. At least some of the passive semiconductor components and/or switches may be formed in redistribution layers operably coupled to corresponding semiconductor dies included in the stacked-die semiconductor package. The switches may have multiple operating states and may be operably coupled to the passive semiconductor components such that one or more passive semiconductor components may be selectively included in one or more circuits or excluded from one or more circuits. The switches may be manually controlled or autonomously controlled using one or more control circuits. The one or more control circuits may receive one or more input signals containing host system information and/or data that is used to adjust or set the operating state of at least some of the switches.

3. 发明申请

WO2019066924A1 ANTENNA PACKAGE USING BALL ATTACH ARRAY TO CONNECT ANTENNA AND BASE SUBSTRATES 审中-公开
公开(公告)号：WO2019066924A1
公开(公告)日：2019-04-04
申请号：PCT/US2017/054395
申请日：2017-09-29
申请人： INTEL CORPORATION , YAO, Jimin , LIFF, Shawna M. , LAMBERT, William J. , ZHANG, Zhichao , SANKMAN, Robert L. , CHAVALI, Sri Chaitra J.
发明人： YAO, Jimin , LIFF, Shawna M. , LAMBERT, William J. , ZHANG, Zhichao , SANKMAN, Robert L. , CHAVALI, Sri Chaitra J.
IPC分类号： H01Q9/04 , H01Q1/38 , H01Q1/22
摘要： In accordance with disclosed embodiments, there is an antenna package using a ball attach array to connect an antenna and base substrates of the package. One example is an RF RF module package including an RF antenna package having a stack material in between a top and a bottom antenna layer to form multiple antenna plane surfaces, a base package having alternating patterned conductive and dielectric layers to form routing through the base package, and a bond between a bottom surface of the antenna package and to a top surface of the base package.

4. 发明申请

WO2019236230A1 ANTENNA MODULES AND COMMUNICATION DEVICES 审中-公开
公开(公告)号：WO2019236230A1
公开(公告)日：2019-12-12
申请号：PCT/US2019/030838
申请日：2019-05-06
申请人： INTEL CORPORATION
发明人： DALMIA, Sidharth , THAI, Trang , LAMBERT, William James , ZHANG, Zhichao , SUN, Jiwei
IPC分类号： H01Q9/04 , H01Q21/06
摘要： Disclosed herein are antenna boards, antenna modules, and communication devices. For example, in some embodiments, an antenna module includes: an antenna patch support including a flexible portion; an integrated circuit (IC) package coupled to the antenna patch support; and an antenna patch coupled to the antenna patch support, wherein the antenna patch is a millimeter wave antenna patch, and the IC package and the antenna patch are coupled to opposite faces of the antenna patch support.

5. 发明申请

WO2017171884A1 FINE FEATURE FORMATION TECHNIQUES FOR PRINTED CIRCUIT BOARDS 审中-公开
标题翻译：印制电路板精细特征形成技术
公开(公告)号：WO2017171884A1
公开(公告)日：2017-10-05
申请号：PCT/US2016/025772
申请日：2016-04-02
申请人： INTEL CORPORATION
发明人： ZHANG, Zhichao , OUYANG, Gong , XIAO, Kai , LI, Eric , AYGUN, Kemal
IPC分类号： H05K3/02 , H05K3/46
CPC分类号： H05K3/0026 , H05K1/0228 , H05K3/027 , H05K3/4694 , H05K2201/09227 , H05K2201/09727 , H05K2203/107 , H05K2203/1476
摘要： Fine feature formation techniques for printed circuit boards are described. In one embodiment, for example, a method may comprise fabricating a conductive structure 306 on a low density interconnect (LDI) printed circuit board (PCB) 150 according to an LDI fabrication process and forming one or more fine conductive features on the LDI PCB by performing a fine feature formation (FFF) process, the FFF process to comprise removing conductive material of the conductive structure along an excision path to form a fine gap region 308 within the conductive structure. Other embodiments are described and claimed.
摘要翻译：描述了用于印刷电路板的精细特征形成技术。在一个实施例中，例如，方法可以包括根据LDI制造工艺在低密度互连（LDI）印刷电路板（PCB）150上制造导电结构306，并且通过以下步骤在LDI PCB上形成一个或多个精细导电特征：执行精细特征形成（FFF）工艺，FFF工艺包括沿着切除路径去除导电结构的导电材料以在导电结构内形成精细间隙区域308。描述并要求保护其他实施例。

6. 发明申请

WO2017112048A1 SMART IMPEDANCE MATCHING FOR HIGH-SPEED I/O 审中-公开
标题翻译：智能阻抗匹配适用于高速I / O
公开(公告)号：WO2017112048A1
公开(公告)日：2017-06-29
申请号：PCT/US2016/056890
申请日：2016-10-13
申请人： INTEL CORPORATION
发明人： SONG, Hongjiang , SONG, Yan W. , QIAN, Zhiguo , ZHANG, Zhichao
IPC分类号： H03H7/40 , H04L25/08 , H03H11/30
CPC分类号： H03K19/0005 , H03K19/017545
摘要： Embodiments are generally directed to smart impedance matching for high-speed I/O. In some embodiments, a circuit includes an impedance sensing block; a finite state machine to provide impedance tuning for a driver; and a control block, the control block to provide a feedback loop to check and tune impedance of the driver. The impedance sensing block is to sample an output voltage of the driver to determine whether the impedance of the driver is greater than or less than an impedance of the channel; and the finite state machine is to produce a signal to decrease or increase the impedance of the driver based on the determination whether the impedance of the driver is greater than or less than the impedance of the channel.
摘要翻译：实施例通常针对用于高速I / O的智能阻抗匹配。在一些实施例中，电路包括阻抗感测块; 为驱动器提供阻抗调谐的有限状态机; 和控制块，控制块提供反馈回路以检查和调整驱动器的阻抗。阻抗感测模块用于对驱动器的输出电压进行采样，以确定驱动器的阻抗是大于还是小于通道的阻抗; 并且有限状态机将基于确定驱动器的阻抗是大于还是小于通道的阻抗来产生用于减小或增加驱动器的阻抗的信号。

7. 发明申请

WO2017095507A1 SHIELDING MOLD 审中-公开
标题翻译：屏蔽模具
公开(公告)号：WO2017095507A1
公开(公告)日：2017-06-08
申请号：PCT/US2016/053410
申请日：2016-09-23
申请人： INTEL CORPORATION
发明人： ZHANG, Zhichao , ELSHERBINI, Adel A. , SANKMAN, Robert L. , AYGUN, Kemal
IPC分类号： H05K1/02 , H05K9/00
CPC分类号： H05K1/0216 , H01L23/552 , H05K1/025 , H05K1/181 , H05K3/284 , H05K2203/1322 , Y02P70/611
摘要： An electronic package having a substrate that includes signal traces and ground traces; an electronic component mounted on an upper surface of the substrate such that the electronic component is electrically connected to the signal traces and the ground traces in the substrate; an insulating layer covering the electronic component and the upper surface of the substrate; and an electromagnetic interference shielding mold covering the insulation layer such that the electromagnetic interference shielding mold is electrically connected to the ground traces in the substrate. In some forms of the electronic package, the electromagnetic interference shielding mold is electrically connected to the ground traces through openings in the insulation layer.
摘要翻译：具有包括信号迹线和接地迹线的基板的电子封装; 安装在所述基板的上表面上的电子部件，使得所述电子部件电连接到所述基板中的信号迹线和接地迹线; 覆盖电子部件和基板的上表面的绝缘层; 以及覆盖绝缘层的电磁干扰屏蔽模具，使得电磁干扰屏蔽模具电连接到基板中的接地迹线。在电子封装的某些形式中，电磁干扰屏蔽模具通过绝缘层中的开口电连接到接地迹线。

8. 发明申请

WO2022139908A1 OPTICAL MULTICHIP PACKAGE WITH MULTIPLE SYSTEM-ON-CHIP DIES 审中-公开
公开(公告)号：WO2022139908A1
公开(公告)日：2022-06-30
申请号：PCT/US2021/051137
申请日：2021-09-20
申请人： INTEL CORPORATION
发明人： ZHANG, Zhichao , AYGÜN, Kemal , POTHUKUCHI, Suresh V. , LI, Xiaoqian , KARHADE, Omkar
IPC分类号： H01L25/16 , H01L23/36 , H01L23/522 , H01L23/00
摘要： Embodiments described herein may be related to apparatuses, processes, and techniques related to disaggregating co-packaged SOC and photonic integrated circuits on an multichip package. The photonic integrated circuits may also be silicon photonics engines. In embodiments, multiple SOCs and photonic integrated circuits may be electrically coupled, respectively, into modules, with multiple modules then incorporated into an MCP using a stacked die structure. Other embodiments may be described and/or claimed.

9. 发明申请

WO2022108647A1 HIGH BANDWIDTH OPTICAL INTERCONNECTION ARCHITECTURES 审中-公开
公开(公告)号：WO2022108647A1
公开(公告)日：2022-05-27
申请号：PCT/US2021/049666
申请日：2021-09-09
申请人： INTEL CORPORATION
发明人： PIETAMBARAM, Srinivas V. , MARIN, Brandon C. , PAITAL, Sameer , VADLIMANI, Sai , MANEPALLI, Rahul N. , LI, Xiaoqian , POTHUKUCHI, Suresh V. , SHARAN, Sujit , SARKAR, Arnab , KARHADE, Omkar , DESHPANDE, Nitin , PRATAP, Divya , ECTON, Jeremy , MALLIK, Debendra , MAHAJAN, Ravindranath V. , ZHANG, Zhichao , AYGÜN, Kemal , NIE, Bai , DARMAWIKARTA, Kristof , JAUSSI, James E. , GAMBA, Jason M. , CASPER, Bryan K. , DUAN, Gang , INTI, Rajesh , MANSURI, Mozhgan , JADHAV, Susheel , BROWN, Kenneth , AGRAWAL, Ankar , DOBRIYAL, Priyanka
IPC分类号： G02B6/42 , H01L31/0203 , H01L23/538 , H01L25/16
摘要： Embodiments disclosed herein include optical packages. In an embodiment, an optical package comprises a package substrate, and a photonics die coupled to the package substrate. In an embodiment, a compute die is coupled to the package substrate, where the photonics die is communicatively coupled to the compute die by a bridge in the package substrate. In an embodiment, the optical package further comprises an optical waveguide embedded in the package substrate. In an embodiment, a first end of the optical waveguide is below the photonics die, and a second end of the optical waveguide is substantially coplanar with an edge of the package substrate.

10. 发明申请

WO2019194917A1 INTEGRATED CIRCUIT STRUCTURES IN PACKAGE SUBSTRATES 审中-公开
公开(公告)号：WO2019194917A1
公开(公告)日：2019-10-10
申请号：PCT/US2019/020275
申请日：2019-03-01
申请人： INTEL CORPORATION
发明人： GANESAN, Sanka , LAMBERT, William James , ZHANG, Zhichao , CHAVALI, Sri Chaitra Jyotsna , SMITH, Stephen Andrew , HILL, Michael James , JIANG, Zhenguo
IPC分类号： H01L23/522 , H01L23/498 , H01L23/528 , H01L23/13 , H01L23/00 , H01L25/065
摘要： Disclosed herein are integrated circuit (IC) structures that may be included in package substrates. For example, disclosed herein are passive components in package substrate, wherein the passive components include at least one non-circular via and at least one pad in contact with the at least one non-circular via, and the passive components include an inductor or a capacitor. Other embodiments are also disclosed.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式