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1. 发明申请

WO2012087583A3 MECHANISM FOR CONFLICT DETECTION USING SIMD 审中-公开
标题翻译：使用SIMD进行冲突检测的机制
公开(公告)号：WO2012087583A3
公开(公告)日：2012-09-27
申请号：PCT/US2011063836
申请日：2011-12-07
申请人： INTEL CORP , SMELYANSKIY MIKHAIL , CHEN YEN-KUANG , KIM DAEHYUN , HUGHES CHRISTOPHER J , LEE VICTOR W
发明人： SMELYANSKIY MIKHAIL , CHEN YEN-KUANG , KIM DAEHYUN , HUGHES CHRISTOPHER J , LEE VICTOR W
IPC分类号： G06F13/16 , G06F15/80
CPC分类号： G06F9/3887 , G06F9/345
摘要： A system and method are configured to detect conflicts when converting scalar processes to parallel processes ("SIMDifying"). Conflicts may be detected for an unordered single index, an ordered single index and/or ordered pairs of indices. Conflicts may be further detected for read-after-write dependencies. Conflict detection is configured to identify operations (i.e., iterations) in a sequence of iterations that may not be done in parallel.
摘要翻译：将系统和方法配置为在将标量过程转换为并行进程（“SIMDifying”）时检测冲突。可以针对无序单索引，有序单索引和/或有序索引对检测冲突。读写依赖关系可能会进一步检测到冲突。冲突检测被配置为识别可能不并行完成的迭代序列中的操作（即迭代）。

2. 发明申请

WO2009120981A2 VECTOR INSTRUCTIONS TO ENABLE EFFICIENT SYNCHRONIZATION AND PARALLEL REDUCTION OPERATIONS 审中-公开
标题翻译：向导说明能够实现高效的同步和并行减少运行
公开(公告)号：WO2009120981A2
公开(公告)日：2009-10-01
申请号：PCT/US2009038596
申请日：2009-03-27
申请人： INTEL CORP , SMELYANSKIY MIKHAIL , KUMAR SANJEEV , KIM DAEHYUN , LEE VICTOR W , NGUYEN ANTHONY D , CHEN YEN-KUANG , HUGHES CHRISTOPHER , KIM CHANGKYU , CHHUGANI JATIN
发明人： SMELYANSKIY MIKHAIL , KUMAR SANJEEV , KIM DAEHYUN , LEE VICTOR W , NGUYEN ANTHONY D , CHEN YEN-KUANG , HUGHES CHRISTOPHER , KIM CHANGKYU , CHHUGANI JATIN
IPC分类号： G06F9/38 , G06F9/445 , G06F15/80
CPC分类号： G06F9/30036 , G06F9/30018 , G06F9/30021 , G06F9/30032 , G06F9/3004 , G06F9/30043 , G06F9/30087 , G06F9/3834 , G06F9/3885 , G06K9/6212 , G06T5/40 , H04N1/4074
摘要： In one embodiment, a processor may include a vector unit to perform operations on multiple data elements responsive to a single instruction, and a control unit coupled to the vector unit to provide the data elements to the vector unit, where the control unit is to enable an atomic vector operation to be performed on at least some of the data elements responsive to a first vector instruction to be executed under a first mask and a second vector instruction to be executed under a second mask. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，处理器可以包括向量单元，用于响应于单个指令对多个数据元素执行操作;以及控制单元，耦合到向量单元，以将数据元素提供给向量单元，其中控制单元将使能响应于在第一掩模下执行的第一向量指令和在第二掩码下执行的第二向量指令，对至少一些数据元素执行的原子向量操作。描述和要求保护其他实施例。

3. 发明申请

WO2012087548A3 VECTOR CONFLICT INSTRUCTIONS 审中-公开
标题翻译：矢量冲突指示
公开(公告)号：WO2012087548A3
公开(公告)日：2012-08-16
申请号：PCT/US2011063307
申请日：2011-12-05
申请人： INTEL CORP , HUGHES CHRISTOPHER J , CHARNEY MARK J , CHEN YEN-KUANG , CORBAL JESUS , FORSYTH ANDREW T , GIRKAR MILIND B , HALL JONATHAN C , IDO HIDEKI , VALENTINE ROBERT , WIEDEMEIER JEFFREY
发明人： HUGHES CHRISTOPHER J , CHARNEY MARK J , CHEN YEN-KUANG , CORBAL JESUS , FORSYTH ANDREW T , GIRKAR MILIND B , HALL JONATHAN C , IDO HIDEKI , VALENTINE ROBERT , WIEDEMEIER JEFFREY
IPC分类号： G06F9/30
CPC分类号： G06F9/30036 , G06F9/30018 , G06F9/30021 , G06F9/30032 , G06F9/30043 , G06F9/3838
摘要： A processing core implemented on a semiconductor chip is described having first execution unit logic circuitry that includes first comparison circuitry to compare each element in a first input vector against every element of a second input vector. The processing core also has second execution logic circuitry that includes second comparison circuitry to compare a first input value against every data element of an input vector.
摘要翻译：描述了在半导体芯片上实现的处理核心，其具有包括第一比较电路的第一执行单元逻辑电路，以将第一输入向量中的每个元素与第二输入向量的每个元素进行比较。处理核心还具有第二执行逻辑电路，其包括第二比较电路，用于将第一输入值与输入向量的每个数据元素进行比较。

4. 发明申请

WO2006072061A3 SYSTEM AND METHOD FOR NON-UNIFORM CACHE IN A MULTI-CORE PROCESSOR 审中-公开
标题翻译：在多核处理器中进行非均匀高速缓存的系统和方法
公开(公告)号：WO2006072061A3
公开(公告)日：2007-01-18
申请号：PCT/US2005047592
申请日：2005-12-27
申请人： INTEL CORP , HUGHES CHRISTOPHER , TUCK III JAMES , LEE VICTOR , CHEN YEN-KUANG
发明人： HUGHES CHRISTOPHER , TUCK III JAMES , LEE VICTOR , CHEN YEN-KUANG
IPC分类号： G06F12/08
CPC分类号： G06F12/084 , G06F12/0833 , G06F12/0846 , G06F12/0853 , G06F2212/271
摘要： A system and method for the design and operation of a distributed shared cache in a multi-core processor is disclosed. In one embodiment, the shared cache may be distributed among multiple cache molecules. Each of the cache molecules may be closest, in terms of access latency time, to one of the processor cores. In one embodiment, a cache line brought in from memory may initially be placed into a cache molecule that is not closest to a requesting processor core. When the requesting processor core makes repeated accesses to that cache line, it may be moved either between cache molecules or within a cache molecule. Due to the ability to move the cache lines within the cache, in various embodiments special search methods may be used to locate a particular cache line.
摘要翻译：公开了一种用于在多核处理器中设计和操作分布式共享高速缓存的系统和方法。在一个实施例中，共享高速缓存可以分布在多个高速缓存分子之间。每个缓存分子在访问延迟时间方面可能最接近于处理器核心之一。在一个实施例中，从存储器引入的高速缓存行可以最初被放置在不最接近请求处理器核的高速缓存分
区中。当请求处理器核心重复访问该高速缓存行时，其可以在高速缓存分子之间或高速缓存分子内移动。由于能够将高速缓存线移动到高速缓存内，在各种实施例中，可以使用特殊搜索方法来定位特定的高速缓存行。

5. 发明申请

WO2006072064A3 SYSTEM AND METHOD FOR CACHE COHERENCY IN A CACHE WITH DIFFERENT CACHE LOCATION LENGTHS 审中-公开
标题翻译：用于具有不同高速缓存位置长度的高速缓存中的高速缓存一致性的系统和方法
公开(公告)号：WO2006072064A3
公开(公告)日：2006-09-14
申请号：PCT/US2005047595
申请日：2005-12-27
申请人： INTEL CORP , CHEN YEN-KUANG , HUGHES CHRISTOPHER , TUCK III JAMES
发明人： CHEN YEN-KUANG , HUGHES CHRISTOPHER , TUCK III JAMES
IPC分类号： G06F12/04 , G06F12/08
CPC分类号： G06F12/04 , G06F12/0817 , G06F12/0886 , Y10S707/99952
摘要： A system and method for the design and operation of a cache system with differing cache location lengths in level one caches is disclosed. In one embodiment, each level one cache may include groups of cache locations of differing length, capable of holding portions of a level two cache line. A state tree may be created from data in a sharing vector. When a request arrives from a level one cache, the level two cache may examine the nodes of the state tree to determine whether the node of the state tree corresponding to the incoming request is already active. The results of this determination may be used to inhibit or permit the concurrent processing of the request.
摘要翻译：公开了一种用于在一级高速缓存中设计和操作具有不同高速缓存位置长度的高速缓存系统的系统和方法。在一个实施例中，每个一级高速缓存可以包括不同长度的高速缓存位置组，其能够保存二级高速缓存线的部分。状态树可以从共享向量中的数据创建。当请求从一级高速缓存到达时，二级高速缓存可以检查状态树的节点以确定与输入请求相对应的状态树的节点是否已经是活动的。该确定的结果可用于禁止或允许请求的并行处理。

6. 发明申请

WO2004034263A3 PERFORMING VIDEO/IMAGE DATA ACCESS IN ACCORDANCE WTH MEMORY ACCESS PATTERN: MPEG-4, JPEG2000 STREAMING SIMD EXTENSIONS 审中-公开
标题翻译：根据视频/图像数据访问WTH存储器访问模式：MPEG-4，JPEG2000流水线SIMD扩展
公开(公告)号：WO2004034263A3
公开(公告)日：2005-11-24
申请号：PCT/US0330572
申请日：2003-09-26
申请人： INTEL CORP
发明人： DEBES ERIC , CHEN YEN-KUANG , HOLLIMAN MATTHEW , YEUNG MINERVA
IPC分类号： G06F12/08 , G06T1/60 , G09G5/393 , G06F9/345 , G06T1/20
CPC分类号： G06F12/0875 , G06F12/0848 , G06F12/0897 , G06T1/60 , G09G5/393
摘要： An apparatus and method for performing data access in accordance with memory access patterns are described. In one embodiment, the method includes the determination, in response to a memory access instruction, of a memory access pattern of data requested by the memory access instruction. Once the memory access pattern is determined, the data requested by the memory access instruction is accessed according to the determined memory access pattern. Finally, once the data is accessed, the data is processed according to the memory access instruction. Accordingly, in this embodiment of the present invention, data is accessed according to memory access patterns including zig-zag patterns scan, Zerotree scan, bit plane extraction, fine granularity scalability or the like.
摘要翻译：描述了根据存储器访问模式执行数据访问的装置和方法。在一个实施例中，该方法包括响应于存储器访问指令确定由存储器访问指令请求的数据的存储器访问模式。一旦确定了存储器访问模式，则根据所确定的存储器访问模式访问由存储器访问指令请求的数据。最后，访问数据后，根据存储器访问指令对数据进行处理。因此，在本发明的这个实施例中，根据存储器访问模式访问数据，包括锯齿形图案扫描，Zerotree扫描，位平面提取，细粒度可伸缩性等。

7. 发明申请

WO03023600A2 AN APPARATUS AND METHOD FOR EXTRACTING AND LOADING DATA TO/FROM A BUFFER 审中-公开
标题翻译：一种用于从缓冲器提取和加载数据的装置和方法
公开(公告)号：WO03023600A2
公开(公告)日：2003-03-20
申请号：PCT/US0227725
申请日：2002-08-30
申请人： INTEL CORP
发明人： MACY WILLIAM JR , HOLLIMAN MATTHEW , DEBES ERIC , CHEN YEN-KUANG
IPC分类号： G06F9/34 , G06F1/00 , G06F5/01 , G06F5/06 , G06F9/305 , G06F9/38 , G06F12/04 , H03M7/30
CPC分类号： G06F5/065
摘要： An apparatus and method for extracting and loading data to/from a buffer are described. The method includes the selection of data from a data buffer in response to execution of a data access instruction. The data buffer includes a plurality of data storage devices, one or more of which initially contain the selected data. Accordingly, the plurality of data storage devices form a single address space that is addressable at a bit- level. When the selected data spans from a source data storage device to a next data storage device of the data buffer, a portion of the selected data from source data storage device is concatenated with a remaining portion of the selected data from the next data storage device to form the selected data as a contiguous unit. Finally, once the selected data is formed, the selected data is stored within a destination data storage device.
摘要翻译：描述了一种用于提取和从缓冲器加载数据的装置和方法。该方法包括响应于数据访问指令的执行从数据缓冲器中选择数据。数据缓冲器包括多个数据存储设备，其中一个或多个初始地包含所选择的数据。因此，多个数据存储装置形成在位层可寻址的单个地址空间。当所选择的数据从源数据存储装置跨越到数据缓冲器的下一个数据存储装置时，来自源数据存储装置的所选数据的一部分与来自下一数据存储装置的所选数据的剩余部分相连，将所选数据形成为连续单位。最后，一旦形成所选择的数据，所选择的数据被存储在目的地数据存储装置中。

8. 发明申请

WO2004034265A2 AN APPARATUS AND METHOD FOR FACILITATING MEMORY DATA ACCESS WITH GENERIC READ/WRITE PATTERNS 审中-公开
标题翻译：用于通用读/写模式来提高存储器数据访问的装置和方法
公开(公告)号：WO2004034265A2
公开(公告)日：2004-04-22
申请号：PCT/US0330578
申请日：2003-09-26
申请人： INTEL CORP
发明人： CHEN YEN-KUANG , DEBES ERIC , HOLLIMAN MATTHEW , YEUNG MINERVA
IPC分类号： G06F12/08 , G06T1/60 , G06T9/00 , G09G5/393 , G06F12/02 , G06F9/38 , G06T1/20
CPC分类号： G06F12/0875 , G06F12/0877 , G06T1/60 , G06T9/00 , G09G5/393 , G09G2360/121
摘要： An apparatus and method facilitating memory data access with generic read/write patterns are described. In one embodiment, the method includes the detection, in response to a load instruction, of a cache hit/cache miss of data requested by the load instruction within a re-tiling (RT) cache. When a cache miss is detected, a block of data is loaded into the RT cache according to the load instruction. This block of data will contain the data requested by the load instruction. Once loaded, a non-horizontally sequential access of the data requested by the load instruction is performed from the RT cache. Finally, the data accessed from the RT cache may be stored into a destination data storage device according to the load instruction.
摘要翻译：描述了利用通用读/写模式促进存储器数据访问的装置和方法。在一个实施例中，该方法包括响应于加载指令，检测在重新平铺（RT）高速缓存内由加载指令请求的数据的高速缓存命中/高速缓存未命中。当检测到高速缓存未命中时，根据加载指令将一块数据加载到RT缓存中。该数据块将包含加载指令请求的数据。一旦加载，从RT缓存执行加载指令请求的数据的非水平顺序访问。最后，从RT缓存访问的数据可以根据加载指令存储到目的地数据存储装置中。

9. 发明申请

WO03058973A3 ZIGZAG SCAN ORDER FOR IMAGE/VIDEO ENCODER AND DECODER 审中-公开
标题翻译： ZIGZAG扫描图像/视频编码器和解码器的命令
公开(公告)号：WO03058973A3
公开(公告)日：2003-10-16
申请号：PCT/US0239264
申请日：2002-12-05
申请人： INTEL CORP
发明人： CHEN YEN-KUANG , PENG WEN-HSIAO
IPC分类号： G06T9/00 , H04N7/26 , H04N7/30 , H04N7/50
CPC分类号： H04N19/37 , H04N19/60
摘要： In an encoding or decoding process for compressible data, non-raster ordered bitstreams of transform data are rearranged in memory so later data access is contiguous, efficiently allowing processing in a single cache line. In an encoder, rearrangement can utilize a buffer copy that enables address calculation to performed only once per block.
摘要翻译：在用于可压缩数据的编码或解码过程中，变换数据的非光栅有序比特流被重新排列在存储器中，所以稍后的数据访问是连续的，有效地允许在单个高速缓存行中进行处理。在编码器中，重排可以利用一个缓冲区副本，使得地址计算只能在每个块中执行一次。

10. 发明申请

WO02056599A2 METHOD AND APPARATUS FOR PROVIDING PREDICTION MODE FINE GRANULARITY SCALABILITY 审中-公开
标题翻译：提供预测模式精细粒度可扩展性的方法和装置
公开(公告)号：WO02056599A2
公开(公告)日：2002-07-18
申请号：PCT/US0200527
申请日：2002-01-07
申请人： INTEL CORP
发明人： CHEN YEN-KUANG , PENG WEN-HSIAO
IPC分类号： G06T9/00 , H03M7/36 , H04N19/30 , H04N7/26 , H04N7/50
CPC分类号： H04N19/34 , H04N19/105 , H04N19/164 , H04N19/184 , H04N19/61
摘要： In an encoding process, video data are represented as a bitstream of a quantisized base layer and at least two enhancement layers, with each picture in each layer identified by a start code. The base layer, plus a number of enhancement layers capable of being transmitted by the communication channel's bandwidth, are transmitted on the communication channel.
摘要翻译：在编码处理中，视频数据被表示为量化的基本层和至少两个增强层的比特流，每层中的每个图像由起始码标识。在通信信道上发送基本层，以及能够通过通信信道的带宽发送的多个增强层。

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