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1. 发明申请

WO2006103563A3 METHOD AND APPARATUS FOR REDUCING SYSTEM INACTIVITY DURING TIME DATA FLOAT DELAY AND EXTERNAL MEMORY WRITE 审中-公开
标题翻译：在数据流延迟和外部存储器写入期间减少系统不活动的方法和装置
公开(公告)号：WO2006103563A3
公开(公告)日：2007-04-26
申请号：PCT/IB2006000957
申请日：2006-03-24
申请人： ATMEL CORP , MATULIK ERIC , RESCANIERES NICOLAS , LAFAGE ANNE
发明人： MATULIK ERIC , RESCANIERES NICOLAS , LAFAGE ANNE
IPC分类号： G06F13/00 , G06F3/00
CPC分类号： G06F13/405 , G06F13/4243
摘要： The invention comprises a system for reducing inactive periods in an integrated circuit. The integrated circuit (600) is coupled to an external peripheral by an external data bus (640). The integrated circuit (600) has a processor (605) coupled to an internal data bus (645). An external bus circuit (620) is coupled to the internal (645) and external data busses (640). The bus interface circuit (620) is configured to receive read and write signals for data request data, and then transmits a wait signal until data from the external periphera is available on the internal data bus (645), which indicates the external (640) and internal data busses (645) are unavailable. After the processor (605) receives or transmits the data, the bus interface circuit (620) stops transmitting the wait signal and transmits a busy signal, which indicates the internal data bus (645) is available and the external data bus (640) is unavailable.
摘要翻译：本发明包括用于减少集成电路中的非活动时段的系统。集成电路（600）通过外部数据总线（640）耦合到外部外围设备。集成电路（600）具有耦合到内部数据总线（645）的处理器（605）。外部总线电路（620）耦合到内部（645）和外部数据总线（640）。总线接口电路（620）被配置为接收用于数据请求数据的读取和写入信号，然后发送等待信号，直到来自外部周边的数据在内部数据总线（645）上可用，其指示外部（640）和内部数据总线（645）不可用。在处理器（605）接收或发送数据之后，总线接口电路（620）停止发送等待信号并发送指示内部数据总线（645）可用的忙信号，并且外部数据总线（640）是不可用。

2. 发明申请

WO2006103563A8 METHOD AND APPARATUS FOR REDUCING SYSTEM INACTIVITY DURING TIME DATA FLOAT DELAY AND EXTERNAL MEMORY WRITE 审中-公开
标题翻译：在数据流延迟和外部存储器写入期间减少系统不活动的方法和装置
公开(公告)号：WO2006103563A8
公开(公告)日：2009-09-11
申请号：PCT/IB2006000957
申请日：2006-03-24
申请人： ATMEL CORP , MATULIK ERIC , RESCANIERES NICOLAS , LAFAGE ANNE
发明人： MATULIK ERIC , RESCANIERES NICOLAS , LAFAGE ANNE
IPC分类号： G06F13/00 , G06F3/00
CPC分类号： G06F13/405 , G06F13/4243
摘要： The invention comprises a system for reducing inactive periods in an integrated circuit. The integrated circuit (600) is coupled to an external peripheral by an external data bus (640). The integrated circuit (600) has a processor (605) coupled to an internal data bus (645). An external bus circuit (620) is coupled to the internal (645) and external data busses (640). The bus interface circuit (620) is configured to receive read and write signals for data request data, and then transmits a wait signal until data from the external periphera is available on the internal data bus (645), which indicates the external (640) and internal data busses (645) are unavailable. After the processor (605) receives or transmits the data, the bus interface circuit (620) stops transmitting the wait signal and transmits a busy signal, which indicates the internal data bus (645) is available and the external data bus (640) is unavailable.
摘要翻译：本发明包括用于减少集成电路中的非活动时段的系统。集成电路（600）通过外部数据总线（640）耦合到外部外围设备。集成电路（600）具有耦合到内部数据总线（645）的处理器（605）。外部总线电路（620）耦合到内部（645）和外部数据总线（640）。总线接口电路（620）被配置为接收用于数据请求数据的读取和写入信号，然后发送等待信号，直到来自外部周边的数据在内部数据总线（645）上可用，其指示外部（640）和内部数据总线（645）不可用。在处理器（605）接收或发送数据之后，总线接口电路（620）停止发送等待信号并发送指示内部数据总线（645）可用的忙信号，并且外部数据总线（640）是不可用。

3. 发明申请

WO2006103563A2 METHOD AND APPARATUS FOR REDUCING SYSTEM INACTIVITY DURING TIME DATA FLOAT DELAY AND EXTERNAL MEMORY WRITE 审中-公开
标题翻译：在数据流延迟和外部存储器写入期间减少系统不活动的方法和装置
公开(公告)号：WO2006103563A2
公开(公告)日：2006-10-05
申请号：PCT/IB2006/000957
申请日：2006-03-24
申请人： ATMEL CORPORATION , MATULIK, Eric , RESCANIERES, Nicolas , LAFAGE, Anne
发明人： MATULIK, Eric , RESCANIERES, Nicolas , LAFAGE, Anne
IPC分类号： G06F3/00 , G06F13/00
CPC分类号： G06F13/405 , G06F13/4243
摘要： The invention comprises a system for reducing inactive periods in an integrated circuit. The integrated circuit is coupled to an external peripheral by an external data bus. The integrated circuit has a processor coupled to an internal data bus. The system comprises the following. An external bus circuit is coupled to the internal and external data busses. The bus interface circuit is configured to receive read and write signals for data request data. In response, the bus interfaces circuit transmits a wait signal until data from the external peripheral is available on the internal data bus. The wait signal indicates that the external and internal data busses are not available for other purposes. After the processor has received or transmits the data, the bus interface circuit stops transmitting the wait signal and transmits a busy signal. The busy signal indicates that the internal data bus is available and the external data bus is not available for other purposes.
摘要翻译：本发明包括用于减少集成电路中的非活动时段的系统。集成电路通过外部数据总线耦合到外部外围设备。集成电路具有耦合到内部数据总线的处理器。该系统包括以下。外部总线电路耦合到内部和外部数据总线。总线接口电路被配置为接收用于数据请求数据的读取和写入信号。作为响应，总线接口电路发送等待信号，直到来自外部外围设备的数据在内部数据总线上可用。等待信号表示外部和内部数据总线不可用于其他目的。处理器接收或发送数据后，总线接口电路停止发送等待信号并发送忙信号。忙信号表示内部数据总线可用，外部数据总线不可用于其他目的。

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