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1. 发明公开

US20240111489A1 BIGNUM ADDITION AND/OR SUBTRACTION WITH CARRY PROPAGATION 审中-公开
公开(公告)号：US20240111489A1
公开(公告)日：2024-04-04
申请号：US17955634
申请日：2022-09-29
申请人： ADVANCED MICRO DEVICES, INC.
发明人： Onur Kayiran , Michael Estlick , Masab Ahmad , Gabriel H. Loh
IPC分类号： G06F7/498 , G06F7/506
CPC分类号： G06F7/4981 , G06F7/506
摘要： A processing unit includes a plurality of adders and a plurality of carry bit generation circuits. The plurality of adders add first and second X bit binary portion values of a first Y bit binary value and a second Y bit binary value. Y is a multiple of X. The plurality of adders further generate first carry bits. The plurality of carry bit generation circuits is coupled to the plurality of adders, respectively, and receive the first carry bits. The plurality of carry bit generation circuits generate second carry bits based on the first carry bits. The plurality of adders use the second carry bits to add the first and second X bit binary portions of the first and second Y bit binary values, respectively.

2. 发明授权

US11768663B1 Compaction of multiplier and adder circuits 有权
公开(公告)号：US11768663B1
公开(公告)日：2023-09-26
申请号：US17014410
申请日：2020-09-08
申请人： Xilinx, Inc.
发明人： Srijan Tiwary , Aman Gayasen
IPC分类号： G06F7/506 , G06F30/327 , G06F30/34 , G06F7/533 , G06F7/57
CPC分类号： G06F7/5334 , G06F7/506 , G06F7/57 , G06F30/327 , G06F30/34
摘要： Approaches for logic compaction include inputting an optimization directive that specifies one of area optimization or speed optimization to a synthesis tool executing on a computer processor. The synthesis tool identifies a multiplier and/or an adder specified in a circuit design and synthesizing the multiplier into logic having LUT-to-LUT connections between LUTs on separate slices of a programmable integrated circuit (IC) in response to the optimization directive specifying speed optimization. The synthesis tool synthesizes the multiplier and/or adder into logic having LUT-carry connections between LUTs and carry logic within a single slice of the programmable IC in response to the optimization directive specifying area optimization. The method includes implementing a circuit on the programmable IC from the logic having LUT-carry connections in response to the optimization directive specifying area optimization.

3. 发明申请

US20220253282A1 NEW LOW POWER ADDER TREE STRUCTURE 有权
公开(公告)号：US20220253282A1
公开(公告)日：2022-08-11
申请号：US17532632
申请日：2021-11-22
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Chia-Fu Lee , Po-Hao Lee , Yi-Chun Shih , Yu-Der Chih
IPC分类号： G06F7/501 , G06F7/506 , H03K19/0185 , H03K19/21
摘要： In some aspects of the present disclosure, an adder tree circuit is disclosed. In some aspects, the adder tree circuit includes a plurality of full adders (FAs) including: a first subgroup of FAs, wherein each FA of the first subgroup includes a first number of transistors; and a second subgroup of FAs, wherein each FA of the second subgroup includes a second number of transistors, the first number being greater than the second number; wherein each FA of the first subgroup receives a first input from a first one of the second subgroup of FAs and a second input from a second one of the second subgroup of FAs, and each FA provides a first output to a third one of the second subgroup of FAs and a second output to a fourth one of the second subgroup of FAs.

4. 发明授权

US11010133B2 Parallel-prefix adder and method 有权
公开(公告)号：US11010133B2
公开(公告)日：2021-05-18
申请号：US16921603
申请日：2020-07-06
申请人： Ranjan B. Lokappa , Igor Arsovski
发明人： Ranjan B. Lokappa , Igor Arsovski
IPC分类号： G06F7/506
摘要： An adder includes a primary carry bit generation circuit and a summing circuit. The primary carry bit generation circuit is configured to generate first carry bits for a first number of pairs of bits from first and second operands, and to generate second carry bits for a second number of pairs of bits from the first and second operands. The second number of pairs being different than the first number of pairs. The summing circuit is configured to generate first sums by adding bits of pairs from the first and second number of pairs and the first and second carry bits. The summing circuit is configured to generate second sums by adding bits of other pairs of the bits from first and second operands than the pairs in the first and second number of pairs and additional carry bits generated when adding the bits of the other pairs.

5. 发明授权

US10768897B2 Arithmetic logic unit for single-cycle fusion operations 有权
公开(公告)号：US10768897B2
公开(公告)日：2020-09-08
申请号：US16577736
申请日：2019-09-20
申请人： International Business Machines Corporation
发明人： Maarten J. Boersma , Niels Fricke
IPC分类号： G06F7/57 , G06F7/506
摘要： An arithmetic logic unit is disclosed that includes a first logical circuit that generates a first partial sum result from three operands in a first stage of a single clock cycle of a processor; a second circuit that generates a second partial result in the same first stage of the clock cycle of the processor; and an adder that receives the first partial result from the first logical circuit and the second partial result from the second circuit and generates a secondary result during a second stage of the single clock cycle of the processor. The arithmetic logic unit may optionally further include a backend circuit that performs additional arithmetic and logic functions in the same single clock cycle of the processor.

6. 发明授权

US10545727B2 Arithmetic logic unit for single-cycle fusion operations 有权
公开(公告)号：US10545727B2
公开(公告)日：2020-01-28
申请号：US15864371
申请日：2018-01-08
申请人： International Business Machines Corporation
发明人： Maarten J. Boersma , Niels Fricke
IPC分类号： G06F7/57 , G06F7/506
摘要： An arithmetic logic unit is disclosed that includes a first logical circuit that generates a first partial sum result from three operands in a first stage of a single clock cycle of a processor; a second circuit that generates a second partial result in the same first stage of the clock cycle of the processor; and an adder that receives the first partial result from the first logical circuit and the second partial result from the second circuit and generates a secondary result during a second stage of the single clock cycle of the processor. The arithmetic logic unit may optionally further include a backend circuit that performs additional arithmetic and logic functions in the same single clock cycle of the processor.

7. 发明授权

US09916130B2 Apparatus and method for vector processing 有权
公开(公告)号：US09916130B2
公开(公告)日：2018-03-13
申请号：US14564708
申请日：2014-12-09
申请人： ARM LIMITED
发明人： David Raymond Lutz , Neil Burgess
IPC分类号： G06F7/483 , G06F7/499 , G06F9/30 , G06F17/16 , H03M7/12 , H03M7/24 , G06F11/34 , G06F11/36 , G06F5/01 , G06F7/38 , G06F7/48 , G06F7/507 , G06F9/38 , G06F7/506
CPC分类号： G06F7/483 , G06F5/012 , G06F7/38 , G06F7/48 , G06F7/4991 , G06F7/49915 , G06F7/49921 , G06F7/49942 , G06F7/506 , G06F7/507 , G06F9/3001 , G06F9/30014 , G06F9/30018 , G06F9/30025 , G06F9/30036 , G06F9/30112 , G06F9/3016 , G06F9/30185 , G06F9/30192 , G06F9/3885 , G06F11/3404 , G06F11/3476 , G06F11/348 , G06F11/3636 , G06F11/3644 , G06F11/3648 , G06F17/16 , G06F2201/865 , G06F2207/483 , H03M7/12 , H03M7/24
摘要： An apparatus comprises processing circuitry for performing, in response to a vector instruction, a plurality of lanes of processing or respective data elements with at least one operand vector to generate corresponding result data elements of a result vector. The processing circuitry may support performing at least two of the lanes of processing with different rounding modes for generating rounding values for the corresponding result data elements of the result vector. This allows two or more calculations with different rounding modes to be executed in response to a single instruction, to improve performance.

8. 发明授权

US09703529B2 Exception generation when generating a result value with programmable bit significance 有权
公开(公告)号：US09703529B2
公开(公告)日：2017-07-11
申请号：US14582978
申请日：2014-12-24
申请人： ARM Limited
发明人： David Raymond Lutz , Neil Burgess , Christopher Neal Hinds
IPC分类号： G06F7/499 , G06F7/483 , G06F9/30 , G06F17/16 , H03M7/12 , H03M7/24 , G06F11/34 , G06F11/36 , G06F5/01 , G06F7/38 , G06F7/48 , G06F7/507 , G06F9/38 , G06F7/506
CPC分类号： G06F7/483 , G06F5/012 , G06F7/38 , G06F7/48 , G06F7/4991 , G06F7/49915 , G06F7/49921 , G06F7/49942 , G06F7/506 , G06F7/507 , G06F9/3001 , G06F9/30014 , G06F9/30018 , G06F9/30025 , G06F9/30036 , G06F9/30112 , G06F9/3016 , G06F9/30185 , G06F9/30192 , G06F9/3885 , G06F11/3404 , G06F11/3476 , G06F11/348 , G06F11/3636 , G06F11/3644 , G06F11/3648 , G06F17/16 , G06F2201/865 , G06F2207/483 , H03M7/12 , H03M7/24
摘要： A data processing system performs processing operations upon input operand(s) having a programmable bit significance. Exception generating circuitry generates exception indications representing exceptions such as overflow, underflow and inexact in respect of a result value having the programmable bit significance.

9. 发明授权

US09448767B2 Three-term predictive adder and/or subtracter 有权
标题翻译：三项预测加法器和/或减法器
公开(公告)号：US09448767B2
公开(公告)日：2016-09-20
申请号：US14192102
申请日：2014-02-27
申请人： Texas Instruments Incorporated
发明人： Timothy D. Anderson , Mujibur Rahman , Kai Chirca
IPC分类号： G06F7/50 , G06F7/57 , G06F7/505 , G06F7/506
CPC分类号： G06F7/57 , G06F7/5055 , G06F7/506
摘要： A predictive adder produces the result of incrementing and/or decrementing a sum of A and B by a one-bit constant of the form of the form 2k, where k is a bit position at which the sum is to be incremented or decremented. The predictive adder predicts the ripple portion of bits in the potential sum of the first operand A and the second operand B that would be toggled by incrementing or decrementing the sum A+B by the one-bit constant to generate and indication of the ripple portion of bits in the potential sum. The predictive adder uses the indication of the ripple portion of bits in the potential sum and the carry output generated by evaluating A+B to produce the results of at least one of A+B+2k and A+B−2k.
摘要翻译：预测加法器产生将形式为2k的1比特常数递增和/或递减A和B的和的结果，其中k是要递增或递减的比特位置。预测加法器预测第一操作数A和第二操作数B的电位之和的纹波部分，该第一操作数A和第二操作数B将通过将和A + B递增或递减1比特常数来切换，以产生和指示纹波部分的位数在电位和。预测加法器使用电位和中的波纹部分的指示和通过评估A + B产生的进位输出来产生A + B + 2k和A + B-2k中的至少一个的结果。

10. 发明申请

US20150137851A1 Configurable IC's With Large Carry Chains 有权
标题翻译：可配置IC与大携带链
公开(公告)号：US20150137851A1
公开(公告)日：2015-05-21
申请号：US14311359
申请日：2014-06-23
申请人： Tabula, Inc.
发明人： Herman Schmit , Jason Redgrave
IPC分类号： G06F7/506 , H03K19/173
CPC分类号： G06F7/506 , G06F2207/3868 , H03K19/173
摘要： Some embodiments provide a configurable IC that includes several configurable logic circuits, where the logic circuits include several sets of associated configurable logic circuits. For each several sets of associated configurable logic circuits, the reconfigurable IC also includes a carry circuit for performing up to N carry operations sequentially, wherein N is greater than two.
摘要翻译：一些实施例提供了包括若干可配置逻辑电路的可配置IC，其中逻辑电路包括若干组相关联的可配置逻辑电路。对于每组几组相关联的可配置逻辑电路，可重新配置的IC还包括一个执行多达N个进位操作的进位电路，其中N大于2。

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