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1. 发明授权

US06828514B2 High speed circuit board and method for fabrication 失效
标题翻译：高速电路板及其制造方法
公开(公告)号：US06828514B2
公开(公告)日：2004-12-07
申请号：US10354000
申请日：2003-01-30
申请人： Benson Chan , John M. Lauffer , How T. Lin , Voya R. Markovich , David L. Thomas
发明人： Benson Chan , John M. Lauffer , How T. Lin , Voya R. Markovich , David L. Thomas
IPC分类号： H05K706
CPC分类号： H05K3/4688 , H01L23/3128 , H01L23/5383 , H01L25/0652 , H01L25/0655 , H01L25/18 , H01L2224/16 , H01L2224/73253 , H01L2924/00014 , H01L2924/01019 , H01L2924/01046 , H01L2924/01057 , H01L2924/01078 , H01L2924/01079 , H01L2924/12044 , H01L2924/14 , H01L2924/1433 , H01L2924/15311 , H01L2924/16195 , H01L2924/3011 , H01L2924/3025 , H05K1/024 , H05K1/113 , H05K3/4623 , H05K2201/09536 , H05K2201/096 , H05K2203/061 , Y10T29/49126 , Y10T29/49165 , H01L2224/0401
摘要： A multilayered PCB including two multilayered portions, one of these able to electrically connect electronic components mounted on the PCB to assure high frequency connections therebetween. The PCB further includes a conventional PCB portion to reduce costs while assuring a structure having a satisfactory overall thickness for use in the PCB field. Coupling is also possible to the internal portion from these components. Methods of making these structures have also been provided.
摘要翻译：包括两个多层部分的多层PCB，其中之一能够电连接安装在PCB上的电子部件，以确保其间的高频连接。 PCB还包括常规PCB部分以降低成本，同时确保具有令人满意的整体厚度的结构以用于PCB领域。这些组件的内部部分也可以进行耦合。也提供了制造这些结构的方法。

2. 发明授权

US06762368B2 Reducing inductance of a capacitor 有权
标题翻译：降低电容的电感
公开(公告)号：US06762368B2
公开(公告)日：2004-07-13
申请号：US09905474
申请日：2001-07-13
申请人： Stephanus D. Saputro , Lan Zhang
发明人： Stephanus D. Saputro , Lan Zhang
IPC分类号： H05K706
CPC分类号： H05K1/113 , G06F1/189 , H05K1/0231 , H05K1/0298 , H05K1/114 , H05K1/115 , H05K2201/0979 , H05K2201/10636 , Y02P70/611
摘要： The inductance of the capacitor is reduced by connecting the capacitor directly to a via. In one embodiment inductance of a capacitor is reduced by a plurality of via, the number of via greater than the number of electrical couplings from the voltage pad to the voltage plane. In one embodiment the capacitor has a ground pad of a minimum size. In another embodiment the capacitor is electrically coupled to a trace having a length reduced to minimize inductance.
摘要翻译：通过将电容器直接连接到通孔来减小电容器的电感。在一个实施例中，电容器的电感被多个通孔减少，通孔的数量大于从电压焊盘到电压平面的电耦合的数量。在一个实施例中，电容器具有最小尺寸的接地焊盘。在另一个实施例中，电容器电耦合到具有减小的长度的迹线以最小化电感。

3. 发明授权

US06707681B2 Surface mount typed electronic circuit of small size capable of obtaining a high-Q 失效
标题翻译：表面贴装小型电子电路，可获得高Q值
公开(公告)号：US06707681B2
公开(公告)日：2004-03-16
申请号：US10346324
申请日：2003-01-17
申请人： Takeo Suzuki , Shigeru Osada
发明人： Takeo Suzuki , Shigeru Osada
IPC分类号： H05K706
CPC分类号： H01L23/66 , H01F27/292 , H01F27/40 , H01L25/0657 , H01L2224/16 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06565 , H01L2924/15192 , H01L2924/15313
摘要： In the surface mount typed electronic circuit of the invention, an insulating substrate has an inductance element formed in a conductive pattern whose end portions are connected to the second lands. A bare chip is superimposed on the insulating substrate, so as to respectively connect the first electrodes and the second electrodes to the first lands and the second lands. Therefore, since the inductance element is positioned below the bare chip, the length of the connecting conductor between the inductance element and the semiconductor circuit can be extremely shortened, and a high-Q electronic circuit, especially in high-frequency, can be provided.
摘要翻译：在本发明的表面贴装型电子电路中，绝缘基板具有以导电图案形成的电感元件，其端部连接到第二焊盘。裸芯片叠加在绝缘基板上，以将第一电极和第二电极分别连接到第一焊盘和第二焊盘。因此，由于电感元件位于裸芯片的下方，电感元件和半导体电路之间的连接导体的长度可以极大地缩短，并且可以提供特别是高频的高Q电子电路。

4. 发明授权

US06492598B1 Printed circuit board assembly and method for making a printed circuit board assembly 失效
标题翻译：印刷电路板组装件和制造印刷电路板组件的方法
公开(公告)号：US06492598B1
公开(公告)日：2002-12-10
申请号：US08565090
申请日：1995-11-30
申请人： Dean A. Klein
发明人： Dean A. Klein
IPC分类号： H05K706
CPC分类号： H05K3/225 , H05K3/222 , H05K3/321 , H05K3/341 , H05K3/3452 , H05K13/06 , H05K2201/0989 , H05K2201/10287 , H05K2203/175 , Y10T29/49144 , Y10T29/49728 , Y10T29/4981
摘要： A PCB assembly which allows economical and reliable rework. The PCB assembly contains a soldermask and a trace with a portion of the trace exposed by a soldermask relief. When one needs to rework the PCB assembly, one bonds a rework wire, using conventional intermetalic bonding materials, to the portion of the trace exposed by the soldermask relief. There is no need to bond a rework wire to a component. Further, there is no need to scrape off the soldermask and possibly damage the traces and/or vias. The bonds are high reliability bonds, and the labor required to perform such bonds are minimal.
摘要翻译： PCB组件，允许经济可靠的返工。 PCB组件包含焊接掩模和痕迹，其中痕迹的一部分由焊接掩模释放。当需要重新组装PCB组件时，使用常规的金属间粘合材料将返修线与焊接掩模露出的部分迹线相连。没有必要将返工线连接到组件。此外，不需要刮掉焊接掩模并且可能损坏迹线和/或通孔。这些债券是高可靠性债券，执行这种债券所需的劳动力是最小的。

5. 发明授权

US06437990B1 Multi-chip ball grid array IC packages 有权
标题翻译：多芯片球栅阵列IC封装
公开(公告)号：US06437990B1
公开(公告)日：2002-08-20
申请号：US09528882
申请日：2000-03-20
申请人： Yinon Degani , Thomas Dixon Dudderar , King Lien Tai
发明人： Yinon Degani , Thomas Dixon Dudderar , King Lien Tai
IPC分类号： H05K706
CPC分类号： H01L25/0655 , H01L23/49816 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/81 , H01L24/85 , H01L25/18 , H01L2224/05554 , H01L2224/05568 , H01L2224/05573 , H01L2224/16225 , H01L2224/16227 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/4943 , H01L2224/73253 , H01L2224/8121 , H01L2224/81815 , H01L2224/85 , H01L2924/01013 , H01L2924/01014 , H01L2924/01028 , H01L2924/01079 , H01L2924/10253 , H01L2924/14 , H01L2924/15311 , H01L2924/1532 , H05K1/141 , H05K3/3436 , H01L2924/00014 , H01L2924/00
摘要： The specification describes a high density IC BGA package in which one or more IC chips are wire bonded to a BGA substrate in a conventional fashion and the BGA substrate is solder ball bonded to a printed wiring board. The standoff between the BGA substrate and the printed wiring board to which it is attached provides a BGA gap which, according to the invention, accommodates one or more IC chips flip-chip bonded to the underside of the BGA substrate. The recognition that state of the art IC chips, especially chips that are thinned, can easily fit into the BGA gap makes practical this efficient use of the BGA gap. The approach of the invention also marries wire bond technology with high packing density flip-chip assembly to produce a low cost, high reliability, state of the art IC package.
摘要翻译：该说明书描述了一种高密度IC BGA封装，其中一个或多个IC芯片以常规方式引线接合到BGA衬底，并且BGA衬底焊接到印刷线路板上。 BGA衬底与其所附接的印刷电路板之间的间隔提供了一个BGA间隙，根据本发明，它可以容纳一个或多个倒装芯片，其结合到BGA衬底的底面。认识到现有技术的IC芯片，特别是薄型的芯片，可以很容易地适应BGA间隙，实际上可以有效地利用BGA间隙。本发明的方法还将引线键合技术与高封装密度倒装芯片组合结合，以产生低成本，高可靠性，最先进的IC封装。

6. 发明授权

US06430054B1 Electrical junction box 有权
标题翻译：电接线盒
公开(公告)号：US06430054B1
公开(公告)日：2002-08-06
申请号：US09392224
申请日：1999-09-09
申请人： Yoshifumi Iwata
发明人： Yoshifumi Iwata
IPC分类号： H05K706
CPC分类号： H05K7/026 , H05K1/144 , H05K3/202
摘要： The electrical junction box has a case, which accommodates a printed circuit board provided in a lower side of the case. The case also receives an electrical wiring circuit and a busbar circuit disposed in an upper side of the case so as to be parallel to the printed circuit board. Wiring harness connectors are mounted on a side wall of the case, and relay connectors are positioned on the side wall or another side wall of the case. The side walls are perpendicular to the printed circuit board. The wiring harness connectors are connected to inner circuits including the printed circuit, the busbar circuit, and the electrical wiring circuit. The case has a top cover, a bottom cover, and a horizontal intermediate partition. The intermediate partition is provided with the electrical wire circuit on an under surface of the partition so as to be opposed to the printed circuit. The upper surface of the intermediate partition is provided with the busbar circuit.
摘要翻译：电接线盒具有壳体，其容纳设置在壳体的下侧的印刷电路板。该壳体还接收布置在壳体的上侧的电布线电路和母线电路，以平行于印刷电路板。线束连接器安装在壳体的侧壁上，并且中继连接器位于壳体的侧壁或另一侧壁上。侧壁垂直于印刷电路板。线束连接器连接到包括印刷电路，母线电路和电布线电路的内部电路。外壳具有顶盖，底盖和水平中间隔板。中间隔板在分隔件的下表面上设置有电线电路，以与印刷电路相对。中间隔板的上表面设有母线电路。

7. 发明授权

US06288905B1 Contact module, as for a smart card, and method for making same 失效
标题翻译：接触模块，智能卡以及制作方法
公开(公告)号：US06288905B1
公开(公告)日：2001-09-11
申请号：US09412052
申请日：1999-10-04
申请人： Kevin Kwong-Tai Chung
发明人： Kevin Kwong-Tai Chung
IPC分类号： H05K706
CPC分类号： B32B37/203 , B32B3/08 , B32B7/12 , B32B33/00 , B32B2425/00 , B32B2429/00 , B32B2519/02 , G06K19/07743 , G06K19/07745 , G06K19/07747 , H01L23/055 , H01L23/49838 , H01L23/4985 , H01L23/49855 , H01L23/5387 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/97 , H01L2224/05571 , H01L2224/05573 , H01L2224/05611 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05655 , H01L2224/05664 , H01L2224/16225 , H01L2224/16237 , H01L2224/32225 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/73253 , H01L2224/73265 , H01L2224/97 , H01L2225/0651 , H01L2225/06517 , H01L2225/0652 , H01L2225/06527 , H01L2225/06541 , H01L2225/06572 , H01L2225/06579 , H01L2225/06582 , H01L2225/06586 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01021 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01057 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/07802 , H01L2924/14 , H01L2924/15174 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01Q1/22 , H01Q1/2225 , H01Q1/36 , H01Q1/38 , H01Q7/00 , H01Q7/005 , H01Q23/00 , H05K1/0393 , H05K1/113 , H05K1/165 , H05K3/4069 , H05K3/423 , H05K2201/0355 , H05K2201/0394 , H05K2201/10674 , H05K2203/1453 , Y10T29/49126 , Y10T29/4913 , Y10T29/49146 , H01L2924/00014 , H01L2924/00012 , H01L2924/00 , H01L2924/013
摘要： A module, such as a contact module for embedding an electronic device into a credit card, smart card, identification tag or other article, comprise a pattern of metal contacts having a first and a second surface and electrically-conductive vias built up on the first surface of the metal contacts. A layer of dielectric adhesive on the first surface of the pattern of metal contacts surrounds the electrically-conductive vias except the ends thereof distal from the metal contacts. An electronic device has electrical contacts connected to the exposed ends of the conductive vias, as by wire bonds or by flip-chip type connections. The module is preferably made by forming a pattern of conductive vias on the first surface of a sheet of electrical contact material, the pattern of vias corresponding to the pattern of contacts of an electronic device; applying dielectric adhesive on the first surface of the sheet of electrical material except in locations corresponding to the vias; patterning the sheet of electrical material to define a pattern of electrical contacts thereon, wherein ones of the electrical contacts are associated with at least corresponding ones of the vias; and attaching the electronic device with the contacts of the electronic device electrically connected to corresponding vias.
摘要翻译：诸如用于将电子设备嵌入到信用卡，智能卡，识别标签或其它物品中的接触模块的模块包括具有第一和第二表面的金属触点图案以及在第一和第二表面上建立的导电通孔金属触点表面。在金属触点图案的第一表面上的介电粘合剂层围绕导电通孔，除了远离金属触点的端部。电子设备具有通过引线键合或通过倒装芯片型连接而连接到导电通孔的暴露端的电触点。模块优选地通过在电接触材料片的第一表面上形成导电通孔的图案来形成，通孔图案对应于电子器件的触点图案; 在电气材料片的第一表面上施加电介质粘合剂，除了对应于通孔的位置; 图案化电气材料片以限定其上的电触点的图案，其中电触点中的一个与至少相应的通孔相关联; 以及将所述电子设备与所述电子设备的触点相连接，以电连接到相应的通孔。

8. 发明授权

US06833513B1 Crosstalk reduction in a PWB connector footprint 有权
标题翻译： PWB连接器占用空间中的串扰减少
公开(公告)号：US06833513B1
公开(公告)日：2004-12-21
申请号：US10279191
申请日：2002-10-22
申请人： Bilal Ahmad
发明人： Bilal Ahmad
IPC分类号： H05K706
CPC分类号： H05K1/0219 , H05K1/116 , H05K3/429 , H05K2201/09618 , H05K2201/10189 , H05K2201/10704
摘要： A modified connector footprint on a PWB includes a row of ground vias disposed outside a standard connector footprint that do not mate to pins in the connector. The extra ground vias provide additional shielding and reduce cross-talk in the connector/PWB interface.
摘要翻译： PWB上的改进的连接器占用面积包括一排布置在不与连接器中的引脚匹配的标准连接器覆盖区之外的接地通孔。额外的接地通孔在连接器/ PWB接口中提供额外的屏蔽和减少串扰。

9. 发明授权

US06743985B1 Method and apparatus for increased routing density on printed circuit boards with differential pairs 有权
标题翻译：用于增加具有差分对的印刷电路板上布线密度的方法和装置
公开(公告)号：US06743985B1
公开(公告)日：2004-06-01
申请号：US10370164
申请日：2003-02-19
申请人： Michael C. Greim , Patrick W. Carrier
发明人： Michael C. Greim , Patrick W. Carrier
IPC分类号： H05K706
CPC分类号： H05K1/0216 , H05K1/0219 , H05K2201/09236 , H05K2201/09254
摘要： A method and apparatus for decreasing crosstalk between conductors, particularly differential pairs, that are routed in high-density patterns on printed circuit boards system. In one embodiment of the invention, a single-ended conductor is divided at a first point into two single-ended conductors of equal width, with the two single-ended conductors being routed around and alongside a differential pair of conductors. Equal and opposite noise is coupled onto each branch of the single-ended signal from each side of the differential pair. The two single-ended conductors are rejoined at a second point to form a combined single-ended conductor. Signals traveling along the two separate paths of the single-ended are combined at the second point and noise carried in the respective signals is cancelled. Noise coupled into the differential pair from the two single-ended paths is eliminated at the receiving end as common mode noise. In other embodiments of the present invention, the single-ended conductors and the differential pairs are oriented between two planes in stripline or dual stripline configurations. The method and apparatus of the present invention can be implemented in numerous media, such as vias and cables (including flex and ribbon).
摘要翻译：一种减少在印刷电路板系统上以高密度图案布线的导体之间的串扰的方法和装置，特别是差分对。在本发明的一个实施例中，单端导体在第一点被分成两个相等宽度的单端导体，两个单端导体绕差分对导体路由。相等和相反的噪声从差分对的每一侧耦合到单端信号的每个分支上。两个单端导体在第二个点处重新连接以形成组合的单端导体。在第二点处组合沿着单端两个独立路径行进的信号，并取消相应信号中携带的噪声。耦合到两个单端路径的差分对的噪声在接收端被消除为共模噪声。在本发明的其它实施例中，单端导体和差分对在带状线或双带状线构造的两个平面之间取向。本发明的方法和装置可以在许多介质中实现，例如通孔和电缆（包括柔性和带状物）。

10. 发明授权

US06740819B2 Printed wiring board 有权
标题翻译：印刷电路板
公开(公告)号：US06740819B2
公开(公告)日：2004-05-25
申请号：US10421272
申请日：2003-04-23
申请人： Anilkumar C. Bhatt , Ashwinkumar C. Bhatt , Subahu D. Desai , John M. Lauffer , Voya R. Markovich , Thomas R. Miller
发明人： Anilkumar C. Bhatt , Ashwinkumar C. Bhatt , Subahu D. Desai , John M. Lauffer , Voya R. Markovich , Thomas R. Miller
IPC分类号： H05K706
CPC分类号： H05K3/445 , H05K1/056 , H05K3/0023 , H05K3/0082 , H05K3/4641 , H05K2203/143
摘要： Via holes are formed in an electrically conductive power plane. Photo-imageable dielectric (PID) material is applied to one side of the power plane filling the via holes. The power plane side with no PID material is exposed to light energy to cure the PID material in the via holes. A developer is used to remove any uncured PID material. Signal plane assemblies comprising a conductive signal plane and a dielectric layer are laminated onto the filled power plane forming a two signal and one power plane (2S1P) structure. In another embodiment, the power plane has PID material applied from both sides. A photo-mask is applied to the power plane and the PID material in the via holes is cured with light energy. A developer is used to remove uncured PID material. Signal plane assemblies, as described above, are laminated onto the filled power plane forming a 2S1P structure.
摘要翻译：通孔形成在导电电力平面中。可光成像电介质（PID）材料被施加到填充通孔的电源平面的一侧。没有PID材料的电源平面侧暴露于光能以固化通孔中的PID材料。开发人员用于去除任何未固化的PID材料。包括导电信号平面和电介质层的信号平面组件层压到形成两个信号和一个功率平面（2S1P）结构的填充的电源平面上。在另一实施例中，动力平面具有从两侧施加的PID材料。将光掩模应用于电源平面，通孔中的PID材料用光能固化。开发人员用于清除未固化的PID材料。如上所述的信号平面组件被层压到形成2S1P结构的填充的电源平面上。

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