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    • 1. 发明授权
    • Information reproducer
    • 信息再现器
    • US4884150A
    • 1989-11-28
    • US145956
    • 1988-01-20
    • Masao Kanda
    • Masao Kanda
    • H04N5/93G11B20/02H04N5/937H04N5/953H04N5/956
    • H04N5/956H04N5/937
    • A video signal reproducing system including a still picture reproduction function is provided with correction circuitry for preventing the line jitter problem which often occurs in conventional units. A memory circuit is provided which has a capacity of at least one field, and receives a video input via a variable delay circuit. The output is derived, in alternate fields, from the memory circuit or a correction circuit. In one embodiment, the correction circuit may deliver a line interpolated signal derived by averaging the memory output signal and a 1-H delayed signal from the memory circuit.
    • 包括静止图像再现功能的视频信号再现系统设置有用于防止常规单元中经常发生的线路抖动问题的校正电路。 提供了具有至少一个场的容量并且经由可变延迟电路接收视频输入的存储器电路。 输出在交替字段中从存储器电路或校正电路导出。 在一个实施例中,校正电路可以传递通过对存储器输出信号进行平均而得到的线内插信号和来自存储器电路的1-H延迟信号。
    • 5. 发明授权
    • Apparatus for modifying the time base of signals
    • 用于修改信号时基的装置
    • US3947874A
    • 1976-03-30
    • US519359
    • 1974-10-29
    • Robert A. Lentz
    • Robert A. Lentz
    • G11B20/02H04N5/953H04N5/795
    • H04N5/953
    • Time base instability of signals in a train thereof is corrected by use of analog shift registers. As employed in the correction of time base instability of video signals, plural analog shift registers are used. The same clock rate is used, respectively, to clock video signals into and out of analog shift registers. The clock rate is set so that samples of a video signal which has a normal duration may load all stages of an analog shift register within the duration of the normal signal. Thus, samples of a stretched signal fully load all stages of the analog shift register, the trailing part of such stretched signal being discarded. Conversely, a video signal which has been compressed, although being fully loaded into the analog shift register, loads less than all of the analog shift register stages.
    • 通过使用模拟移位寄存器校正其列车中的信号的时基不稳定性。 如在视频信号的时基不稳定性的校正中使用的,使用多个模拟移位寄存器。 分别使用相同的时钟频率将视频信号输入和输出模拟移位寄存器。 设置时钟速率使得具有正常持续时间的视频信号的样本可以在正常信号的持续时间内加载模拟移位寄存器的所有级。 因此,拉伸信号的样本完全加载模拟移位寄存器的所有级,这种拉伸信号的尾部被丢弃。 相反,已经被压缩的视频信号尽管被完全加载到模拟移位寄存器中,但是比所有的模拟移位寄存器级加载少。
    • 7. 发明授权
    • Time-base error correction system
    • 时基误差校正系统
    • US3748386A
    • 1973-07-24
    • US3748386D
    • 1972-04-03
    • MONNEY DHERZOG W
    • MONNEY DHERZOG W
    • H04N5/93G11B20/02H03K5/007H04N5/16H04N5/18H04N5/92H04N5/931H04N5/95H04N5/953H04N5/04
    • H04N5/95H04N5/16H04N5/185H04N5/92H04N5/931
    • A time-base error correction system for a video signal employing a plurality of serially connected delay lines. Circuit means are conditioned to detect the closest timing match between a reference synchronizing signal and the video signal as it appears at various points along the delay path and to connect the appropriate delay line point or junction to an output at which the correctly delayed video signal appears. Featured circuitry provides for eliminating the erroneous leading edge of a video synchronizing pulse distorted by changes in the selected delay point and for compensating for variations in d.c. offset of the video signal introduced by differential delay line path effects.
    • 一种采用多个串行连接的延迟线的视频信号的时基误差校正系统。 电路装置被调节为检测参考同步信号和视频信号之间最接近的定时匹配,因为它在沿着延迟路径的不同点处出现,并且将适当的延迟线点或结点连接到出现正确延迟的视频信号的输出端 。 特色电路提供消除视频同步脉冲的错误前沿,通过所选延迟点的变化而变形,并补偿直流电流的变化。 通过差分延迟线路路径效应引入的视频信号的偏移。