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1. 发明授权

US11804841B2 Interface circuit and operating method thereof to compensate for supply voltage variations 有权
公开(公告)号：US11804841B2
公开(公告)日：2023-10-31
申请号：US17569041
申请日：2022-01-05
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Jaemin Choi , Yonghun Kim , Jinhyeok Baek , Yoochang Sung , Changsik Yoo , Jeongdon Ihm
IPC分类号： H03K19/003 , G11C7/22 , G11C5/14 , H03K19/0185 , G11C7/10 , G11C8/06
CPC分类号： H03K19/00384 , G11C5/147 , G11C7/22 , H03K19/018521 , G11C7/1057 , G11C7/1084 , G11C8/06
摘要： An interface circuit includes: a buffer circuit configured to receive an input signal and to generate an output signal having a delay time, the delay time being determined based on a current level of a bias current and a voltage level of a power supply voltage; and a bias generation circuit configured to vary a voltage level of a bias control voltage so that the delay time is constant by compensating for a change in the voltage level of the power supply voltage, the bias generation circuit being further configured to provide the bias control voltage to the buffer circuit.

2. 发明授权

US11714579B2 Nonvolatile memory device supporting high-efficiency I/O interface 有权
公开(公告)号：US11714579B2
公开(公告)日：2023-08-01
申请号：US17828176
申请日：2022-05-31
申请人： Samsung Electronics Co., Ltd.
发明人： Seonkyoo Lee , Jeongdon Ihm , Chiweon Yoon , Byunghoon Jeong
IPC分类号： G06F3/06 , G06F1/06 , G06F13/16 , G11C16/04 , G11C16/10 , G11C16/26
CPC分类号： G06F3/0659 , G06F1/06 , G06F3/0613 , G06F3/0679 , G06F13/1668 , G11C16/0483 , G11C16/10 , G11C16/26
摘要： A nonvolatile memory device includes a first pin that receives a first signal, a second pin that receives a second signal, third pins that receive third signals, a fourth pin that receives a write enable signal, a memory cell array, and a memory interface circuit that obtains a command, an address, and data from the third signals in a first mode and obtains the command and the address from the first signal and the second signal and the data from the third signals in a second mode. In the first mode, the memory interface circuit obtains the command from the third signals and obtains the address from the third signals. In the second mode, the memory interface circuit obtains the command from the first signal and the second signal and obtains the address from the first signal and the second signal.

3. 发明申请

US20230091026A1 SEMICONDUCTOR DEVICE INCLUDING DELAY COMPENSATION CIRCUIT 有权
公开(公告)号：US20230091026A1
公开(公告)日：2023-03-23
申请号：US17994296
申请日：2022-11-26
申请人： Samsung Electronics Co., Ltd.
发明人： Anil Kavala , Seonkyoo Lee , Taesung Lee , Jeongdon Ihm , Byunghoon Jeong
IPC分类号： H03L7/081 , H03L7/085 , H03K5/133 , G11C7/22
摘要： A semiconductor device includes an internal clock generation circuit configured to generate an internal clock; a plurality of unit circuits configured to have a first unit circuit and a second unit circuit operating while being synchronized with an internal clock; a plurality of transfer circuits including a first transfer circuit configured to provide a first transfer path having a first delay time, and a second transfer circuit configured to provide a second transfer path having a second delay time different from the first delay time; and a delay compensation circuit configured to compare a first clock input to the first unit circuit through the first transfer path with a second clock input to the second unit circuit through the second transfer path, and to adjust the second delay time so that the adjusted second delay time matches the first delay time.

4. 发明授权

US10998888B2 Parameter monitoring circuit for detecting error of parameter, duty cycle correction circuit, and impedance calibration circuit 有权
公开(公告)号：US10998888B2
公开(公告)日：2021-05-04
申请号：US16861903
申请日：2020-04-29
申请人： Samsung Electronics Co., Ltd.
发明人： Dongho Shin , Kyungtae Kang , Junha Lee , Tongsung Kim , Jangwoo Lee , Jeongdon Ihm , Byunghoon Jeong
IPC分类号： H03K3/017 , H03K19/21 , H03K5/24
摘要： A parameter monitoring circuit includes a code generation circuit configured to generate a first code, to which a first offset is applied, and a second code, to which a second offset is applied; a parameter adjustment circuit configured to generate a first parameter and a second parameter by respectively applying the first code and the second code to a current parameter; a comparator circuit configured to generate a first comparison result and a second comparison result, the first comparison result indicating a comparison result between the first parameter and a reference parameter value, and the second comparison result indicating a comparison result between the second parameter and the reference parameter value; and a parameter error detection circuit configured to detect an error in the current parameter, based on the first comparison result and the second comparison result.

5. 发明授权

US10262708B2 Memory system performing training operation 有权
公开(公告)号：US10262708B2
公开(公告)日：2019-04-16
申请号：US15825504
申请日：2017-11-29
申请人： Samsung Electronics Co., Ltd.
发明人： Byunghoon Jeong , Jeongdon Ihm
IPC分类号： G11C8/12 , H01L21/822 , G11C16/16 , H01L27/11556 , G11C16/04 , G11C7/22 , G11C29/02 , G11C16/34 , H01L27/06 , H01L21/3213
摘要： A memory system may include a nonvolatile memory device and a controller. The nonvolatile memory device may include a data area and a device information area, the device information area being inaccessible accessed by a host. The controller may be configured to perform the training operation with respect to a data signal transmitted to or received from the nonvolatile memory device based on training information stored in the device information area. The controller may be configured to select one of a first training operation and a second training operation based on an identification code of the training information, and to perform the selected one of the first training operation based on a rooted training code generated by the controller and the second training operation based on a dynamic training code of the training information, the second training operation including performing a fewer number of searches than the first training operation.

6. 发明申请

US20140204676A1 HIGH VOLTAGE SWITCH AND A NONVOLATILE MEMORY DEVICE INCLUDING THE SAME 有权
标题翻译：高电压开关和非易失性存储器件，包括它们
公开(公告)号：US20140204676A1
公开(公告)日：2014-07-24
申请号：US14077769
申请日：2013-11-12
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Taehyun Kim , Youngsun Min , Bilal Ahmad Janjua , Jeongdon Ihm
IPC分类号： G11C16/30
CPC分类号： G11C16/30 , G11C16/0483 , G11C16/12
摘要： A high voltage switch of a nonvolatile memory device includes a depletion type NMOS transistor configured to switch a second driving voltage in response to an output signal of the high voltage switch; at least one inverter configured to convert a voltage of an input signal of the high voltage switch into a first driving voltage or a ground voltage, wherein the first and second driving voltages are received from an external device; and a PMOS transistor configured to transfer the second driving voltage provided to a first terminal of the PMOS transistor from the depletion type NMOS transistor to a second terminal of the PMOS transistor as the output signal in response to an output of the at least one inverter, wherein the output of the at least one inverter is transferred to a gate terminal of the PMOS transistor.
摘要翻译：非易失性存储器件的高电压开关包括耗尽型NMOS晶体管，其配置为响应于高电压开关的输出信号而切换第二驱动电压; 至少一个反相器，被配置为将高压开关的输入信号的电压转换为第一驱动电压或接地电压，其中从外部装置接收第一和第二驱动电压; 以及PMOS晶体管，被配置为响应于所述至少一个反相器的输出，将提供给所述PMOS晶体管的第一端子的所述第二驱动电压从所述耗尽型NMOS晶体管传送到所述PMOS晶体管的第二端子作为所述输出信号，其中所述至少一个反相器的输出被传送到所述PMOS晶体管的栅极端子。

7. 发明授权

US11769537B2 Memory device and memory system including the same 有权
公开(公告)号：US11769537B2
公开(公告)日：2023-09-26
申请号：US18069685
申请日：2022-12-21
申请人： Samsung Electronics Co., Ltd.
发明人： Byunghoon Jeong , Kyungtae Kang , Jangwoo Lee , Jeongdon Ihm
IPC分类号： G11C7/22 , G11C7/10 , H03K19/173 , G11C8/18 , G11C29/42
CPC分类号： G11C7/222 , G11C7/1057 , G11C7/1063 , G11C7/1084 , G11C8/18 , G11C29/42 , H03K19/1737
摘要： A memory device includes a memory cell array configured to store data; and a data output circuit configured to transmit status data to an external device through at least one data line in a latency period in response to a read enable signal received from the external device and transmit the data read from the memory cell array to the external device through the at least one data line in a period subsequent to the latency period.

8. 发明授权

US11550498B2 Storage device and retraining method thereof 有权
公开(公告)号：US11550498B2
公开(公告)日：2023-01-10
申请号：US17030635
申请日：2020-09-24
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Tongsung Kim , Jangwoo Lee , Seonkyoo Lee , Chiweon Yoon , Jeongdon Ihm
IPC分类号： G06F3/06 , G06K9/62
摘要： A storage device includes NVM package and a controller connected to the NVM package through a channel and controlling operation of the NVM package. The NVM package includes an interface chip, first NVM devices connected to the interface chip through a first internal channel and second NVM devices connected to the interface chip through a second internal channel. The interface chip selects the first internal channel in response to an operation request received from the controller and connects the first internal channel to the channel. The interface chip also determines whether retraining is necessary in relation to the second internal channel and transmits a retraining request to the controller when retraining is necessary.

9. 发明授权

US11372593B2 Nonvolatile memory device supporting high-efficiency I/O interface 有权
公开(公告)号：US11372593B2
公开(公告)日：2022-06-28
申请号：US17168620
申请日：2021-02-05
申请人： Samsung Electronics Co., Ltd.
发明人： Seonkyoo Lee , Jeongdon Ihm , Chiweon Yoon , Byunghoon Jeong
IPC分类号： G06F3/06 , G11C16/26 , G06F1/06 , G11C16/04 , G11C16/10 , G06F13/16
摘要： A nonvolatile memory device includes a first pin that receives a first signal, a second pin that receives a second signal, third pins that receive third signals, a fourth pin that receives a write enable signal, a memory cell array, and a memory interface circuit that obtains a command, an address, and data from the third signals in a first mode and obtains the command and the address from the first signal and the second signal and the data from the third signals in a second mode. In the first mode, the memory interface circuit obtains the command from the third signals and obtains the address from the third signals. In the second mode, the memory interface circuit obtains the command from the first signal and the second signal and obtains the address from the first signal and the second signal.

10. 发明申请

US20210320664A1 SEMICONDUCTOR DEVICE INCLUDING DELAY COMPENSATION CIRCUIT 有权
公开(公告)号：US20210320664A1
公开(公告)日：2021-10-14
申请号：US17077891
申请日：2020-10-22
申请人： Samsung Electronics Co., Ltd.
发明人： Anil Kavala , Seonkyoo Lee , Taesung Lee , Jeongdon Ihm , Byunghoon Jeong
IPC分类号： H03L7/081 , G11C7/22 , H03K5/133 , H03L7/085
摘要： A semiconductor device includes an internal clock generation circuit configured to generate an internal clock; a plurality of unit circuits configured to have a first unit circuit and a second unit circuit operating while being synchronized with an internal clock; a plurality of transfer circuits including a first transfer circuit configured to provide a first transfer path having a first delay time, and a second transfer circuit configured to provide a second transfer path having a second delay time different from the first delay time; and a delay compensation circuit configured to compare a first clock input to the first unit circuit through the first transfer path with a second clock input to the second unit circuit through the second transfer path, and to adjust the second delay time so that the adjusted second delay time matches the first delay time.

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