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    • 1. 发明申请
    • FREQUENCY SELECTIVE DISTRIBUTED AMPLIFIER
    • 频率选择分配放大器
    • US20030201830A1
    • 2003-10-30
    • US10133829
    • 2002-04-26
    • Robert StengelScott Olson
    • H03F003/60
    • H03F3/607H03F3/605
    • A frequency selective differential amplifier (400) consistent with certain embodiments of the invention has a plurality of N amplifier stages (401, 402, 403 through 404) that collectively drive load (410). The plurality of N amplifier stages (401, 402, 403, . . . , 404) have input nodes and output nodes. A plurality of Nnull1 output phase shift circuits (421, 422, . . . , 423) connect the output nodes of the plurality of amplifier stages in a manner that causes output signals from the plurality of output nodes to add together for delivery to the load (410), the plurality of output phase shift circuits (421, 422, . . . , 423) have a plurality of phase shifts of null(f)nullnullnull(f)1,2; null(f)2,3; . . . ; null(f)Nnull2,Nnull1null. A plurality of Nnull1 input phase shift circuits (431, 432 through 433) are coupled to the plurality of input nodes and provide input signals thereto. The plurality of input phase shift circuits (431, 432, . . . , 433) have a plurality of phase shifts of null(f)nullnullnull(f)1,2; null(f)2,3; . . . ; null(f)Nnull2,Nnull1null. To achieve the frequency selectivity of the current invention, null(f) is not equal to null(f), so that output signals from the plurality of N amplifier stages (401, 402, 403, . . . , 404) are added with a frequency dependent phase relationship.
    • 与本发明的某些实施例一致的频率选择性差分放大器(400)具有共同驱动负载(410)的多个N个放大器级(401,402,403至404)。 多个N个放大器级(401,402,403,...,404)具有输入节点和输出节点。 多个N-1输出相移电路(421,422 ...,423)以使多个输出节点的输出信号相加的方式连接多个放大器级的输出节点, 多个输出相移电路(421,422 ...,423)中的负载(410)具有θ(f)= {θ(f))1,2的多个相移; theta(f)2,3; 。 。 。 ; theta(f)N-2,N-1}。 多个N-1输入相移电路(431,432至433)耦合到多个输入节点并向其提供输入信号。 多个输入相移电路(431,432 ...,433)具有Phi(f)= {Phi(f)1,2)的多个相移; Phi(f)2,3; 。 。 。 ; Phi(f)N-2,N-1}。 为了实现本发明的频率选择性,θ(f)不等于Phi(f),使得来自多个N个放大器级(401,402,403,...,404)的输出信号被加上 频率相关关系。
    • 3. 发明申请
    • Distributed amplifier
    • 分布式放大器
    • US20030184383A1
    • 2003-10-02
    • US10259893
    • 2002-09-30
    • Yasunori Ogawa
    • H03F003/60H03F003/68
    • H03F3/607
    • A distributed amplifier having a plurality of cascode amplifying circuits, and which causes little deterioration of the output waveform. In a preferred embodiment, the source potentials of the source-grounded transistors of the respective amplifying circuits are set individually. The source potentials of none or one or more of the source-grounded transistors are set at null0.8 volts, and the source potentials of the remaining source-grounded transistors are set at zero volts. The voltage gain of the source-grounded transistors whose source potential is null0.8 volts is zero, so that these source-grounded transistors do not contribute to the voltage gain of the amplifier as a whole. The source-grounded transistors whose source potential is zero volts contribute to the voltage gain, and output an amplified signal with a good waveform. The magnitude of the voltage gain can be adjusted by setting the number of source-grounded transistors whose source potential is zero volts.
    • 具有多个共源共栅放大电路的分布式放大器,其输出波形的劣化很小。 在优选实施例中,分别设置各个放大电路的源极接地晶体管的源极电位。 源极接地晶体管中的一个或多个源极电位被设置为+0.8伏,而剩余的源极接地晶体管的源极电位被设置为零伏特。 源极电压为+0.8伏特的源极接地晶体管的电压增益为零,因此这些源极接地晶体管对整个放大器的电压增益没有贡献。 源极电位为零伏特的源极接地晶体管有助于电压增益,并输出具有良好波形的放大信号。 可以通过设置源极电位为零伏的源极接地晶体管的数量来调节电压增益的幅度。
    • 6. 发明申请
    • Method for configuring low-noise integrated amplifier circuits
    • 配置低噪声集成放大器电路的方法
    • US20020125953A1
    • 2002-09-12
    • US10036049
    • 2001-12-31
    • Stephene Catala
    • H03F003/60
    • H03F1/26H03F2200/372
    • A method for configuring low-noise integrated amplifier circuits having an input stage with a transistor includes noise matching the circuit to the real part of a predetermined output impedance of a transfer element connected upstream of the circuit by a choice of process parameters during the production of the circuit and/or of geometry parameters of the integrated components and/or dimensioning the component values of the circuit, the noise figure of the circuit, dependent on a real generator resistance, is less than a predetermined figure in a range wherein the value of the output impedance real part also lies. The required power matching of the input impedance of the circuit to the output impedance is performed by choosing the effective load on a transistor collector to produce a complex voltage gain that, due to the Miller effect, generates an input impedance equal to the complex conjugate of the predetermined output impedance.
    • 用于配置具有晶体管的输入级的低噪声集成放大器电路的方法包括通过在制造期间选择工艺参数来将电路与电路上游连接的传输元件的预定输出阻抗的实部相匹配的噪声 集成组件的电路和/或几何参数和/或对电路的分量值进行尺寸化,取决于实际发电机电阻的电路的噪声系数小于预定的数字,其范围在 输出阻抗的实际部分也在于。 通过选择晶体管集电极上的有效负载来实现电路的输入阻抗与输出阻抗的所需功率匹配,以产生复合电压增益,由于米勒效应,产生等于复共轭的复共轭的输入阻抗 预定的输出阻抗。
    • 7. 发明申请
    • Distributed amplifier with improved flatness of frequency characteristic
    • 具有改善频率特性平坦度的分布式放大器
    • US20010002803A1
    • 2001-06-07
    • US09725451
    • 2000-11-30
    • Fujitsu Limited
    • Masaru Sato
    • H03F003/60
    • H03F3/607
    • FETs 31 to 34 for amplification are connected between an input transmission line 10 and an output transmission line 20. A terminating circuit 29 having a capacitor 292 and a terminating resistor 291 connected in series is connected to an end of the output transmission line 20. To improve a flatness of the gain over a low frequency band, a series-connected circuit having a capacitor 71 and a resistor 61 between the gate of each FET and ground, wherein the design parameter of this circuit is determined so that the impedance thereof is lower in the low frequency band but higher in a high frequency band than the input impedance of each FET.
    • 用于放大的FET 31至34连接在输入传输线10和输出传输线20之间。具有串联连接的电容器292和终端电阻器291的端接电路29连接到输出传输线20的一端。 提高在低频带上的增益的平坦度,在每个FET的栅极和地之间具有电容器71和电阻器61的串联电路,其中确定该电路的设计参数使得其阻抗较低 在高频带中高于每个FET的输入阻抗。
    • 8. 发明申请
    • High-frequency circuit
    • 高频电路
    • US20040155712A1
    • 2004-08-12
    • US10772314
    • 2004-02-06
    • Tatsunobu InamotoJiro Miyahara
    • H03F003/60
    • H05K3/222H03F3/19H03F3/60H05K1/0219H05K1/0237H05K2201/0715H05K2201/09336H05K2201/10636Y02P70/611
    • A high-frequency circuit comprises a substrate having an electronic component on an obverse side thereof, a first ground pattern formed on almost an entire reverse side of the substrate, a microstrip line formed on the obverse side of the substrate, and a bias line connected to the electronic component on the obverse side of the substrate and formed continuously on the obverse side and the reverse side of the substrate so as to cross the microstrip line on the reverse side of the substrate in plan view so as to supply a bias voltage to the electronic component, wherein the first ground pattern is formed so as to circumvent the bias line formed on the reverse side of the substrate, a portion of the first ground pattern that circumvents the bias line on the reverse side of the substrate is continuously formed on the obverse side of the substrate as a second ground pattern so as to divide the microstrip line in two parts, and a chip jumper is arranged to bridge the two divided parts of the microstrip line over the second ground pattern so as to connect the divided microstrip line electrically.
    • 高频电路包括在其正面上具有电子部件的基板,形成在基板的几乎整个背面的第一接地图案​​,形成在基板的正面的微带线和连接的偏置线 到基板的正面的电子部件,并且在基板的正面和反面上连续地形成,以在平面图中与基板的相反侧的微带线交叉,以便将偏置电压提供给 所述电子部件,其中形成所述第一接地图案​​以避开形成在所述基板的相反侧上的所述偏置线,所述第一接地图案​​的绕所述基板的相反侧的所述偏置线的部分连续地形成在 将基板的正面作为第二接地图案,以将微带线分成两部分,并且设置芯片跳线以将两个分开的部分 e微带线在第二接地图案上,以便电连接分开的微带线。