专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06690040B2 Vertical replacement-gate junction field-effect transistor 有权
标题翻译：垂直取代栅结场效应晶体管
公开(公告)号：US06690040B2
公开(公告)日：2004-02-10
申请号：US09950384
申请日：2001-09-10
申请人： Samir Chaudhry , Paul Arthur Layman , John Russell McMacken , Ross Thomson , Jack Qingsheng Zhao
发明人： Samir Chaudhry , Paul Arthur Layman , John Russell McMacken , Ross Thomson , Jack Qingsheng Zhao
IPC分类号： H01L2932
CPC分类号： H01L29/66909 , H01L21/823487 , H01L27/088 , H01L27/098 , H01L29/42392 , H01L29/66545 , H01L29/66742 , H01L29/78642 , H01L29/8083
摘要： A vertical JFET architecture. Generally, an integrated circuit structure includes a semiconductor area with a major surface formed along a plane and a first source/drain doped region formed in the surface. A second doped region forming a channel of different conductivity type than the first region is disposed over the first region. A third doped region is formed over the second doped region having an opposite conductivity type with respect to the second doped region, and forming a source/drain region. A gate is formed over the channel to form a vertical JFET.
摘要翻译：垂直JFET架构。通常，集成电路结构包括具有沿着平面形成的主表面的半导体区域和形成在表面中的第一源极/漏极掺杂区域。形成与第一区域不同的导电类型的沟道的第二掺杂区域设置在第一区域上。第三掺杂区形成在相对于第二掺杂区具有相反导电类型的第二掺杂区上方，以及形成源极/漏极区。在沟道上形成栅极以形成垂直JFET。

2. 发明授权

US06373083B1 Capacitor for semiconductor device and fabrication method thereof 有权
标题翻译：半导体器件用电容器及其制造方法
公开(公告)号：US06373083B1
公开(公告)日：2002-04-16
申请号：US09392632
申请日：1999-09-09
申请人： Bo-Seok Oh
发明人： Bo-Seok Oh
IPC分类号： H01L2932
CPC分类号： H01L27/0805
摘要： A capacitor having variable capacitance for a semiconductor device is formed on a device isolation area. A trench is formed in a semiconductor substrate for device isolation and a device isolating insulating film in which a bottom electrode of the capacitor is buried is formed in the trench. A first dielectric film is formed on the buried bottom electrode, a middle electrode is formed thereon and a second dielectric film and a top electrode are formed on the middle electrode, thereby having a three-layer electrode structure. The capacitor according to the present invention has variable capacitance in accordance with a voltage applied to top, bottom and middle electrodes, respectively.
摘要翻译：在器件隔离区域上形成具有用于半导体器件的可变电容的电容器。在用于器件隔离的半导体衬底中形成沟槽，并且在沟槽中形成其中埋入电容器的底部电极的器件隔离绝缘膜。在掩埋底部电极上形成第一电介质膜，在其上形成中间电极，在中间电极上形成第二电介质膜和顶部电极，由此具有三层电极结构。根据本发明的电容器分别根据施加到顶部，底部和中间电极的电压具有可变电容。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式