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1. 发明授权

US07544553B2 Integration scheme for fully silicided gate 有权
标题翻译：完全硅化栅的集成方案
公开(公告)号：US07544553B2
公开(公告)日：2009-06-09
申请号：US11094367
申请日：2005-03-30
申请人： Marcus Culmsee , Hermann Wendt , Lothar Doni
发明人： Marcus Culmsee , Hermann Wendt , Lothar Doni
IPC分类号： H01L23/336 , H01L21/3205
CPC分类号： H01L29/665 , H01L21/28097 , H01L29/66545 , H01L29/6656
摘要： To form a semiconductor device, a silicon (e.g., polysilicon) gate layer is formed over a gate dielectric and a sacrificial layer (preferably titanium nitride) is formed over the silicon gate layer. The silicon gate layer and the sacrificial layer are patterned to form a gate structure. A spacer, such as an oxide sidewall spacer and a nitride sidewall spacer, is formed adjacent the sidewall of the gate structure. The semiconductor body is then doped to form a source region and a drain region that are self-aligned to the spacers. The sacrificial layer can then be removed selectively with respect to the oxide sidewall spacer, the nitride sidewall spacer and the silicon gate. A metal layer (e.g., nickel) is formed over the source region, the drain region and the silicon gate and reacted with these regions to form a silicided source contact, a silicided drain contact and a silicided gate.
摘要翻译：为了形成半导体器件，在栅极电介质上形成硅（例如，多晶硅）栅极层，并且在硅栅极层上形成牺牲层（优选氮化钛）。图案化硅栅极层和牺牲层以形成栅极结构。邻近栅极结构的侧壁形成间隔物，例如氧化物侧壁间隔物和氮化物侧壁间隔物。然后，半导体体被掺杂以形成与间隔物自对准的源极区域和漏极区域。然后可以相对于氧化物侧壁间隔物，氮化物侧壁间隔物和硅栅极选择性地去除牺牲层。在源极区域，漏极区域和硅栅极上形成金属层（例如镍），并与这些区域反应以形成硅化物源极接触，硅化物漏极接触和硅化物栅极。

2. 发明授权

US07205198B2 Method of making a bi-directional read/program non-volatile floating gate memory cell 有权
标题翻译：制造双向读/写非易失浮动存储单元的方法
公开(公告)号：US07205198B2
公开(公告)日：2007-04-17
申请号：US11521162
申请日：2006-09-14
申请人： Bomy Chen , Sohrab Kianian , Jack Frayer
发明人： Bomy Chen , Sohrab Kianian , Jack Frayer
IPC分类号： H01L23/336 , H01L29/788
CPC分类号： H01L27/11521 , G11C16/0458 , G11C16/0483 , G11C16/0491 , H01L27/115
摘要： A bi-directional read/program non-volatile memory cell and array is capable of achieving high density. Each memory cell has two spaced floating gates for storage of charges thereon. The cell has spaced apart source/drain regions with a channel therebetween, with the channel having three portions. One of the floating gate is over a first portion; another floating gate is over a second portion, and a gate electrode controls the conduction of the channel in the third portion between the first and second portions. An independently controllable control gate is insulated from each of the source/drain regions, and is also capacitively coupled to the floating gate. The cell programs by hot channel electron injection, and erases by Fowler-Nordheim tunneling of electrons from the floating gate to the gate electrode. Bi-directional read permits the cell to be programmed to store bits, with one bit in each floating gate. The independently controllable control gates permit an array of such memory cells to operate in a NAND configuration.
摘要翻译：双向读/写非易失性存储单元和阵列能够实现高密度。每个存储单元具有两个间隔开的浮动栅极，用于在其上存储电荷。电池具有间隔开的源极/漏极区域，其间具有沟道，沟道具有三个部分。浮动门之一在第一部分之上; 另一个浮栅位于第二部分之上，栅电极控制第一和第二部分之间的第三部分中的沟道的导通。独立可控的控制栅极与源极/漏极区域中的每一个绝缘，并且还电容耦合到浮动栅极。通过热通道电子注入的电池程序，并通过Fowler-Nordheim将电子从浮动栅极隧穿到栅电极而擦除。双向读取允许将单元编程为存储位，每个浮动栅极中有一位。独立可控的控制门允许这种存储器单元的阵列在NAND配置中操作。

3. 发明授权

US08349695B2 Work function adjustment in high-k gate stacks including gate dielectrics of different thickness 有权
标题翻译：在高k栅极堆叠中的功能调整包括不同厚度的栅极电介质
公开(公告)号：US08349695B2
公开(公告)日：2013-01-08
申请号：US12848741
申请日：2010-08-02
申请人： Thilo Scheiper , Andy Wei , Martin Trentzsch
发明人： Thilo Scheiper , Andy Wei , Martin Trentzsch
IPC分类号： H01L23/336
CPC分类号： H01L21/823462 , H01L21/823857
摘要： In sophisticated manufacturing techniques, the work function and thus the threshold voltage of transistor elements may be adjusted in an early manufacturing stage by providing a work function adjusting species within the high-k dielectric material with substantially the same spatial distribution in the gate dielectric materials of different thickness. After the incorporation of the work function adjusting species, the final thickness of the gate dielectric materials may be adjusted by selectively forming an additional dielectric layer so that the further patterning of the gate electrode structures may be accomplished with a high degree of compatibility to conventional manufacturing techniques. Consequently, extremely complicated processes for re-adjusting the threshold voltages of transistors having a different thickness gate dielectric material may be avoided.
摘要翻译：在复杂的制造技术中，工作功能和晶体管元件的阈值电压可以在早期制造阶段通过提供在高k电介质材料内调节物质的功函数来调节，其中栅极电介质材料具有基本上相同的空间分布不同厚度。在结合工作功能调整物质之后，可以通过选择性地形成额外的介电层来调节栅极电介质材料的最终厚度，使得栅电极结构的进一步图案化可以以与常规制造高度的相容性来实现技术因此，可以避免用于重新调整具有不同厚度栅极电介质材料的晶体管的阈值电压的非常复杂的工艺。

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