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1. 发明授权

US06410948B1 Memory cell arrays comprising intersecting slanted portions 有权
标题翻译：存储单元阵列包括相交的倾斜部分
公开(公告)号：US06410948B1
公开(公告)日：2002-06-25
申请号：US09340983
申请日：1999-06-28
申请人： Luan Tran , D. Mark Duncan , Tyler A. Lowrey , Rob B. Kerr , Kris K. Brown
发明人： Luan Tran , D. Mark Duncan , Tyler A. Lowrey , Rob B. Kerr , Kris K. Brown
IPC分类号： H01L2710
CPC分类号： H01L27/10852 , H01L27/10808 , H01L27/10885
摘要： A memory device includes memory cells, bit lines, active area lines running generally in parallel to the bit lines, and transistors formed in each active area line and electrically coupling memory cells to corresponding bit lines. Each bit line includes slanted portions that intersect a corresponding portion of an active area line at an angle. Contacts electrically coupling the bit line to portions of the active area line are formed in a region generally defined by the angled intersection of the bit line to the active area line. The memory cells can have an area of about 6F2, and the bit lines can be coupled to sense amplifiers in a folded bit line configuration. Each bit line includes a first level portion and a second level portion.
摘要翻译：存储器件包括存储器单元，位线，通常与位线平行地运行的有源区线以及在每个有源区域线中形成的晶体管，并将存储单元电耦合到相应的位线。每个位线包括以一角度与有源区域线的相应部分相交的倾斜部分。将位线电耦合到有源区域线的部分的触点形成在通常由位线到有源区域线的成角度的交叉点限定的区域中。存储器单元可以具有约6F2的面积，并且位线可以以折叠位线配置耦合到读出放大器。每个位线包括第一电平部分和第二电平部分。

2. 发明授权

US07045834B2 Memory cell arrays 失效
标题翻译：存储单元阵列
公开(公告)号：US07045834B2
公开(公告)日：2006-05-16
申请号：US10059727
申请日：2002-01-29
申请人： Luan Tran , D. Mark Duncan , Tyler A. Lowrey , Rob B. Kerr , Kris K. Brown
发明人： Luan Tran , D. Mark Duncan , Tyler A. Lowrey , Rob B. Kerr , Kris K. Brown
IPC分类号： H01L27/10 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： H01L27/10852 , H01L27/10808 , H01L27/10885
摘要： A memory device includes memory cells, bit lines, active area lines running generally in parallel to the bit lines, and transistors formed in each active area line and electrically coupling memory cells to corresponding bit lines. Each bit line includes slanted portions that intersect a corresponding portion of an active area line at an angle. Contacts electrically coupling the bit line to portions of the active area line are formed in a region generally defined by the angled intersection of the bit line to the active area line. The memory cells can have an area of about 6F2, and the bit lines can be coupled to sense amplifiers in a folded bit line configuration. Each bit line includes a first level portion and a second level portion.
摘要翻译：存储器件包括存储器单元，位线，通常与位线平行地运行的有源区线以及在每个有源区域线中形成的晶体管，并将存储单元电耦合到相应的位线。每个位线包括以一角度与有源区域线的相应部分相交的倾斜部分。将位线电耦合到有源区域线的部分的触点形成在通常由位线到有源区域线的成角度的交叉点限定的区域中。存储器单元可以具有约6F 2的面积，并且位线可以以折叠位线配置耦合到读出放大器。每个位线包括第一电平部分和第二电平部分。

3. 发明授权

US06607944B1 Method of making memory cell arrays 有权
标题翻译：制造存储单元阵列的方法
公开(公告)号：US06607944B1
公开(公告)日：2003-08-19
申请号：US09918345
申请日：2001-07-30
申请人： Luan Tran , D. Mark Duncan , Tyler A. Lowrey , Rob B. Kerr , Kris K. Brown
发明人： Luan Tran , D. Mark Duncan , Tyler A. Lowrey , Rob B. Kerr , Kris K. Brown
IPC分类号： H01L2182
CPC分类号： H01L27/10852 , H01L27/10808 , H01L27/10885
摘要： A memory device includes memory cells, bit lines, active area lines running generally in parallel to the bit lines, and transistors formed in each active area line and electrically coupling memory cells to corresponding bit lines. Each bit line includes slanted portions that intersect a corresponding portion of an active area line at an angle. Contacts electrically coupling the bit line to portions of the active area line are formed in a region generally defined by the angled intersection of the bit line to the active area line. The memory cells can have an area of about 6F2, and the bit lines can be coupled to sense amplifiers in a folded bit line configuration. Each bit line includes a first level portion and a second level portion.
摘要翻译：存储器件包括存储器单元，位线，通常与位线平行地运行的有源区线以及在每个有源区域线中形成的晶体管，并将存储单元电耦合到相应的位线。每个位线包括以一角度与有源区域线的相应部分相交的倾斜部分。将位线电耦合到有源区域线的部分的触点形成在通常由位线到有源区域线的成角度的交叉点限定的区域中。存储器单元可以具有约6F2的面积，并且位线可以以折叠位线配置耦合到读出放大器。每个位线包括第一电平部分和第二电平部分。

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