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1. 发明授权

US06359829B1 Magnetic memory 有权
标题翻译：磁记忆
公开(公告)号：US06359829B1
公开(公告)日：2002-03-19
申请号：US09443751
申请日：1999-11-19
申请人： Hugo Van Den Berg
发明人： Hugo Van Den Berg
IPC分类号： G11C802
CPC分类号： G11C11/15 , G11C11/16
摘要： A magnetic memory of the random access type (MRAM) contains a memory cell array formed of a multiplicity of memory cells. The memory cells are disposed in the form of a matrix at the points of intersection of word lines and sense lines and the logical data contents of which are defined by a magnetic state. The magnetic memory further contains an addressing circuit allocated to the word lines. The address circuit applies a read voltage to the word line of one or more selected memory cells, the data contents of which are to be read out. An evaluation circuit is provided that is allocated to the sense lines and receives and evaluates a sense signal corresponding to the data contents of the selected memory cell or memory cells. The evaluation circuit has a comparator circuit receiving a reference signal supplied by a reference element that is compared with the sense signal of the memory cell or memory cells to be read out.
摘要翻译：随机存取类型（MRAM）的磁存储器包含由多个存储单元形成的存储单元阵列。存储单元在字线和感测线的相交点处以矩阵的形式设置，并且其逻辑数据内容由磁状态定义。磁存储器还包含分配给字线的寻址电路。地址电路将读取的电压施加到一个或多个选择的存储器单元的字线，其数据内容将被读出。提供分配给感测线的评估电路，并且接收和评估与所选存储单元或存储单元的数据内容相对应的感测信号。评估电路具有比较器电路，其接收由参考元件提供的参考信号，该参考信号与要读出的存储器单元或存储器单元的感测信号进行比较。

2. 发明授权

US06510096B2 Power down voltage control method and apparatus 有权
公开(公告)号：US06510096B2
公开(公告)日：2003-01-21
申请号：US09981945
申请日：2001-10-17
申请人： Jong-hyun Choi , Jei-hwan Yoo , Jong-eon Lee , Hyun-soon Jang
发明人： Jong-hyun Choi , Jei-hwan Yoo , Jong-eon Lee , Hyun-soon Jang
IPC分类号： G11C802
CPC分类号： G11C5/143 , G11C7/22
摘要： A semiconductor device for controlling entry to and exit from a power down mode (DPD) of a semiconductor memory, comprising a plurality of voltage generators for providing operating voltages to the semiconductor memory; a DPD controller for detecting a DPD condition and for generating a DPD signal to control the application of the operating voltages to the semiconductor memory; and circuitry for controlling the timing of turning on/off the plurality of voltage generators upon entry/exit of DPD mode to reduce surge current through the semiconductor memory to less than maximum current level.

3. 发明授权

US06456556B1 Voltage regulator and data path for a memory device 有权
标题翻译：用于存储器件的稳压器和数据通路
公开(公告)号：US06456556B1
公开(公告)日：2002-09-24
申请号：US09792553
申请日：2001-02-23
申请人： Brian W. Huber
发明人： Brian W. Huber
IPC分类号： G11C802
CPC分类号： G11C5/147 , G11C5/145
摘要： The present invention relates generally to a method and apparatus for changing the output of a voltage regulator by forcing the voltage regulator into a low power mode. One aspect of the present invention is directed to a method of forcing the voltage regulator into a low power mode by increasing the rate at which a bias current, supplied to a differential amplifier within the voltage regulator, is decreased. The differential amplifier is used to set the output of the voltage regulator. Another aspect of the present invention is directed to an apparatus having a first switch for connecting a control signal for controlling a source of bias current for the amplifier to ground and a second switch connected between a resistive and capacitive load connected to an output transistor and a predetermined voltage other than ground.
摘要翻译：本发明一般涉及通过将调压器强制为低功率模式来改变电压调节器的输出的方法和装置。本发明的一个方面涉及通过增加提供给稳压器内的差分放大器的偏置电流减小的速率来将调压器强制为低功率模式的方法。差分放大器用于设置稳压器的输出。本发明的另一方面涉及一种具有用于连接控制信号的第一开关的装置，所述控制信号用于控制放大器与地的偏置电流源，以及连接在连接到输出晶体管的电阻和电容性负载之间的第二开关，地线以外的预定电压。

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