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1. 发明授权

US06906975B2 Reference voltage generating circuit of nonvolatile ferroelectric memory device 有权
标题翻译：非易失性铁电存储器件参考电压发生电路
公开(公告)号：US06906975B2
公开(公告)日：2005-06-14
申请号：US10207197
申请日：2002-07-30
申请人： Hee Bok Kang , Hun Woo Kye , Duck Ju Kim , Je Hoon Park
发明人： Hee Bok Kang , Hun Woo Kye , Duck Ju Kim , Je Hoon Park
IPC分类号： G11C7/14 , G11C11/22 , G11C7/04
CPC分类号： G11C11/22 , G11C7/14
摘要： A reference voltage generating circuit of a non-volatile ferroelectric memory device includes a temperature compensating control circuit that increases and outputs a level of a signal to a reference capacitor node according to an increase in temperature when a reference control signal is at a high level, a plurality of ferroelectric capacitors connected in parallel, each of first electrodes of the plurality of ferroelectric capacitors are commonly connected to a ground voltage terminal and each of second electrodes of the plurality of ferroelectric capacitors are commonly connected to the reference capacitor node, and a plurality of switching blocks controlled by a reference wordline signal, each having drain terminals commonly connected to the reference capacitor node, source terminals connected to a corresponding bitline.
摘要翻译：非易失性强电介质存储器件的参考电压产生电路包括：温度补偿控制电路，当温度补偿控制信号处于高电平时，根据温度上升，增加信号电平并将其输出到参考电容器节点; 并联连接的多个铁电电容器，多个铁电电容器的每个第一电极共同连接到接地电压端子，并且多个铁电电容器中的每个第二电极共同连接到参考电容器节点，并且多个由参考字线信号控制的开关块，其各自具有共同连接到参考电容器节点的漏极端子，源极端子连接到对应的位线。

2. 发明授权

US06879510B2 Nonvolatile ferroelectric memory device and method for operating the same 有权
标题翻译：非易失性铁电存储器件及其操作方法
公开(公告)号：US06879510B2
公开(公告)日：2005-04-12
申请号：US10286913
申请日：2002-11-04
申请人： Hee Bok Kang , Hun Woo Kye , Duck Ju Kim , Je Hoon Park
发明人： Hee Bok Kang , Hun Woo Kye , Duck Ju Kim , Je Hoon Park
IPC分类号： G11C11/22 , G11C5/06
CPC分类号： G11C11/22
摘要： A nonvolatile ferroelectric memory device includes a top cell array block having a first plurality of unit cells, each with a pair of first and second top split wordlines, a bottom cell array block provided with a second plurality of unit cells, each having a pair of first and second bottom split wordlines to correspond to the pair of first and second top split wordlines, a top split wordline driver controlling an output signal transmitted to the first and second top split wordlines of the top cell array block, a bottom split wordline driver controlling an output signal transmitted to the first and second bottom split wordlines of the bottom cell array block, a split wordline driver controller outputting first and second split wordline control signals, and a sensing amplifier arranged for each bitline between the top cell array block and the bottom cell array block.
摘要翻译：非易失性铁电存储器件包括具有第一多个单位单元的顶部单元阵列块，每个单元具有一对第一和第二顶部分割字线，底部单元阵列块，其具有第二多个单位单元，每个单元单元具有一对第一和第二底部分割字线对应于一对第一和第二顶部分割字线，顶部分割字线驱动器，控制发送到顶部单元阵列块的第一和第二顶部分离字线的输出信号，底部分离字线驱动器控制发送到底部单元阵列块的第一和第二底部分离字线的输出信号，输出第一和第二分割字线控制信号的分割字线驱动器控制器，以及布置在顶部单元阵列块和底部单元阵列块之间的每个位线的感测放大器单元阵列块。

3. 发明授权

US06836425B2 CODING CELL OF NONVOLATILE FERROELECTRIC MEMORY DEVICE AND OPERATING METHOD THEREOF, AND COLUMN REPAIR CIRCUIT OF NONVOLATILE FERROELECTRIC MEMORY DEVICE HAVING THE CODING CELL AND METHOD FOR REPAIRING COLUMN 有权
标题翻译：非易失性存储器件的编码单元及其操作方法，以及具有编码单元的非易失性存储器件的修复电路及其修复方法
公开(公告)号：US06836425B2
公开(公告)日：2004-12-28
申请号：US10653238
申请日：2003-09-03
申请人： Hee Bok Kang , Hun Woo Kye , Duck Ju Kim , Je Hoon Park
发明人： Hee Bok Kang , Hun Woo Kye , Duck Ju Kim , Je Hoon Park
IPC分类号： G11C2900
CPC分类号： G11C29/789 , G11C11/22
摘要： A fail repair circuit of a nonvolatile ferroelectric memory device and a method for repairing the same are disclosed, in which a redundancy time can be reduced and a redundancy algorithm can be changed or added at any time. The fail repair circuit includes: a memory test logic block generating a redundancy active pulse (RAP) if a row address including a fail bit to be repaired is found during test; a power-up sensor generating a power-up pulse if a stable power source voltage is sensed; a first redundancy control block generating first to fifth control signals ENN, ENP, EQN, CPL, and PREC and a sixth control signal ENW in response to the RAP and the power-up pulse; a counter generating n bit counter bit signal increased by one bit through the RAP to correspond to the number of redundancy bits; a redundancy counter decoding control block generating an activated coding signal ENW in response to the counter bit signal of the counter and the sixth control signal ENW; and a redundancy coding block outputting a master signal in response to the coding signal ENW and the first to fifth control signals, programming a fail address in a plurality of redundancy coding cells, and outputting seventh and eighth control signals REN and RPUL to repair the programmed fail address.
摘要翻译：公开了一种非易失性铁电存储器件的故障修复电路及其修复方法，其中可以减少冗余时间，并可随时更改或添加冗余算法。故障修复电路包括：如果在测试期间发现包括要修复的故障位的行地址，则产生冗余有效脉冲（RAP）的存储器测试逻辑块; 如果感测到稳定的电源电压，则产生上电脉冲的上电传感器; 第一冗余控制块，响应于RAP和上电脉冲，产生第一到第五控制信号ENN，ENP，EQN，CPL和PREC以及第六控制信号ENW; 计数器产生通过RAP增加1比特的n比特计数器比特信号以对应于冗余比特数; 冗余计数器解码控制块响应于计数器的计数器位信号和第六控制信号ENW产生激活的编码信号ENW 和第一至第五控制信号输出主信号，对多个冗余编码单元中的故障地址进行编程，并输出第七和第八控制信号REN < 和RPUL 修复编程的失败地址。

4. 发明授权

US06687173B2 Circuit for testing ferroelectric capacitor in FRAM 有权
标题翻译：用于测试FRAM中的铁电电容器的电路
公开(公告)号：US06687173B2
公开(公告)日：2004-02-03
申请号：US10166613
申请日：2002-06-12
申请人： Hee Bok Kang , Hun Woo Kye , Duck Ju Kim , Je Hoon Park , Geun Il Lee
发明人： Hee Bok Kang , Hun Woo Kye , Duck Ju Kim , Je Hoon Park , Geun Il Lee
IPC分类号： G11C2900
CPC分类号： G11C29/028 , G11C11/22 , G11C29/50
摘要： A circuit for testing a ferroelectric capacitor in a FRAM includes: a test pulse signal generating part; a digital test pulse providing part, responsive to the test pulse signal; an n-bit counter, responsive to the digital test pulse signal as a clock signal; a measuring control signal providing part; a write pulse bar signal generating part; an input drive control part for receiving a reference voltage signal, a voltage signal at the first electrode of the ferroelectric capacitor, the measuring control signal, and the write pulse bar signal, and applying a driving voltage to the second electrode of the ferroelectric capacitor in response to the test pulse signal, and a measured result forwarding part for receiving the reference voltage signal and the voltage signal from the first electrode, and amplifying and forwarding a voltage variation between the electrodes of the ferroelectric capacitor.
摘要翻译：用于测试FRAM中的铁电电容器的电路包括：测试脉冲信号产生部分; 数字测试脉冲提供部分，响应测试脉冲信号; n比特计数器，响应数字测试脉冲信号作为时钟信号; 测量控制信号提供部分; 写脉冲条信号产生部分; 用于接收参考电压信号的输入驱动控制部分，强电介质电容器的第一电极处的电压信号，测量控制信号和写入脉冲条信号，以及向铁电电容器的第二电极施加驱动电压响应于测试脉冲信号，以及测量结果转发部分，用于接收来自第一电极的参考电压信号和电压信号，并且放大并转发铁电电容器的电极之间的电压变化。

5. 发明授权

US06600675B2 Reference circuit in ferroelectric memory and method for driving the same 有权
标题翻译：铁电存储器中的参考电路及其驱动方法
公开(公告)号：US06600675B2
公开(公告)日：2003-07-29
申请号：US10170646
申请日：2002-06-14
申请人： Hee Bok Kang , Hun Woo Kye , Duck Ju Kim , Je Hoon Park , Geun II Lee
发明人： Hee Bok Kang , Hun Woo Kye , Duck Ju Kim , Je Hoon Park , Geun II Lee
IPC分类号： G11C1122
CPC分类号： G11C11/22
摘要： A reference circuit in a ferroelectric memory includes a reference plate line and a reference word line adjacently formed in a first direction in correspondence with a cell block including a plurality of unit cells; a plurality of bit lines connected to the unit cells and formed in a second direction; a plurality of parallelly disposed reference capacitors each having a first electrode connected to the reference plate line and a second electrode connected to a storage node SN of a reference cell; an initializing unit connected to the storage node for initializing a level of the reference cell; and a switching block formed between the bit lines and the storage node in correspondence with the bit lines and controlled by signals applied to the reference word line.
摘要翻译：铁电存储器中的参考电路包括与包括多个单元电池的单元块相对应的在第一方向上相邻形成的参考板线和参考字线; 连接到所述单位单元并沿第二方向形成的多个位线; 多个平行布置的参考电容器，每个参考电容器具有连接到参考板线的第一电极和连接到参考单元的存储节点SN的第二电极; 连接到存储节点的初始化单元，用于初始化参考单元的电平; 以及与位线对应地形成在位线和存储节点之间并由施加到参考字线的信号控制的切换块。

6. 发明授权

US06490189B1 Boost voltage generating circuit for nonvolatile ferroelectric memory device and method for generating boost voltage 失效
标题翻译：用于非易失性铁电存储器件的升压产生电路和用于产生升压电压的方法
公开(公告)号：US06490189B1
公开(公告)日：2002-12-03
申请号：US10036369
申请日：2002-01-07
申请人： Hee Bok Kang , Hun Woo Kye , Duck Ju Kim , Je Hoon Park
发明人： Hee Bok Kang , Hun Woo Kye , Duck Ju Kim , Je Hoon Park
IPC分类号： G11C1122
CPC分类号： G11C11/22 , G11C5/145
摘要： A boost voltage generating circuit and method for a nonvolatile ferroelectric memory device is disclosed in the present invention. The present invention provides a stable operation when a power source supply voltage region is in a wide power source voltage region, and a layout area for generating a boost voltage is reduced, thereby reducing a chip cost.
摘要翻译：在本发明中公开了一种用于非易失性铁电存储器件的升压电压产生电路和方法。本发明提供电源电压区域处于宽电源电压区域时的稳定动作，并且用于产生升压电压的布局区域减小，从而降低芯片成本。

7. 发明授权

US06845030B2 Nonvolatile ferroelectric memory device and method of fabricating the same 有权
标题翻译：非易失性铁电存储器件及其制造方法
公开(公告)号：US06845030B2
公开(公告)日：2005-01-18
申请号：US10308098
申请日：2002-12-03
申请人： Hee Bok Kang , Hun Woo Kye , Geun Il Lee , Je Hoon Park , Jung Hwan Kim
发明人： Hee Bok Kang , Hun Woo Kye , Geun Il Lee , Je Hoon Park , Jung Hwan Kim
IPC分类号： G11C5/06 , G11C11/22 , H01L21/8246 , H01L27/10 , H01L27/105 , H01L27/115 , G11C8/00
CPC分类号： H01L27/11502 , G11C5/063 , G11C11/22
摘要： A nonvolatile ferroelectric memory device includes a plurality of top array blocks disposed along a first direction, each having a plurality of top sub-cell array blocks disposed along a second direction perpendicular to the first direction, each of the top sub-cell array blocks include a first plurality of unit cells, a plurality of bottom array blocks disposed along the first direction below the plurality of top array blocks, each having a plurality of bottom sub-cell array blocks disposed along the second direction, each of the bottom sub-cell array blocks include a second plurality of unit cells, a plurality of sub-bit lines extending along the second direction and disposed at equal first intervals along the first direction, each sub-bit line connected to at least a first end of one of the first and second pluralities of unit cells, and a plurality of main bit lines extending along the second direction and disposed at the equal first intervals along a third direction perpendicular to both the first and second directions.
摘要翻译：非易失性铁电存储器件包括沿着第一方向设置的多个顶部阵列块，每个顶部阵列块具有沿垂直于第一方向的第二方向设置的多个顶部子单元阵列块，每个顶部子单元阵列块包括第一多个单位单元，沿着多个顶部阵列块下方的第一方向设置的多个底部阵列块，每个底部阵列块具有沿着第二方向设置的多个底部子单元阵列块，每个底部子单元阵列块包括第二多个单位单元，沿着第二方向延伸并且沿着第一方向以相等的第一间隔布置的多个子位线，每个子位线连接到第一个单元中的一个的至少第一端和第二多个单元电池，以及沿着第二方向延伸并沿着第三方向垂直设置的相等的第一间隔的多个主位线到第一和第二方向。

8. 发明授权

US06775172B2 Nonvolatile ferroelectric memory and method for driving the same 有权
标题翻译：非易失性铁电存储器及其驱动方法
公开(公告)号：US06775172B2
公开(公告)日：2004-08-10
申请号：US10233399
申请日：2002-09-04
申请人： Hee Bok Kang , Hun Woo Kye , Geun Il Lee , Je Hoon Park , Jung Hwan Kim
发明人： Hee Bok Kang , Hun Woo Kye , Geun Il Lee , Je Hoon Park , Jung Hwan Kim
IPC分类号： G11C1112
CPC分类号： G11C11/22
摘要： A nonvolatile ferroelectric memory includes a top cell array block and a bottom cell array block, each array block having sub cell array blocks, each sub cell array block having a plurality of unit cells; a plurality of main bitlines arranged in one direction in correspondence to a column unit of the sub cell array blocks; a plurality of sub bitlines each connected to one terminal of one of the plurality of unit cells arranged in a same direction as the one direction of the main bitlines; a sense amplifier block having sense amplifiers between the top cell array block and the bottom cell array block, each sense amplifier for amplifying a signal from the main bitline; sub bitline first switch signal application lines and sub bitline second switch signal application lines for controlling connection of the sub bitlines and the main bitlines, sub bitline pull up signal application lines for controlling pull up of the sub bitlines by a self boost operation, and sub bitline pull down signal application lines for selective pull down of the sub bitlines, which are arranged perpendicular to the sub bitlines in correspondence to the sub cell array blocks; a first switch device in each sub cell array block in correspondence to a column direction for operation under control of the sub bitline first switch signal application line; a second switch device in each sub cell array block in correspondence to a column direction for selective transfer of a signal from the sub bitline pull up signal application line to the sub bitline under the control of the sub line second switch signal application line; and, a third switch device in each sub cell array block in correspondence to a column direction for selective pull down of the sub bitline under control of the sub bitline pull down application line.
摘要翻译：非易失性铁电存储器包括顶单元阵列块和底单元阵列块，每个阵列块具有子单元阵列块，每个子单元阵列块具有多个单位单元; 对应于子单元阵列块的列单元沿一个方向布置的多个主位线; 多个子位线，分别连接到与主位线的一个方向相同的方向上布置的多个单位单元中的一个的一个端子; 在顶部单元阵列块和底部单元阵列块之间具有读出放大器的读出放大器块，用于放大来自主位线的信号的每个读出放大器; 子位线第一开关信号施加线和子位线第二开关信号施加线，用于控制子位线和主位线的连接，用于通过自升压操作控制子位线的上拉的副位线上拉信号施加线，以及子位线位线下拉信号施加线，用于与子单元阵列块相对应地垂直于子位线布置的子位线的选择性下拉; 每个子单元阵列块中的对应于在子位线第一开关信号施加线的控制下操作的列方向的第一开关装置; 对应于列方向的每个子单元阵列块中的第二开关装置，用于在子线路第二开关信号施加线的控制下将信号从子位线上拉信号施加线选择性地传送到子位线; 以及在子位线下拉应用行的控制下，与子位线的选择性下拉相对应的列方向的每个子单元阵列块中的第三开关器件。

9. 发明授权

US06754096B2 Apparatus and method for driving ferroelectric memory 有权
标题翻译：用于驱动铁电存储器的装置和方法
公开(公告)号：US06754096B2
公开(公告)日：2004-06-22
申请号：US10320611
申请日：2002-12-17
申请人： Hee Bok Kang , Hun Woo Kye , Geun Il Lee , Je Hoon Park , Jung Hwan Kim
发明人： Hee Bok Kang , Hun Woo Kye , Geun Il Lee , Je Hoon Park , Jung Hwan Kim
IPC分类号： G11C1122
CPC分类号： G11C11/22 , G11C8/06 , G11C8/18
摘要： Disclosed is an apparatus and method for driving a ferroelectric memory that can secure an enough read/write cycle time of a corresponding address during a chip is driven. In a driving circuit to generate an operation pulse for controlling operation of a ferroelectric chip, the ferroelectric memory driving apparatus includes an address latch block for latching a buffered address signal by a feedback cell operation pulse, an address transition detection summation value outputting block for generating an address transition detection pulse by detecting change of an address signal, and for outputting summation of address transition pulses generated by a plurality of addresses, a pulse width extension/control pulse generating block for extending a pulse width of the summation of the address transition pulses and outputting a chip control pulse by using an extended signal, and a cell operation pulse generating block for generating a cell operating pulse with a pulse width required on a read/write chip operation by using the chip control pulse, wherein in an active region of the cell operation pulse corresponding the address, an ATD signal of a different address is not generated.
摘要翻译：公开了一种用于驱动铁电存储器的装置和方法，其可以在驱动芯片期间确保相应地址的足够的读/写周期时间。在用于产生用于控制铁电芯片的操作的操作脉冲的驱动电路中，铁电存储器驱动装置包括用于通过反馈单元操作脉冲来锁存缓冲地址信号的地址锁存块，用于产生的地址转移检测求和值输出块通过检测地址信号的变化并输出由多个地址产生的地址转换脉冲的和的地址转换检测脉冲，用于扩展地址转换脉冲的和的脉冲宽度的脉宽扩展/控制脉冲发生块并通过使用扩展信号输出芯片控制脉冲;以及单元操作脉冲产生模块，用于通过使用芯片控制脉冲产生具有读/写芯片操作所需的脉冲宽度的单元操作脉冲，其中在单元操作脉冲对应的地址，一个ATD信号不同的地址 s不生成。

10. 发明授权

US06597608B2 CODING CELL OF NONVOLATILE FERROELECTRIC MEMORY DEVICE AND OPERATING METHOD THEREOF, AND COLUMN REPAIR CIRCUIT OF NONVOLATILE FERROELECTRIC MEMORY DEVICE HAVING THE CODING CELL AND METHOD FOR REPAIRING COLUMN 失效
标题翻译：非易失性存储器件的编码单元及其操作方法，以及具有编码单元的非易失性存储器件的修复电路及其修复方法
公开(公告)号：US06597608B2
公开(公告)日：2003-07-22
申请号：US10163351
申请日：2002-06-07
申请人： Hee Bok Kang , Hun Woo Kye , Duck Ju Kim , Je Hoon Park , Geun II Lee
发明人： Hee Bok Kang , Hun Woo Kye , Duck Ju Kim , Je Hoon Park , Geun II Lee
IPC分类号： G11C2900
CPC分类号： G11C29/789 , G11C7/20 , G11C11/22 , G11C29/787
摘要： A column repair circuit and method of a nonvolatile ferroelectric memory device can include: a memory test logic block capable of generating a redundancy active pulse (RAP) and a corresponding fail input/output (IO) number FION if a column address including a fail bit to be repaired is found during test; a power-up sensor capable of generating a power-up pulse if a stable power source voltage is sensed; a first redundancy control block capable of generating first to fifth control signals ENN, ENP, EQN, CPL, and PREC and a sixth control signal ENW in response to the RAP and the power-up pulse; a counter generating n bit counter bit signal increased by one bit through the RAP to correspond to the number of redundancy bits; a redundancy counter decoding control block capable of generating an activated coding signal ENW in response to the counter bit signal of the counter and the sixth control signal ENW; and a redundancy coding block capable of coding a fail column address in response to the coding signal ENW , the first to fifth control signals, the first and second address signals ADD and ADDB, and the fail IO number FION , and coding a fail IO bus.
摘要翻译：非易失性铁电存储器件的列修复电路和方法可以包括：存储器测试逻辑块，其能够产生冗余有效脉冲（RAP）和相应的失败输入/输出（IO）数FION ，如果列地址包括在测试过程中发现故障点被修复; 如果感测到稳定的电源电压，则能够产生上电脉冲的上电传感器; 能够响应于RAP和上电脉冲而产生第一至第五控制信号ENN，ENP，EQN，CPL和PREC以及第六控制信号ENW的第一冗余控制块; 计数器产生通过RAP增加1比特的n比特计数器比特信号以对应于冗余比特数; 冗余计数器解码控制块，其能够响应于计数器的计数器位信号和第六控制信号ENW产生激活的编码信号ENW ，第一至第五控制信号，第一和第二地址信号ADD和ADDB以及故障IO号FION 编码故障列地址的冗余编码块，并编码失败的IO总线。

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