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    • 1. 发明授权
    • Expert system building method and system
    • 专家系统建设方法与制度
    • US5319740A
    • 1994-06-07
    • US664205
    • 1991-03-04
    • Hiroshi YamadaKenichi NakaraiKatsuyuki Yoshino
    • Hiroshi YamadaKenichi NakaraiKatsuyuki Yoshino
    • G06F9/44G06N5/04G06F7/28
    • G06N5/04
    • An expert system building method wherein, in an expert system which executes an inference process according to a decision tree, at least one data unit or any combination of such data units of data forming an input/output information is made. Next, a data input/output method is specified on the basis of relationship between the at least one data unit and the input/output information. Thus, data possibly needed can be stored simultaneously. The expert system can execute an inference process according to the decision tree having the expert's knowledge described as they are with no relation to the data input, and the data can be simultaneously entered in units which are easy to understand by an end user with no relation to the process of the decision tree.
    • 一种专家系统建立方法,其中在执行根据决策树的推理过程的专家系统中,进行形成输入/输出信息的数据的至少一个数据单元或这些数据单元的任何组合。 接下来,基于至少一个数据单元和输入/输出信息之间的关系来指定数据输入/输出方法。 因此,可能需要的数据可以同时存储。 专家系统可以根据具有与数据输入无关的所述专家知识的决策树来执行推理过程,并且数据可以以不相关的最终用户易于理解的单元同时输入 到决策树的过程。
    • 2. 发明授权
    • Dual mode disk controller
    • 双模盘控制器
    • US4811280A
    • 1989-03-07
    • US505107
    • 1983-06-16
    • Frederick J. BerkowitzSanford S. Brown
    • Frederick J. BerkowitzSanford S. Brown
    • G06F3/06G06F5/16G06F12/08G06F13/28G06F13/00G06F7/28G11B5/09
    • G06F3/0613G06F12/0866G06F3/064G06F3/0674
    • A dual mode disk controller is disclosed for use between a host processor and its storage medium for controlling data transfer to and from the storage medium. The data is formatted on the medium in two distinct formats, one capable of bulk fast transfers useful in a swapping operation, and the other capable of periodic slower transfers as is acceptable for file retrieval. The disk controller is designed having a small fast buffer memory for accepting information from the storage medium. File transfer data is transferred immediately without host CPU intervention, to a larger cache memory. The host CPU accesses the fast buffer memory periodically to retrieve swap transfer data while only accessing the larger cache memory when it needs to retrieve the file formatted information.
    • 公开了一种双模式盘控制器,用于在主处理器及其存储介质之间使用以控制到存储介质和从存储介质传送数据的数据。 数据在介质上以两种不同的格式格式化,一种能够在交换操作中有用的批量快速传输,另一种能够进行周期性较慢的传输,如文件检索可接受的那样。 磁盘控制器被设计成具有用于从存储介质接收信息的小型快速缓冲存储器。 文件传输数据在没有主机CPU干预的情况下立即传输到较大的缓存中。 主机CPU定期访问快速缓冲存储器以检索交换传输数据,同时只有在需要检索文件格式化信息时才访问较大的缓存。
    • 5. 发明授权
    • Electronic reading balance
    • 电子阅读平衡
    • US4347903A
    • 1982-09-07
    • US192529
    • 1980-03-10
    • Shozo YanoToshiyuki MiyakeYasuhiro FujinagaAkira KoomotoToshio KawaraAkio YagiTomohiro TsujiTadashi Nagaoka
    • Shozo YanoToshiyuki MiyakeYasuhiro FujinagaAkira KoomotoToshio KawaraAkio YagiTomohiro TsujiTadashi Nagaoka
    • G01D7/00G01G17/08G01G23/10G01G23/37G01G19/04G06F7/28
    • G01G23/10G01G17/08G01G23/3707
    • A weighing balance to provide an average weight to an object which tends to move while being weighed such as a laboratory animal. The object to be weighed is placed on a receiving pan which provides an electrical analog output signal corresponding to the weight of the object. This signal after passing through an amplifier is converted to a digital electrical signal fed to a data input control means. A level detector setting means allows an output from said control means only when the weight on the balance reaches a predetermined level. The output from the control means is fed to a memory having a plurality of registers which store this information. Coupled on one side to this memory is a comparator which is also coupled on a second side to said control means. Also coupled to said comparator means is an allowable range means, sampling time means, and average calculating means. The average calculating means feeds an output to a printer.
    • PCT No.PCT / JP79 / 00178 Sec。 371日期1980年3月10日 102(e)日期1980年2月5日PCT申请日1979年7月5日PCT公布。 公开号WO80 / 00272 日期1980年2月21日。称重平衡,以便在被称重时容易移动的物体(例如实验室动物)提供平均重量。 待称重的物体放置在接收盘上,该接收盘提供对应于物体的重量的电模拟输出信号。 通过放大器之后的该信号被转换为馈送到数据输入控制装置的数字电信号。 电平检测器设定装置只有当天平上的重量达到预定水平时才允许来自所述控制装置的输出。 来自控制装置的输出被馈送到具有存储该信息的多个寄存器的存储器。 在该存储器的一侧耦合是比较器,其也在第二侧耦合到所述控制装置。 还耦合到所述比较器装置是可允许范围装置,采样时间装置和平均计算装置。 平均计算装置将输出提供给打印机。
    • 7. 发明授权
    • Plural control memory system with multiple micro instruction readout
    • 具有多个微指令读出的多种控制存储系统
    • US4008462A
    • 1977-02-15
    • US530301
    • 1974-12-06
    • Yasunori Kanda
    • Yasunori Kanda
    • G06F9/28G06F9/22G06F9/26G06F7/28G06F13/00G11C7/00
    • G06F9/267
    • A microprogramming control system employing a plurality of low read rate control memories, for storing micro instructions, individually addressed in turn at a rate greater than the read rate of each memory. Each addressed control memory reads out a plurality of micro instructions. A selection circuit receives the plurality of micro instructions, in time shared fashion, read out in turn from each addressed control memory, then selects and gates a single micro instruction to a storage device. One portion of the selected micro instruction is designated as an address for the next micro instruction to be read out from the same control memory, and is accordingly gated to an address storage device at the input of the corresponding control memory.
    • 一种微程序控制系统,其采用多个低读速率控制存储器,用于存储微指令,依次以大于每个存储器的读取速率的速率寻址。 每个寻址控制存储器读出多个微指令。 选择电路以时间共享的方式接收多个微指令,从每个寻址的控制存储器依次读出,然后选择并将一个微指令写入存储设备。 所选择的微指令的一部分被指定为从相同的控制存储器读出的下一个微指令的地址,因此被选通到对应的控制存储器的输入端的地址存储装置。