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1. 发明授权

US06901503B2 Data processing circuits and interfaces 有权
标题翻译：数据处理电路和接口
公开(公告)号：US06901503B2
公开(公告)日：2005-05-31
申请号：US10032985
申请日：2001-10-29
申请人： Stephen John Barlow , Alistair Guy Morfey , James Digby Collier
发明人： Stephen John Barlow , Alistair Guy Morfey , James Digby Collier
IPC分类号： G06F7/57 , G06F9/30 , G06F9/302 , G06F9/38 , G06F11/267 , G06F11/36 , G06F9/315 , G06F13/40 , G06F12/04
CPC分类号： G06F7/57 , G06F1/3203 , G06F1/3237 , G06F9/30 , G06F9/30014 , G06F9/30032 , G06F9/3005 , G06F9/30083 , G06F9/30101 , G06F9/30145 , G06F9/3016 , G06F9/30167 , G06F9/322 , G06F9/324 , G06F9/3869 , G06F11/2236 , G06F11/3648 , G06F11/3656 , G06F15/7832 , Y02D10/128 , Y02D50/20
摘要： An integrated circuit contains a microprocessor core, program memory and separate data storage, together with analog and digital signal processing circuitry. The ALU is 16 bits wide, but a 32-bit shift unit is provided, using a pair of 16-bit registers. The processor has a fixed length instruction format, with an instruction set including multiply and divide operations which use the shift unit over several cycles. No interrupts are provided. external pins of the integrated circuit allow for single stepping and other debug operations, and a serial interface (SIF) which allows external communication of test dat or working data as necessary. The serial interface has four wires (SERIN, SEROUT, SERCLK, SERLOADB), allowing handshaking with a master apparatus, and allowing direct access to the memory space of the processor core, without specific program control. Within each processor cycle, the processor circuitry is divided into plural stages, and latches are interposed between the stages to minimize power consumption.
摘要翻译：集成电路包含微处理器内核，程序存储器和单独的数据存储器，以及模拟和数字信号处理电路。 ALU为16位宽，但提供32位移位单元，使用一对16位寄存器。处理器具有固定长度的指令格式，其中指令集包括在多个周期内使用移位单元的乘法和除法运算。不提供中断。集成电路的外部引脚允许单步执行和其他调试操作，以及允许外部通信测试数据或工作数据的串行接口（SIF）。串行接口有四根线（SERIN，SEROUT，SERCLK，SERLOADB），允许与主设备进行握手，并允许直接访问处理器内核的存储空间，无需特定的程序控制。在每个处理器周期内，处理器电路被分成多个级，并且锁存器插在两个级之间以使功耗最小化。

2. 发明授权

US06311263B1 Data processing circuits and interfaces 失效
标题翻译：数据处理电路和接口
公开(公告)号：US06311263B1
公开(公告)日：2001-10-30
申请号：US08809498
申请日：1997-03-24
申请人： Stephen John Barlow , Alistair Guy Morfey , James Digby Collier
发明人： Stephen John Barlow , Alistair Guy Morfey , James Digby Collier
IPC分类号： G06F13364
CPC分类号： G06F7/57 , G06F1/3203 , G06F1/3237 , G06F9/30 , G06F9/30014 , G06F9/30032 , G06F9/3005 , G06F9/30083 , G06F9/30101 , G06F9/30145 , G06F9/3016 , G06F9/30167 , G06F9/322 , G06F9/324 , G06F9/3869 , G06F11/2236 , G06F11/3648 , G06F11/3656 , G06F15/7832 , Y02D10/128 , Y02D50/20
摘要： An integrated circuit contains a microprocessor core, program memory and separate data storage, together with analogue and digital signal processing circuitry. The ALU is 16 bits wide, but a 32-bit shift unit is provided, using a pair of 16-bit registers. The processor has a fixed length instruction format, with an instruction set including multiply and divide operations which use the shift unit over several cycles. No interrupts are provided. External pins of the integrated circuit allow for single stepping and other debug operations, and a serial interface (SIF) which allows external communication of test data or working data as necessary. The serial interface has four wires (SERIN, SEROUT, SER-CLK, SERLOADB), allowing handshaking with a master apparatus, and allowing direct access to the memory space of the processor core, without specific program control. Within each processor cycle, the processor circuitry is divided into plural stages, and latches are interposed between the stages to minimize power consumption.
摘要翻译：集成电路包含微处理器内核，程序存储器和单独的数据存储器，以及模拟和数字信号处理电路。 ALU为16位宽，但提供32位移位单元，使用一对16位寄存器。处理器具有固定长度的指令格式，其中指令集包括在多个周期内使用移位单元的乘法和除法运算。不提供中断。集成电路的外部引脚允许单步和其他调试操作，以及允许外部通信测试数据或工作数据的串行接口（SIF）。串行接口有四根线（SERIN，SEROUT，SER-CLK，SERLOADB），允许与主设备进行握手，并允许直接访问处理器内核的存储空间，无需特定的程序控制。在每个处理器周期内，处理器电路被分成多个级，并且锁存器插在两个级之间以使功耗最小化。

3. 发明申请

US20130055030A1 Data Processing Apparatus and Related Methods of Debugging Processing Circuitry 审中-公开
标题翻译：数据处理装置及调试处理电路的相关方法
公开(公告)号：US20130055030A1
公开(公告)日：2013-02-28
申请号：US13244023
申请日：2011-09-23
申请人： Andrew Brian Thomas Hopkins , Stephen John Barlow , Constantine Krasic
发明人： Andrew Brian Thomas Hopkins , Stephen John Barlow , Constantine Krasic
IPC分类号： G06F11/30 , G06F11/07
CPC分类号： G06F11/348 , G06F11/3636 , G06F11/3656
摘要： A data processing apparatus, comprising processing circuitry, which in use, generates data and debug circuitry arranged to debug operation of the processing circuitry. The processing circuitry includes bus circuitry arranged to pass data at least one of into and out of the processing apparatus over a communication bus. The debug circuitry comprises monitoring circuitry arranged to monitor the data generated, in use, by the processing circuitry and generate a stream of trace elements. An interface unit is arranged to interface, using the bus circuitry, the trace elements generated by the monitoring circuitry onto the communication bus to be output, in use, from the processing apparatus using the communication bus. The interface unit comprises a controller which is arranged to control operation of the interface unit independently of the operation of the processing circuitry.
摘要翻译：一种数据处理装置，包括处理电路，其在使用中产生被配置为调试处理电路的操作的数据和调试电路。处理电路包括总线电路，其布置成通过通信总线将数据传输到处理设备中的至少一个。调试电路包括监控电路，其被布置为监视在使用中由处理电路产生的数据并产生微量元素流。接口单元布置成使用总线电路将由监视电路产生的微量元件与使用中使用通信总线的处理设备一起输出到通信总线上。接口单元包括控制器，其被配置为独立于处理电路的操作来控制接口单元的操作。

4. 发明授权

US07917766B2 Stegotext encoder and decoder 有权
公开(公告)号：US07917766B2
公开(公告)日：2011-03-29
申请号：US11869507
申请日：2007-10-09
申请人： Roger Fane Sewell , Mark St. John Owen , Stephen John Barlow , Simon Paul Long
发明人： Roger Fane Sewell , Mark St. John Owen , Stephen John Barlow , Simon Paul Long
IPC分类号： H04L9/00
CPC分类号： H04H20/31 , G06T1/0028 , G06T1/005 , G06T2200/28 , G06T2201/0052 , G06T2201/0065 , G10L19/018
摘要： The invention comprises an encoder for encoding a stegotext and a decoder for decoding the encoded stegotext, the stegotext being generated by modulating the log power spectrogram of a covertext signal with at least one key, the or each key having been added or subtracted in the log domain to the covertext power spectrogram in accordance with the data of the watermark code with which the stegotext was generated, and the modulated power spectrogram having been returned into the original domain of the covertext. The decoder carries out Fast Fourier Transformation and rectangular polar conversion of the stegotext signal so as to transform the stegotext signal into the log power spectrogram domain; subtracts in the log power domain positive and negative multiples of the key or keys from blocks of the log power spectrogram and evaluates the probability of the results of such subtractions representing an unmodified block of covertext in accordance with a predetermined statistical model.

5. 发明申请

US20080152128A1 STEGOTEXT ENCODER AND DECODER 有权
标题翻译： STEGOTEXT编码器和解码器
公开(公告)号：US20080152128A1
公开(公告)日：2008-06-26
申请号：US11869507
申请日：2007-10-09
申请人： Roger Fane Sewell , Mark St.John Owen , Stephen John Barlow , Simon Paul Long
发明人： Roger Fane Sewell , Mark St.John Owen , Stephen John Barlow , Simon Paul Long
IPC分类号： H04L9/28 , H04L17/14 , G06F17/16 , G06F17/10
CPC分类号： H04H20/31 , G06T1/0028 , G06T1/005 , G06T2200/28 , G06T2201/0052 , G06T2201/0065 , G10L19/018
摘要： The invention comprises an encoder for encoding a stegotext and a decoder for decoding the encoded stegotext, the stegotext being generated by modulating the log power spectrogram of a covertext signal with at least one key, the or each key having been added or subtracted in the log domain to the covertext power spectrogram in accordance with the data of the watermark code with which the stegotext was generated, and the modulated power spectrogram having been returned into the original domain of the covertext. The decoder carries out Fast Fourier Transformation and rectangular polar conversion of the stegotext signal so as to transform the stegotext signal into the log power spectrogram domain; subtracts in the log power domain positive and negative multiples of the key or keys from blocks of the log power spectrogram and evaluates the probability of the results of such subtractions representing an unmodified block of covertext in accordance with a predetermined statistical model.
摘要翻译：本发明包括一个编码器，用于对一个熟悉的编码器和一个解码器进行编码，该编码器通过用至少一个键调制覆盖文本信号的对数功率谱图来生成，该信号是通过在日志中被加或减根据生成了嘟嘟声的水印码的数据，将调制后的功率谱图返回到覆盖文本的原始域。解码器执行快速傅里叶变换和stegotext信号的矩形极化转换，以将stegotext信号转换成对数功率谱图域; 从对数功率谱图的块中减去对数功率域的键或键的正负的倍数，并根据预定的统计模型来评估表示未修改的覆盖文本块的这种减法的结果的概率。

6. 发明授权

US08112677B2 Method of debugging multiple processes 有权
标题翻译：调试多个进程的方法
公开(公告)号：US08112677B2
公开(公告)日：2012-02-07
申请号：US12713880
申请日：2010-02-26
申请人： Stephen John Barlow , Andrew James Bower , Andrew Brian Thomas Hopkins , Klaus Dieter McDonald-Maier
发明人： Stephen John Barlow , Andrew James Bower , Andrew Brian Thomas Hopkins , Klaus Dieter McDonald-Maier
IPC分类号： G06F11/00
CPC分类号： G06F11/364
摘要： A method of debugging a multiple concurrent processes comprising: obtaining, from each process, a plurality of events that have been processed and, if no time information is associated with each event, associating time information therewith; causing a display to display the events such that an event that has occurred in a first portion of the display associated with a first process at a first time is aligned with an event in a second portion of the display associated with a second process that has occurred at a similar time to the first time. To be accompanied, when published, by FIG. 5 of the drawings.
摘要翻译：一种调试多个并发处理的方法，包括：从每个进程获得已处理的多个事件，如果没有时间信息与每个事件相关联，则将时间信息与之相关联; 导致显示器显示事件，使得在与第一进程相关联的显示器的第一部分中发生的事件在第一时间与与已发生的第二进程相关联的显示器的第二部分中的事件对准在第一次相似的时间。陪同，当出版时，由图。附图5。

7. 发明申请

US20090190755A1 STEGOTEXT ENCODER AND DECODER 有权
标题翻译： STEGOTEXT编码器和解码器
公开(公告)号：US20090190755A1
公开(公告)日：2009-07-30
申请号：US11869539
申请日：2007-10-09
申请人： Roger Fane Sewell , Mark St. John Owen , Stephen John Barlow , Simon Paul Long
发明人： Roger Fane Sewell , Mark St. John Owen , Stephen John Barlow , Simon Paul Long
IPC分类号： H04L9/06 , H04L9/28 , H04K1/02
CPC分类号： H04H20/31 , G06T1/0028 , G06T1/005 , G06T2200/28 , G06T2201/0052 , G06T2201/0065 , G10L19/018
摘要： The invention comprises an encoder for encoding a stegotext and a decoder for decoding the encoded stegotext, the stegotext being generated by modulating the log power spectrogram of a covertext signal with at least one key, the or each key having been added or subtracted in the log domain to the covertext power spectrogram in accordance with the data of the watermark code with which the stegotext was generated, and the modulated power spectrogram having been returned into the original domain of the covertext. The decoder carries out Fast Fourier Transformation and rectangular polar conversion of the stegotext signal so as to transform the stegotext signal into the log power spectrogram domain; subtracts in the log power domain positive and negative multiples of the key or keys from blocks of the log power spectrogram and evaluates the probability of the results of such subtractions representing an unmodified block of covertext in accordance with a predetermined statistical model.
摘要翻译：本发明包括一个编码器，用于对一个熟悉的编码器和一个解码器进行编码，该编码器通过用至少一个键调制覆盖文本信号的对数功率谱图来生成，该信号是通过在日志中被加或减根据生成了嘟嘟声的水印码的数据，将调制后的功率谱图返回到覆盖文本的原始域。解码器执行快速傅里叶变换和stegotext信号的矩形极化转换，以将stegotext信号转换成对数功率谱图域; 从对数功率谱图的块中减去对数功率域的键或键的正负的倍数，并根据预定的统计模型来评估表示未修改的覆盖文本块的这种减法的结果的概率。

8. 发明申请

US20110214023A1 Method of Debugging Multiple Processes 有权
标题翻译：调试多个进程的方法
公开(公告)号：US20110214023A1
公开(公告)日：2011-09-01
申请号：US12713880
申请日：2010-02-26
申请人： Stephen John Barlow , Andrew James Bower , Andrew Brian Thomas Hopkins , Klaus Dieter McDonald-Maier
发明人： Stephen John Barlow , Andrew James Bower , Andrew Brian Thomas Hopkins , Klaus Dieter McDonald-Maier
IPC分类号： G06F11/07
CPC分类号： G06F11/364
摘要： A method of debugging a multiple concurrent processes comprising: obtaining, from each process, a plurality of events that have been processed and, if no time information is associated with each event, associating time information therewith; causing a display to display the events such that an event that has occurred in a first portion of the display associated with a first process at a first time is aligned with an event in a second portion of the display associated with a second process that has occurred at a similar time to the first time. To be accompanied, when published, by FIG. 5 of the drawings.
摘要翻译：一种调试多个并发处理的方法，包括：从每个进程获得已处理的多个事件，如果没有时间信息与每个事件相关联，则将时间信息与之相关联; 导致显示器显示事件，使得在与第一进程相关联的显示器的第一部分中发生的事件在第一时间与与已发生的第二进程相关联的显示器的第二部分中的事件对准在第一次相似的时间。陪同，当出版时，由图。附图5。

9. 发明授权

US07916862B2 Stegotext encoder and decoder 有权
标题翻译： Stegotext编码器和解码器
公开(公告)号：US07916862B2
公开(公告)日：2011-03-29
申请号：US11869539
申请日：2007-10-09
申请人： Roger Fane Sewell , Mark St. John Owen , Stephen John Barlow , Simon Paul Long
发明人： Roger Fane Sewell , Mark St. John Owen , Stephen John Barlow , Simon Paul Long
IPC分类号： H04L9/00
CPC分类号： H04H20/31 , G06T1/0028 , G06T1/005 , G06T2200/28 , G06T2201/0052 , G06T2201/0065 , G10L19/018
摘要： The invention comprises an encoder for encoding a stegotext and a decoder for decoding the encoded stegotext, the stegotext being generated by modulating the log power spectrogram of a covertext signal with at least one key, the or each key having been added or subtracted in the log domain to the covertext power spectrogram in accordance with the data of the watermark code with which the stegotext was generated, and the modulated power spectrogram having been returned into the original domain of the covertext. The decoder carries out Fast Fourier Transformation and rectangular polar conversion of the stegotext signal so as to transform the stegotext signal into the log power spectrogram domain; subtracts in the log power domain positive and negative multiples of the key or keys from blocks of the log power spectrogram and evaluates the probability of the results of such subtractions representing an unmodified block of covertext in accordance with a predetermined statistical model.
摘要翻译：本发明包括一个编码器，用于对一个熟悉的编码器和一个解码器进行编码，该编码器通过用至少一个键调制覆盖文本信号的对数功率谱图来生成，该信号是通过在日志中被加或减根据生成了嘟嘟声的水印码的数据，将调制后的功率谱图返回到覆盖文本的原始域。解码器执行快速傅里叶变换和stegotext信号的矩形极化转换，以将stegotext信号转换成对数功率谱图域; 从对数功率谱图的块中减去对数功率域的键或键的正负的倍数，并根据预定的统计模型来评估表示未修改的覆盖文本块的这种减法的结果的概率。

10. 发明授权

US07298841B2 Stegotext encoder and decoder 有权
标题翻译： Stegotext编码器和解码器
公开(公告)号：US07298841B2
公开(公告)日：2007-11-20
申请号：US10343145
申请日：2001-07-27
申请人： Roger Fane Sewell , Mark St. John Owen , Stephen John Barlow , Simon Paul Long
发明人： Roger Fane Sewell , Mark St. John Owen , Stephen John Barlow , Simon Paul Long
IPC分类号： H04L1/08 , H04L9/34 , H04L9/16
CPC分类号： H04H20/31 , G06T1/0028 , G06T1/005 , G06T2200/28 , G06T2201/0052 , G06T2201/0065 , G10L19/018
摘要： The invention comprises an encoder for encoding a stegotext and a decoder for decoding the encoded stegotext, the stegotext being generated by modulating the log power spectrogram of a covertext signal with at least one key, the or each key having been added or subtracted in the log domain to the covertext power spectrogram in accordance with the data of the watermark code with which the stegotext was generated, and the modulated power spectrogram having been returned into the original domain of the covertext. The decoder carries out Fast Fourier Transformation and rectangular polar conversion of the stegotext signal so as to transform the stegotext signal into the log power spectrogram domain; subtracts in the log power domain positive and negative multiples of the key or keys from blocks of the log power spectrogram and evaluates the probability of the results of such subtractions representing an unmodified block of covertext in accordance with a predetermined statistical model.
摘要翻译：本发明包括一个编码器，用于对一个熟悉的编码器和一个解码器进行编码，该编码器通过用至少一个键调制覆盖文本信号的对数功率谱图来生成，该信号是通过在日志中被加或减根据生成了嘟嘟声的水印码的数据，将调制后的功率谱图返回到覆盖文本的原始域。解码器执行快速傅里叶变换和stegotext信号的矩形极化转换，以将stegotext信号转换成对数功率谱图域; 从对数功率谱图的块中减去对数功率域的键或键的正负的倍数，并根据预定的统计模型来评估表示未修改的覆盖文本块的这种减法的结果的概率。

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