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1. 发明申请

US20040230765A1 Data sharing apparatus and processor for sharing data between processors of different endianness 有权
标题翻译：用于在不同字节的处理器之间共享数据的数据共享装置和处理器
公开(公告)号：US20040230765A1
公开(公告)日：2004-11-18
申请号：US10802914
申请日：2004-03-18
发明人： Kazutoshi Funahashi , Satoshi Ikawa , Masaru Nagayasu
IPC分类号： G06F012/02
CPC分类号： G06F13/4013
摘要： The data sharing apparatus in the present invention includes a first processor 10 and a second processor 20, each of a different endianness, that are both connected to the memory via the data bus, in a byte order based on the endianness of the first processor 10. It also includes an address conversion unit 21 which converts at least one lower bit of an address to indicate a reversed position of data in the data bus, and outputs the converted address to the memory, in the case where the second processor 20 performs a memory access on the shared memory for data with a smaller width than the data bus.
摘要翻译：本发明中的数据共享装置包括第一处理器10和第二处理器20，每个第一处理器10和第二处理器20都具有不同的字节顺序，它们都以基于第一处理器10的字节顺序的字节顺序经由数据总线连接到存储器它还包括一个地址转换单元21，其转换地址的至少一个低位，以指示数据总线中的数据的反向位置，并且在第二处理器20执行一个操作的情况下将转换的地址输出到存储器共享内存上的存储器访问宽度小于数据总线的数据。

2. 发明申请

US20040225861A1 Method and circuit for generating memory addresses for a memory buffer 有权
标题翻译：用于产生存储器缓冲器的存储器地址的方法和电路
公开(公告)号：US20040225861A1
公开(公告)日：2004-11-11
申请号：US10429942
申请日：2003-05-05
申请人： STMicroelectronics S.r.l.
发明人： Fabio Brognara , Marco Ferretti , Mauro De Ponti , Vittorio Peduto
IPC分类号： G06F012/02
CPC分类号： H04N1/32475 , G06F7/728 , G06K15/02 , H04N1/1911 , H04N1/32358
摘要： A method for generating sequences of memory addresses for a memory buffer having N*M locations includes making a first address and a last address of every sequence respectively equal to 0 and to N*Mnull1, assigning a first sequence of addresses, and each address but a last address of another sequence of addresses is generated by multiplying a corresponding address of a previous sequence by N, and performing a modular reduction of this product with respect to N*Mnull1. The method further includes calculating a greatest bit length of every address, and calculating an auxiliary constant as the modular reduction with respect to N*Mnull1 of the power of two raised to twice the greatest bit length. Each sequence of addresses includes storing an auxiliary parameter equal to an Nnull1th address of the current sequence, computing a first factor as the modular product with respect to N*Mnull1 of the auxiliary constant based upon a ratio between the auxiliary parameter and the power of two raised to the greatest bit length, and generating all addresses but the last of a sequence by performing the Montgomery algorithm using the first factor and an address index varying from 0 to N*Mnull2 as factors of the Montgomery algorithm, and with the quantity N*Mnull1 as modulus of the Montgomery algorithm, and the greatest bit length as the number of iterations of the Montgomery algorithm.
摘要翻译：一种用于产生具有N * M个位置的存储器缓冲器的存储器地址序列的方法包括使每个序列的第一地址和最后地址分别等于0和N * M-1，分配第一地址序列，通过将先前序列的相应地址乘以N来生成另一个地址序列的最后地址，并且相对于N * M-1执行该乘积的模块化减少。该方法还包括计算每个地址的最大比特长度，以及计算辅助常数作为相对于两倍的幂的N * M-1的模数减少提高到最大比特长度的两倍。每个地址序列包括存储等于当前序列的N + 1＆gt;地址的辅助参数，基于辅助常数的N * M-1计算第一因子作为相对于辅助常数的N * M-1的模块乘积辅助参数和两个功率提升到最大位长度，并且通过使用第一因子和从0到N * M-2变化的地址索引执行蒙哥马利算法来生成所有地址而不是序列的最后一个作为因子蒙哥马利算法，数量N * M-1作为蒙哥马利算法的模数，最大位长度作为蒙哥马利算法的迭代次数。

3. 发明申请

US20040193834A1 Method for optimizing utilization of a double-data-rate-SDRAM memory system 有权
标题翻译：优化双数据速率 - SDRAM存储系统利用率的方法
公开(公告)号：US20040193834A1
公开(公告)日：2004-09-30
申请号：US10403843
申请日：2003-03-31
发明人： Brian D. Emberling
IPC分类号： G06F012/02
CPC分类号： G06F13/1621 , G06F13/4243 , G11C7/1066 , G11C7/1072
摘要： A predictive memory performance optimizing unit for use with an interleaved memory, for example a DDR SDRAM memory, and suitable for use in a computer graphics system, among others, is described. The unit maintains a queue of pending requests for data from the memory, and prioritizes precharging and activating interleaves with pending requests. Interleaves which are in a ready state may be accessed independently of the precharging and activation of non-ready interleaves. The unit utilizes idle cycles occurring between consecutive requests to activate interleaves with pending requests.
摘要翻译：描述了一种用于交错存储器（例如DDR SDRAM存储器）并且适用于计算机图形系统等的预测存储器性能优化单元。该单元维护来自存储器的数据待处理请求的队列，并优先处理预先充电并激活具有未决请求的交错。处于就绪状态的交织可以独立于非就绪交错的预充电和激活来访问。该单元利用在连续请求之间发生的空闲周期来激活具有未决请求的交错。

4. 发明申请

US20030065973A1 Memory and method for employing a checksum for addresses of replaced storage elements 失效
标题翻译：用于将校验和用于替换的存储元件的地址的存储器和方法
公开(公告)号：US20030065973A1
公开(公告)日：2003-04-03
申请号：US09967008
申请日：2001-09-28
发明人： Joerg Vollrath , Philip Moore
IPC分类号： H04L001/22 , G06F011/10 , G06F011/16 , G06F012/02
CPC分类号： G06F11/1004 , G11C29/02 , G11C29/027 , G11C29/42 , G11C29/785
摘要： A memory includes: a memory array having a plurality of storage elements; a plurality of replacement storage elements; a plurality of address fuse units, each having a plurality of fusible links and being operable to store a replacement address, each replacement address identifying one of the storage elements of the memory array to be replaced by an associated one of the replacement storage elements and forming a respective 2m bit row or 2n bit column of a fuse array; a vector generator operable to produce a 2n bit row vector based on the rows of the fuse array and to produce a 2m bit column vector based on the columns of the fuse array; and a compression unit operable to produce a row checksum from the row vector and to produce a column checksum from the column vector.
摘要翻译：存储器包括：具有多个存储元件的存储器阵列; 多个替换存储元件; 多个地址熔丝单元，每个地址熔丝单元具有多个可熔链，并且可操作以存储替换地址，每个替换地址标识存储器阵列的存储元件之一，以被相关联的一个替换存储元件代替并形成熔丝阵列的相应的2m位行或2n位列; 矢量发生器，其可操作以基于所述熔丝阵列的行产生2n位行向量，并且基于所述熔丝阵列的列产生2m位列向量; 以及压缩单元，其可操作以从所述行向量产生行校验和，并从所述列向量产生列校验和。

5. 发明申请

US20030018874A1 Method of utilisation of a data storage array, and array controller therefor 有权
标题翻译：数据存储阵列的利用方法及其阵列控制器
公开(公告)号：US20030018874A1
公开(公告)日：2003-01-23
申请号：US10185725
申请日：2002-07-01
发明人： Mark Robert Watkins , Alastair Michael Slater , Andrew Michael Sparkes
IPC分类号： G06F012/02 , G06F012/00
CPC分类号： G06F3/0608 , G06F3/0665 , G06F3/0689
摘要： A number of virtual areas with virtual addresses of storage locations within the virtual areas are allocated to a data storage array, having a total physical storage capacity. Physical addresses are allocated by an array controller for the disc storage array to the virtual addresses only as data are to be written to the respective virtual addresses.
摘要翻译：具有虚拟区域中的存储位置的虚拟地址的多个虚拟区域被分配给具有总物理存储容量的数据存储阵列。仅当数据要写入相应的虚拟地址时，才将物理地址由磁盘存储阵列的阵列控制器分配给虚拟地址。

6. 发明申请

US20030016225A1 Selecting between double buffered stereo and single buffered stereo in a windowing system 失效
标题翻译：在窗口系统中选择双缓冲立体声和单缓冲立体声
公开(公告)号：US20030016225A1
公开(公告)日：2003-01-23
申请号：US09909235
申请日：2001-07-19
申请人： International Business Machines Corporation
发明人： George F. Ramsay III , Jeanne K. Sparlin
IPC分类号： G06F012/02 , G09G005/399 , G09G005/36
CPC分类号： G09G3/003 , G06F3/14 , G09G5/39 , G09G2360/12
摘要： A method, computer program product and system for allocating the memory space in a frame buffer. A Device Dependent Layer (DDX) of an X-server may read command line options or alternatively an option selected by a user. If the command line options or alternatively the user selectable option indicates to allocate the memory space in the frame buffer to support a particular type of stereo, e.g., double buffered stereo, single buffered stereo, then the DDX may allocate the memory space in the frame buffer accordingly. If the memory space of the frame buffer is allocated for single buffered stereo, then the extra memory space in the frame buffer from not supporting double buffered stereo may be allocated for texture and/or off screen caching.
摘要翻译：一种用于在帧缓冲器中分配存储器空间的方法，计算机程序产品和系统。 X服务器的设备相关层（DDX）可以读取命令行选项或者由用户选择的选项。如果命令行选项或用户可选择的选项指示分配帧缓冲器中的存储器空间以支持特定类型的立体声，例如双缓冲立体声，单缓冲立体声，则DDX可以在帧中分配存储器空间相应地缓冲。如果帧缓冲区的存储空间被分配给单缓冲立体声，则帧缓冲器中不支持双缓冲立体声的额外存储空间可被分配用于纹理和/或离屏缓存。

7. 发明申请

US20020169939A1 Address-generating arrangement 有权
标题翻译：地址生成安排
公开(公告)号：US20020169939A1
公开(公告)日：2002-11-14
申请号：US10139733
申请日：2002-05-06
发明人： Wolfram Drescher , Uwe Porst
IPC分类号： G06F012/02
CPC分类号： G06F9/342
摘要： An address-generating arrangement for a microprocessor has, in addition to its base address-generating unit, one or more address-generating expansion units, connected to the basic unity by an interface. The interface comprises one or more input data buses supplying data from the basic unit to the expansion unit and an output data bus supplying data from the expansion unit to the basic unit under control of the microprocessor.
摘要翻译：除了基地址生成单元之外，微处理器的地址生成装置还具有通过接口连接到基本单位的一个或多个地址生成扩展单元。该接口包括一个或多个输入数据总线，其从基本单元向扩展单元提供数据，以及输出数据总线，其在微处理器的控制下将数据从扩展单元提供给基本单元。

8. 发明申请

US20020145611A1 Video controller system with object display lists 有权
标题翻译：具有对象显示列表的视频控制器系统
公开(公告)号：US20020145611A1
公开(公告)日：2002-10-10
申请号：US10085241
申请日：2002-02-28
发明人： Thomas A. Dye , Peter D. Geiger , Manuel J. Alvarez II
IPC分类号： G06F012/02 , G06T009/00 , G06F013/00
CPC分类号： G09G5/363 , G09G5/14 , G09G5/393 , G09G5/395 , G09G5/399 , G09G2340/02 , H04N5/145
摘要： A graphics controller which performs display list-based video refresh operations that enable objects with independent frame rates to be efficiently assembled is disclosed. The graphics controller maintains a virtual display refresh list (VDRL) comprising a plurality of pointers to scan line segments in memory. The graphics controller also creates, maintains, and deletes draw display lists (DDLs) that comprise pointers to object display list subroutines (ODLs) that independently draw objects in memory. The ODLs may allocated one or more buffers in memory into which different frames of the objects are drawn. When an ODL has completed executing, the corresponding pointer in the DDL may be updated to point to the buffer location in memory that stores the newly completed object frame. The VDRL is maintained independently (and may be doubled-buffered) and is updated using the DDLs. Motion estimation may be performed by the graphics controller using the different frames of objects that are drawn into memory by the ODLs. The different object frames may also be animated by the graphics controller once they are drawn into memory. The object frames stored in memory may be compressed to conserve memory.
摘要翻译：公开了一种图形控制器，其执行基于显示列表的视频刷新操作，使具有独立帧速率的对象被有效地组装。图形控制器维护虚拟显示刷新列表（VDRL），其包括多个指针以在存储器中扫描线段。图形控制器还创建，维护和删除绘制显示列表（DDL），其中包含指向独立在内存中绘制对象的对象显示列表子程序（ODL）的指针。 ODL可以在存储器中分配一个或多个缓冲器，其中绘制对象的不同帧。当ODL完成执行时，可能会更新DDL中的相应指针，以指向存储新完成的对象帧的内存中的缓冲区位置。 VDRL独立维护（可能会被双缓冲），并使用DDL进行更新。可以由图形控制器使用由ODL吸引到存储器中的对象的不同帧来执行运动估计。图形控制器一旦绘制到存储器中，也可以对不同的对象帧进行动画化。存储在存储器中的对象帧可以被压缩以节省存储器。

9. 发明申请

US20020144075A1 Memory control system with incrementer for generating speculative addresses 失效
标题翻译：带增量器的存储器控制系统，用于产生推测地址
公开(公告)号：US20020144075A1
公开(公告)日：2002-10-03
申请号：US09823160
申请日：2001-03-29
发明人： Liewei Bao
IPC分类号： G06F012/02
CPC分类号： G06F12/0215
摘要： A memory controller includes an incrementer for predicting a next address to be asserted by a processor. The incrementer, structurally a counter, is configurable to wrap at a wrap boundary and to indicate when a predicted address crosses a page boundary if the memory is in page mode. This incrementer provides accurate predictions even where successor addresses are on different pages or, in the case of address loops, even in some cases in which the successor address is not consecutive. Thus, the number of accurate address predictions is increased, enhancing overall performance. The invention has particular applicability to signal processing applications with instructions loops that cross one or more page boundaries.
摘要翻译：存储器控制器包括用于预测由处理器断言的下一个地址的增量器。增量器，结构上是一个计数器，可配置为在包装边界包装，并指示当存储器处于页面模式时，预测地址何时跨越页面边界。即使在后续地址在不同的页面上，或者在地址循环的情况下，即使在某些情况下，后继地址不是连续的，该增量器也提供准确的预测。因此，准确地址预测的数量增加，从而提高整体性能。本发明特别适用于具有跨越一个或多个页面边界的指令循环的信号处理应用。

10. 发明申请

US20020105525A1 Method and apparatus for scrolling an image to be presented on a display unit 有权
标题翻译：用于滚动要呈现在显示单元上的图像的方法和装置
公开(公告)号：US20020105525A1
公开(公告)日：2002-08-08
申请号：US10003552
申请日：2001-10-24
发明人： Michael Abler
IPC分类号： G06F012/02 , G09G005/36
CPC分类号： G09G5/346
摘要： In order to enable the gentlest possible scrolling of an image to be presented on a display unit, without restricting the scrolling range and with a low outlay, an image area is defined that is larger than the image area that can be presented on the display unit. This larger image area is subdivided into a number of image area sections to which the image data of a corresponding memory section of a frame buffer provided for storing the image data of the image area are assigned by means of corresponding address information items.
摘要翻译：为了使能够呈现在显示单元上的图像的最轻的可能滚动，而不限制滚动范围和低的花费，定义的图像区域大于可以呈现在显示单元上的图像区域。这个较大的图像区域被细分为多个图像区域部分，其中通过相应的地址信息项分配用于存储图像区域的图像数据的帧缓冲器的相应存储器部分的图像数据。

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