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1. 发明授权

US06526481B1 Adaptive cache coherence protocols 失效
标题翻译：自适应高速缓存一致性协议
公开(公告)号：US06526481B1
公开(公告)日：2003-02-25
申请号：US09561168
申请日：2000-04-27
申请人： Xiaowei Shen , Arvind Mithal , Lawrence Rogel
发明人： Xiaowei Shen , Arvind Mithal , Lawrence Rogel
IPC分类号： C06F1200
CPC分类号： G06F12/0826 , G06F9/3004 , G06F9/30087 , G06F12/0817
摘要： A methodology for designing a distributed shared-memory system, which can incorporate adaptation or selection of cache protocols during operation, guarantees semantically correct processing of memory instructions by the multiple processors. A set of rules includes a first subset of “mandatory” rules and a second subset of “voluntary” rules such that correct operation of the memory system is provided by application of all of the mandatory rules and selective application of the voluntary rules. A policy for enabling voluntary rules specifies a particular coherent cache protocol. The policy can include various types of adaptation and selection of different operating modes for different addresses and at different caches. A particular coherent cache protocol can make use of a limited capacity directory in which some but not necessarily all caches that hold a particular address are identified in the directory. In another coherent cache protocol, various caches hold an address in different modes which, for example, affect communication between a cache and a shared memory in processing particular memory instructions.
摘要翻译：用于设计分布式共享存储器系统的方法，其可以在操作期间结合适应或选择高速缓存协议，保证了多处理器对存储器指令的语义上正确的处理。一组规则包括“强制性”规则的第一子集和“自愿”规则的第二子集，从而通过应用所有强制性规则并选择性地应用自愿规则来提供存储系统的正确操作。启用自愿规则的策略规定了特定的一致高速缓存协议。该策略可以包括各种类型的适配和针对不同地址和不同高速缓存的不同操作模式的选择。特定的一致高速缓存协议可以使用有限容量的目录，其中在目录中识别出一些但不一定所有保存特定地址的高速缓存。在另一个相干高速缓存协议中，各种高速缓存以不同的模式保存地址，这些地址例如在处理特定的存储器指令时影响高速缓存和共享存储器之间的通信。

2. 发明授权

US06571327B1 Non-aligned double word access in word addressable memory 有权
标题翻译：字可寻址存储器中的非对齐双字访问
公开(公告)号：US06571327B1
公开(公告)日：2003-05-27
申请号：US09379142
申请日：1999-08-23
申请人： Gideon Wertheizer , Eran Briman , Eli Ofek , Gil Vinitzky
发明人： Gideon Wertheizer , Eran Briman , Eli Ofek , Gil Vinitzky
IPC分类号： C06F1200
CPC分类号： G06F12/04 , G06F9/345
摘要： An apparatus which generates even addressed words and odd addressed words in a memory. The apparatus consists of a port adapted for receiving an address, one or more even units in operative communication with the port and one or more odd units in operative communication with the port. The even units output an even address and the odd units output and odd address. If the input address is even the even address is equal to the input address and if the input address is odd the even address is spaced from the input address by N addresses, where N is an odd integer. If the input address is odd, the odd address is equal to the input address and if the input address is even, the odd address is spaced from the input address by N addresses.
摘要翻译：一种在存储器中产生偶数寻址字和奇数寻址字的装置。该装置包括适于接收地址的端口，与端口可操作地通信的一个或多个偶数单元和与该端口可操作地通信的一个或多个奇数单元。偶数单位输出偶数地址，奇数单位输出和奇数地址。如果输入地址偶数地址等于输入地址，如果输入地址为奇数，偶数地址与输入地址间隔N个地址，其中N为奇整数。如果输入地址为奇数，则奇数地址等于输入地址，如果输入地址为偶数，则奇数地址与输入地址间隔N个地址。

3. 发明授权

US06493803B1 Direct memory access controller with channel width configurability support 失效
标题翻译：直接内存访问控制器，支持通道宽度配置
公开(公告)号：US06493803B1
公开(公告)日：2002-12-10
申请号：US09378873
申请日：1999-08-23
申请人： Thai H. Pham , Pratik M. Mehta , Michael S. Quimby
发明人： Thai H. Pham , Pratik M. Mehta , Michael S. Quimby
IPC分类号： C06F1200
CPC分类号： G06F13/28
摘要： A direct memory access (DMA) controller provides seven DMA channels configurable for a PC/AT compatible mode or an enhanced mode. In an enhanced mode of the DMA controller, three DMA master channels on a master DMA controller and a DMA channel on a slave DMA controller are individually configurable to be either 8-bit or 16-bit DMA channels. In addition, in the enhanced mode, a memory address can increment or decrement across a memory page boundary. The DMA controller includes a transfer count register selectively configured for 16-bit operation or 24-bit operation. The DMA controller also includes address generation logic selectively configured for 24-bit operation or 28-bit operation. In the PC/AT compatible mode, the DMA controller supports three 16-bit channels and four 8-bit channels. The DMA controller thus provides DMA channel width configurability.
摘要翻译：直接存储器访问（DMA）控制器提供可配置用于PC / AT兼容模式或增强模式的七个DMA通道。在DMA控制器的增强模式下，主DMA控制器上的三个DMA主通道和从属DMA控制器上的DMA通道可以单独配置为8位或16位DMA通道。此外，在增强模式中，存储器地址可以跨越存储器页边界递增或递减。 DMA控制器包括有选择地配置用于16位操作或24位操作的传输计数寄存器。 DMA控制器还包括有选择地配置用于24位操作或28位操作的地址生成逻辑。在PC / AT兼容模式下，DMA控制器支持三个16位通道和四个8位通道。因此，DMA控制器提供DMA通道宽度可配置性。

4. 发明授权

US06338127B1 Method and apparatus for resynchronizing a plurality of clock signals used to latch respective digital signals, and memory device using same 有权
标题翻译：用于重新同步用于锁存相应数字信号的多个时钟信号的方法和装置，以及使用它们的存储器件
公开(公告)号：US06338127B1
公开(公告)日：2002-01-08
申请号：US09143033
申请日：1998-08-28
申请人： Troy A. Manning
发明人： Troy A. Manning
IPC分类号： C06F1200
CPC分类号： G06F1/12
摘要： A system adaptively adjusts the phases of a plurality of internal clock signals, each respective internal clock signal causing a corresponding latch to store a digital signal responsive to the respective internal clock signal. The system includes a plurality of clock control circuits, each clock control circuit controlling the phase of a respective internal clock signal relative to a corresponding external clock signal responsive to a respective phase command signal. A plurality of evaluation circuits are coupled to the respective latches, each comparing the plurality of digital signals stored in the corresponding latch to expected values and generating a result signal indicating the results of this comparison. A phase selector circuit operates in a storage mode to sequentially develop a plurality of phase command signals on an output and store a corresponding result signal sequentially received on an input. The phase selector operates in an analysis mode to develop on the output a final phase command signal from the stored result signals. A plurality of storage circuits are coupled to respective clock control circuits and to the output of a selector circuit. Each storage circuit stores the final phase command signal responsive to a corresponding clock domain signal. A clock-domain control circuit develops a plurality of clock domain signals to control the evaluation, storage, and phase selector circuits to sequentially synchronize each internal clock signal. The clock-domain control circuit operates to perform partial synchronization of the clock signals after all clock signals have once been synchronized during a power-up submode of operation.
摘要翻译：系统自适应地调整多个内部时钟信号的相位，每个相应的内部时钟信号使得相应的锁存器响应于相应的内部时钟信号来存储数字信号。该系统包括多个时钟控制电路，每个时钟控制电路响应于相应的相位命令信号相对于对应的外部时钟信号控制相应的内部时钟信号的相位。多个评估电路耦合到相应的锁存器，每个锁存器将存储在相应锁存器中的多个数字信号与期望值进行比较，并产生指示该比较结果的结果信号。相位选择器电路在存储模式下工作，以在输出上顺序地产生多个相位指令信号，并存储在输入上顺序接收的相应结果信号。相位选择器在分析模式下操作以在输出端产生来自存储结果信号的最终相位指令信号。多个存储电路耦合到相应的时钟控制电路和选择器电路的输出端。每个存储电路响应于对应的时钟域信号存储最终相位指令信号。时钟域控制电路产生多个时钟域信号以控制评估，存储和相位选择器电路以顺序地同步每个内部时钟信号。时钟域控制电路在所有时钟信号在上电子模式操作期间一度被同步之后，进行时钟信号的部分同步。

5. 发明授权

US06510507B1 Page address look-up range ram 有权
标题翻译：页面地址查找范围ram
公开(公告)号：US06510507B1
公开(公告)日：2003-01-21
申请号：US09517986
申请日：2000-03-03
申请人： David Matt , Marulkar Rajendra Sadanand
发明人： David Matt , Marulkar Rajendra Sadanand
IPC分类号： C06F1200
CPC分类号： G06F12/02 , G06F11/261
摘要： A Page Address Look-up Range RAM is disclosed which allows for individual comparisons to be made on a number of consecutive addresses. The upper bits of the bus address 410 (often representing a “page”) are compared against one or more reference registers 430-437 to yield one or more “match_high”s. The lower bits of the same bus address 420 are used to look-up the value of “match_low” in a Page Look-Up RAM 440, the bit of interest corresponding to the particular “match-high” reference register i.e. 430. If both the “match_high” and “match_low” events are true, or=1, then the bus address has matched and should cause the event, otherwise not. The most cost effective implementations will have a Look-up RAM 440 with a width of a multiple of 8. This will allow comparison of the bus address against a multiple of individual pages.
摘要翻译：公开了一种页面寻址范围RAM，其允许在多个连续地址上进行单独的比较。将总线地址410的高位（通常表示“页”）与一个或多个参考寄存器430-437进行比较以产生一个或多个“match_high”。相同总线地址420的较低位用于查找页面查找RAM 440中的“match_low”值，与特定“匹配高”参考寄存器即430相关的感兴趣的位。如果两者 “match_high”和“match_low”事件为真，或= 1，则总线地址已匹配，应导致事件，否则不会。最具成本效益的实现将具有宽度为8的倍数的查找RAM 440.这将允许总线地址与单独页面的倍数进行比较。

6. 发明授权

US06460125B2 Dynamic memory clock control system and method 有权
标题翻译：动态内存时钟控制系统及方法
公开(公告)号：US06460125B2
公开(公告)日：2002-10-01
申请号：US09130746
申请日：1998-08-07
申请人： Keith Sk Lee , David Sinclair
发明人： Keith Sk Lee , David Sinclair
IPC分类号： C06F1200
CPC分类号： G06F1/324 , G06F1/3203 , G06F1/3275 , Y02D10/126 , Y02D10/13 , Y02D10/14
摘要： A memory clock control system and method facilitates power reduction on a dynamic basis by detecting memory access request loading from a number of memory access devices, such as video and graphics engines. Based on the detected memory access requirements, the system and method adaptively varies a memory clock frequency in response to determining the desired memory usage at a given point in time. The memory clock is varied based on the priority of a given memory access engine, such that the clock is kept or increased to a higher rate for high priority engines such as real-time processing engines to facilitate high performance video capture.
摘要翻译：存储器时钟控制系统和方法通过从诸如视频和图形引擎的多个存储器访问设备检测存储器访问请求加载来有助于动态地降低功率。基于检测到的存储器访问要求，响应于在给定时间点确定期望的存储器使用，系统和方法自适应地改变存储器时钟频率。存储器时钟基于给定存储器访问引擎的优先级而变化，使得时钟被保持或增加到诸如实时处理引擎的高优先级引擎的较高速率以便于高性能视频捕获。

7. 发明授权

US06446183B1 Systems and methods for persistent and robust memory management 失效
标题翻译：持久和稳健的内存管理的系统和方法
公开(公告)号：US06446183B1
公开(公告)日：2002-09-03
申请号：US09504064
申请日：2000-02-15
申请人： James R. H. Challenger , Arun K. Iyengar
发明人： James R. H. Challenger , Arun K. Iyengar
IPC分类号： C06F1200
CPC分类号： G06F12/023 , Y10S707/99953 , Y10S707/99956
摘要： A method for managing persistent storage in a memory storage system including a main memory and at least one disk memory device, in accordance with the invention, includes maintaining headers in persistent storage for a plurality of blocks wherein a header for each block includes a block size and an allocation status of the block and maintaining at least one data structure in main memory for allocating and deallocating persistent storage. A storage block is allocated by identifying the storage block by employing the at least one data structure in the main memory, modifying the at least one data structure in the main memory and assigning an allocation status for the block on disk. A storage block is deallocated by assigning an allocation status on disk for the block and modifying the at least one data structure in main memory.
摘要翻译：根据本发明的用于管理包括主存储器和至少一个盘存储器设备的存储器存储系统中的持久存储器的方法包括：为多个块维护持久存储器中的报头，其中每个块的报头包括块大小以及块的分配状态，并且维护主存储器中的至少一个数据结构，用于分配和释放持久存储。通过使用主存储器中的至少一个数据结构来识别存储块来分配存储块，修改主存储器中的至少一个数据结构并为盘上的块分配状态。通过在块的分配状态分配块并修改主存储器中的至少一个数据结构来释放存储块。

8. 发明授权

US06253285B1 Method and apparatus for minimizing dcache index match aliasing using hashing in synonym/subset processing 失效
标题翻译：使用同义词/子集处理中的散列来最小化dcache索引匹配混叠的方法和装置
公开(公告)号：US06253285B1
公开(公告)日：2001-06-26
申请号：US09116039
申请日：1998-07-15
申请人： Rahul Razdan , Richard E. Kessler , James B. Keller
发明人： Rahul Razdan , Richard E. Kessler , James B. Keller
IPC分类号： C06F1200
CPC分类号： G06F12/1054 , G06F12/0864 , G06F2212/1016 , G06F2212/655
摘要： A data caching system comprises a hashing function, a data store, a tag array, a page translator, a comparator and a duplicate tag array. The hashing function combines an index portion of a virtual address with a virtual page portion of the virtual address to form a cache index. The data store comprises a plurality of data blocks for holding data. The tag array comprises a plurality of tag entries corresponding to the data blocks, and both the data store and tag array are addressed with the cache index. The tag array provides a plurality of physical address tags corresponding to physical addresses of data resident within corresponding data blocks in the data store addressed by the cache index. The page translator translates a tag portion of the virtual address to a corresponding physical address tag. The comparator verifies a match between the physical address tag from the page translator and the plurality of physical address tags from the tag array, a match indicating that data addressed by the virtual address is resident within the data store. Finally, the duplicate tag array resolves synonym issues caused by hashing. The hashing function is such that addresses which are equivalent mod 213 are pseudo-randomly displaced within the cache. The preferred hashing function maps VA to bits of the cache index.
摘要翻译：数据缓存系统包括散列函数，数据存储器，标签阵列，页面翻译器，比较器和重复的标签阵列。散列函数将虚拟地址的索引部分与虚拟地址的虚拟页面部分组合以形成高速缓存索引。数据存储器包括用于保存数据的多个数据块。标签阵列包括与数据块相对应的多个标签条目，并且数据存储和标签阵列都用高速缓存索引寻址。标签阵列提供与驻留在由高速缓存索引寻址的数据存储器中的相应数据块内的数据的物理地址相对应的多个物理地址标签。页面翻译器将虚拟地址的标签部分转换为相应的物理地址标签。比较器验证来自页面翻译器的物理地址标签与来自标签阵列的多个物理地址标签之间的匹配，指示由虚拟地址寻址的数据驻留在数据存储中的匹配。最后，重复的标签数组解决哈希引起的同义词问题。散列函数使得等效的mod 213的地址在高速缓存内被伪随机移位。优先散列函数将VA <14,15异或13,12：6>映射到高速缓存索引的位<14：6>。

9. 发明授权

US06785794B2 Differentiated storage resource provisioning 有权
标题翻译：差异化存储资源配置
公开(公告)号：US06785794B2
公开(公告)日：2004-08-31
申请号：US10147795
申请日：2002-05-17
申请人： Jeffrey S. Chase , Ronald P. Doyle , David L. Kaminsky
发明人： Jeffrey S. Chase , Ronald P. Doyle , David L. Kaminsky
IPC分类号： C06F1200
CPC分类号： G06F3/0601 , G06F9/5011 , G06F9/505 , G06F2003/0697 , H04L67/1097
摘要： A method for enforcing a service discrimination policy in a storage system. The service discrimination policy enforcement method can include monitoring load metrics for physical resources required to access content stored within the storage system. A request to access the content stored within the storage system can be received. A corresponding guaranteed service level can be identified from the request. In consequence, a particular one of the physical resources can be selected to service the request based upon a determination that the selected physical resource can service the request while satisfying the guaranteed service level at a load indicated by the monitored load metrics.
摘要翻译：一种用于在存储系统中执行服务辨别策略的方法。服务辨别策略执行方法可以包括监视访问存储在存储系统内的内容所需的物理资源的负载度量。可以接收访问存储在存储系统内的内容的请求。可以从请求中识别相应的保证服务级别。因此，可以选择物理资源中的特定一个来基于所选择的物理资源可以在由所监视的负载度量指示的负载满足保证服务水平的情况下服务于该请求的确定来服务该请求。

10. 发明授权

US06763420B2 Method and apparatus for modifying cache address computation schemes 失效
标题翻译：用于修改缓存地址计算方案的方法和装置
公开(公告)号：US06763420B2
公开(公告)日：2004-07-13
申请号：US09903565
申请日：2001-07-13
申请人： Ole Bentz
发明人： Ole Bentz
IPC分类号： C06F1200
CPC分类号： G06F12/0802 , G06F12/0864 , G06F2212/601
摘要： A plurality of cache addressing functions are stored in main memory. A processor which executes a program selects one of the stored cache addressing functions for use in a caching operation during execution of a program by the processor.
摘要翻译：多个高速缓存寻址功能被存储在主存储器中。执行程序的处理器在处理器执行程序期间选择所存储的高速缓存寻址功能之一用于高速缓存操作。

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