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    • 1. 发明授权
    • Method for handling data transmission frames of variable length with a
channel controller and for writing them to a cyclic buffer memory
    • 用于通过信道控制器处理可变长度的数据传输帧并将其写入循环缓冲存储器的方法
    • US5375119A
    • 1994-12-20
    • US78279
    • 1993-06-22
    • Vesa Koivu
    • Vesa Koivu
    • H04L29/02H04J3/06H04L12/00H04L12/70H04L12/861H04L12/933H04L29/06H04L29/10H04Q11/04H04L12/66
    • H04L12/00H04J3/0632H04L49/108H04L49/90H04L49/9031H04L49/9042H04L2012/5604H04L2012/5672H04L69/22H04Q11/0478
    • A method for handling data transmission frames of variable length in the interface between two networks, and for writing them into a cyclic buffer memory (3) wherein the data transmission frames are made of a header field (H) containing at least control data, a data field (D) and an end field of variable length. To obtain flexible buffering, the buffer memory (3) is divided into more than one logical section, each having a header field and a data field. The indicated real length of an incoming frame is taken into account: in the buffer memory operations in such a manner that the channel decoder (4) is interrupted for each frame section which have come from the channel to the area of the buffer, whereby the channel decoder reads the frame sections to its own memory, whereby the last interrupt related to the frame is made on the basis of the indicated real length of the frame when the last section of said frame is in the buffer.
    • PCT No.PCT / FI92 / 00292 Sec。 371日期:1993年6月22日 102(e)日期1993年6月22日PCT提交1992年10月29日PCT公布。 出版物WO93 / 09623 日期:1993年5月13日。一种用于处理两个网络之间的接口中的可变长度的数据传输帧的方法,并且用于将它们写入循环缓冲存储器(3)中,其中数据传输帧由包含 至少控制数据,数据字段(D)和可变长度的结束字段。 为了获得灵活的缓冲,缓冲存储器(3)被分成多个逻辑部分,每个逻辑部分都有头部字段和数据字段。 考虑到输入帧的所指示的实际长度:在缓冲存储器操作中,以对于从信道到缓冲器的区域的每个帧部分中断信道解码器(4)的方式,由此 信道解码器将帧部分读取到其自己的存储器,由此当帧的最后一部分在缓冲器中时,基于所指示的实际长度,进行与该帧相关的最后一个中断。
    • 2. 发明授权
    • Communication systems
    • 通讯系统
    • US5406550A
    • 1995-04-11
    • US136259
    • 1993-10-15
    • Michael J. McTiffin
    • Michael J. McTiffin
    • H04J3/24H04J13/04H04L12/56H04W28/06H04W88/16H04J13/000
    • H04W88/16H04J3/247H04L2012/5604H04W28/06
    • A communication system for transmission of data from an ATM network to a mobile radio system having an interface apparatus coupled therebetween which is operative to remove from the header of each ATM cell entering the system from the network VPI and VCI data. A translator, responsive to the VPI and VCI data, appropriately codes data formed of the remainder of each cell from which the VPI and VCI data has been removed so that it will be received by a mobile user having an address as indicated by the VPI and CPI data. A second translator responsive to codes corresponding to user addresses produces corresponding VPI and VCI data. A unit for recombining the VPI and VCI data with data formed of the remainder of the cell from which it was removed is provided to thereby produce whole cells suitable for transmission from the system to a mobile terminal.
    • 一种用于从ATM网络向移动无线电系统传输数据的通信系统,其具有耦合在其间的接口装置,其可操作以从进入网络VPI和VCI数据的每个ATM信元的报头移除。 翻译器响应于VPI和VCI数据,适当地对从每个单元的剩余部分形成的数据进行适当的编码,从该VPI和VCI数据已经被去除,从而将由具有由VPI指示的地址的移动用户接收, CPI数据。 响应于与用户地址相对应的代码的第二翻译器产生相应的VPI和VCI数据。 提供用于将VPI和VCI数据与从其被去除的单元的剩余部分形成的数据重新组合的单元,从而产生适合于从系统传输到移动终端的全部小区。
    • 7. 发明授权
    • Method and apparatus for providing a serial interface between an asynchronous transfer mode (ATM) layer and a physical (PHY) layer
    • 用于在异步传输模式(ATM)层和物理(PHY)层之间提供串行接口的方法和装置
    • US06452927B1
    • 2002-09-17
    • US08581242
    • 1995-12-29
    • Craig S. Rich
    • Craig S. Rich
    • H04L1224
    • H04L12/5601H04L49/3081H04L2012/5604
    • An extender circuit provides a serial communication interface between an ATM layer and a PHY layer. The extender circuit includes a first circuit serially coupled to a second circuit. The first circuit communicates in parallel with the ATM layer, and the second circuit communicates in parallel with the PHY layer. The extender circuit additionally includes a serial link which serially transmits signals between the first and second circuits. The serial link includes a first serial link for transmitting a first serial signal from the first circuit to the second circuit, and a second serial link transmitting a second serial signal from the second circuit to the first circuit. The first circuit and the second circuit include similar architecture. The first circuit includes a parallel interface circuit for communicating in parallel with the ATM layer and a serial interface circuit coupled to the parallel interface circuit for serially communicating with the second circuit. The parallel interface circuit includes control circuitry, such as a programmable logic device, and memory circuitry, such as a first-in-first-out (FIFO) memory device. The serial interface circuit includes serializing/deserializing circuitry which includes serializing circuitry for serializing a plurality of parallel signals received from the parallel interface circuit and outputting a plurality of serial output signals. The serializing/deserializing circuitry further includes deserializing circuitry for deserializing a plurality of serial input signals to form a plurality of deserialized signals and providing the deserialized signals to the parallel interface circuit.
    • 扩展电路在ATM层和PHY层之间提供串行通信接口。 扩展器电路包括串联耦合到第二电路的第一电路。 第一电路与ATM层并行通信,第二电路与PHY层并行通信。 扩展器电路还包括在第一和第二电路之间串行发送信号的串行链路。 串行链路包括用于从第一电路向第二电路发送第一串行信号的第一串行链路,以及将第二串行信号从第二电路传输到第一电路的第二串行链路。 第一电路和第二电路包括类似的结构。 第一电路包括用于与ATM层并行通信的并行接口电路和耦合到并行接口电路的串行接口电路,用于与第二电路串联通信。 并行接口电路包括诸如可编程逻辑器件的控制电路和诸如先进先出(FIFO)存储器设备的存储器电路。 串行接口电路包括串行/反序列化电路,其包括串行化电路,用于串行从并行接口电路接收的多个并行信号并输出​​多个串行输出信号。 串行化/反序列化电路还包括反序列化电路,用于反序列化多个串行输入信号以形成多个反序列化信号并将并行接口电路提供反序列化信号。