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1. 发明授权

US10020818B1 Systems and methods for fast delta sigma modulation using parallel path feedback loops 有权
公开(公告)号：US10020818B1
公开(公告)日：2018-07-10
申请号：US15470805
申请日：2017-03-27
申请人： MY Tech, LLC
发明人： Tommy Yu , Avanindra Madisetti
IPC分类号： H03M3/00 , H03M1/06 , H03M3/02 , H04L1/00 , H04B1/40 , H03M1/12
CPC分类号： H03M3/436 , H03M1/12 , H03M3/022 , H03M3/30 , H03M3/434 , H03M3/452 , H03M3/454 , H03M3/464 , H04B1/40 , H04L1/006
摘要： An error feedback system for a delta sigma modulator is disclosed. The error feedback system has an error transfer function where at least k−1 coefficients are set to zero. This allows the error feedback system to be divided into k feedback paths that are performed in parallel at a clock speed that is 1/k of the system clock of the delta sigma modulator (i.e. the rate at which the output of the delta sigma modulator changes).

2. 发明授权

US08842029B2 Area-efficiency delta modulator for quantizing an analog signal 有权
标题翻译：用于量化模拟信号的区域效率增量调制器
公开(公告)号：US08842029B2
公开(公告)日：2014-09-23
申请号：US13788518
申请日：2013-03-07
申请人： National Chiao Tung University
发明人： Chun-Yu Wu , Yuan-Fu Lyu
IPC分类号： H03M3/00 , H03M3/02
CPC分类号： H03M3/02 , H03M3/022
摘要： The invention comprises sample-and-hold circuit and digital-to-analog converter into a differentially operational unit. In analog-to-digital conversion unit, on the premise of fixed or non-fixed quantization error, analog-to-digital converter dynamically adjusts number of bits solved or size of quantized step according to the magnitude of differential voltage between sampled input signal and previously quantized input signal, thus this invention can reduce the non-necessary power consumption from redundant code and overload of input signal. Differentially operational unit and analog-to-digital unit share the same capacitor array which has binary-weighted arrangement to reduce circuit complexity and area.
摘要翻译：本发明包括采样保持电路和数模转换器到差分操作单元中。在模拟数字转换单元中，在固定或非固定量化误差的前提下，模数转换器根据采样输入信号与采样输入信号之间的差分电压幅值动态调整量化位数或量化步长大小先前量化的输入信号，因此本发明可以减少冗余码的非必要功耗和输入信号的过载。差分操作单元和模数 - 数字单元共享相同的电容器阵列，其具有二进制加权布置以降低电路复杂性和面积。

3. 发明授权

US07098816B2 Tri-state delta codec method and system 失效
标题翻译：三态delta编解码方法和系统
公开(公告)号：US07098816B2
公开(公告)日：2006-08-29
申请号：US10908687
申请日：2005-05-23
申请人： Yu Chau Ng , Cheuk Wai Mok
发明人： Yu Chau Ng , Cheuk Wai Mok
IPC分类号： H03M5/16
CPC分类号： H03M3/022
摘要： A delta modulation method and system is provided for processing signals in a digital communications system. The method quantizes an input signal using a tri-state quantizer into a quantized value selected from a set of three different quantized values including a low value, a middle value, and a high value. The selection of the quantized value is based on a comparison between the input signal and a predicted signal of a corresponding sampling period. The method generates from the quantized value an output signal representative of the input signal, determines a predicted signal of the next sampling period, and then feeds the predicted signal of next sampling period back to the tri-state quantizer.
摘要翻译：提供了一种用于在数字通信系统中处理信号的增量调制方法和系统。该方法使用三态量化器将输入信号量化为从包括低值，中间值和高值的三个不同量化值的集合中选择的量化值。量化值的选择基于输入信号与相应采样周期的预测信号之间的比较。该方法从量化值产生表示输入信号的输出信号，确定下一个采样周期的预测信号，然后将下一采样周期的预测信号反馈给三态量化器。

4. 发明申请

US20050275574A1 TRI-STATE DELTA CODEC METHOD AND SYSTEM 失效
标题翻译：三态DELTA编解码方法和系统
公开(公告)号：US20050275574A1
公开(公告)日：2005-12-15
申请号：US10908687
申请日：2005-05-23
申请人： Yu Chau Ng , Cheuk Wai Mok
发明人： Yu Chau Ng , Cheuk Wai Mok
IPC分类号： H03M3/00 , H03M3/02
CPC分类号： H03M3/022
摘要： A delta modulation method and system is provided for processing signals in a digital communications system. The method quantizes an input signal using a tri-state quantizer into a quantized value selected from a set of three different quantized values including a low value, a middle value, and a high value. The selection of the quantized value is based on a comparison between the input signal and a predicted signal of a corresponding sampling period. The method generates from the quantized value an output signal representative of the input signal, determines a predicted signal of the next sampling period, and then feeds the predicted signal of next sampling period back to the tri-state quantizer.
摘要翻译：提供了一种用于在数字通信系统中处理信号的增量调制方法和系统。该方法使用三态量化器将输入信号量化为从包括低值，中间值和高值的三个不同量化值的集合中选择的量化值。量化值的选择基于输入信号与相应采样周期的预测信号之间的比较。该方法从量化值产生表示输入信号的输出信号，确定下一个采样周期的预测信号，然后将下一采样周期的预测信号反馈给三态量化器。

5. 发明申请

US20030058152A1 Analog/digital converter and method for controlling the same 失效
标题翻译：模拟/数字转换器及其控制方法
公开(公告)号：US20030058152A1
公开(公告)日：2003-03-27
申请号：US10254909
申请日：2002-09-26
发明人： Kan Shimizu
IPC分类号： H03M001/34 , H03M003/00
CPC分类号： H03M3/022
摘要： A method for controlling an analog/digital converter circuitry includes generating a digital signal by accumulating a predetermined increment at a predetermined time interval in accordance with a value of a first analog signal input to the analog/digital converter. The digital signal is converted to a second analog signal, the second analog signal is subtracted from the first analog signal, and a detection signal is generated in accordance with a subtraction result. An accumulation mode is selected from accumulation modes in accordance with the detection signal and accumulation is performed at the time interval and in the increment in accordance with the selected accumulation mode.
摘要翻译：一种用于控制模拟/数字转换器电路的方法包括：根据输入到模拟/数字转换器的第一模拟信号的值，以预定的时间间隔累积预定的增量来产生数字信号。数字信号被转换为第二模拟信号，从第一模拟信号中减去第二模拟信号，并且根据减法结果生成检测信号。根据检测信号从累积模式中选择累积模式，并且根据所选择的累加模式在时间间隔和增量中执行累加。

6. 发明授权

US06452522B1 Delta Modulator 失效
标题翻译： Delta调制器
公开(公告)号：US06452522B1
公开(公告)日：2002-09-17
申请号：US09403841
申请日：1999-10-25
申请人： Stefan Wahlberg
发明人： Stefan Wahlberg
IPC分类号： H03M300
CPC分类号： H03M3/022
摘要： An adaptive delta modulator has an A/D-converter controlled by a digital control signal, which is also supplied to a drift compensation logic circuit, which generates a drift compensated digital output signal by an appropriate shift operation of the applied control signal, dependent on an initially detected shift in the A/D converter.
摘要翻译：自适应增量调制器具有由数字控制信号控制的A / D转换器，其也被提供给漂移补偿逻辑电路，漂移补偿逻辑电路通过所施加的控制信号的适当的移位操作产生漂移补偿的数字输出信号，这取决于最初检测到的A / D转换器的移位。

7. 发明授权

US5790062A Delta modulator with pseudo constant modulation level 失效
标题翻译：具有伪恒定调制级的Delta调制器
公开(公告)号：US5790062A
公开(公告)日：1998-08-04
申请号：US653933
申请日：1996-05-23
申请人： Brad Darnell , Rouben Toumani , Paul Bauer
发明人： Brad Darnell , Rouben Toumani , Paul Bauer
IPC分类号： H03M3/02 , H03K13/00
CPC分类号： H03M3/022
摘要： The present invention is directed to delta modulation in which the modulation level is optimized to improve overall system performance. A delta modulator in accordance with the invention includes a step size controller having a overload detector, a step size generator and a modulation level regulator. The overload detector monitors the output serial bit stream and produces a signal indicative of whether overload conditions are present. The step size generator produces steps of varying sizes in response to an input signal. The modulation level regulator monitors the signal output from the overload detector and outputs a modulated signal when the overload detector output has reached at least a certain threshold level. The modulation level regulator output is received at the step size generator input.
摘要翻译：本发明涉及增量调制，其中调制级别被优化以提高整体系统性能。根据本发明的Δ调制器包括具有过载检测器，步长发生器和调制电平调节器的步长控制器。过载检测器监视输出串行比特流并产生指示是否存在过载条件的信号。步长发生器产生响应于输入信号而改变尺寸的步骤。调制电平调节器监视过载检测器输出的信号，并在过载检测器输出达到至少一定阈值电平时输出调制信号。在步长发生器输入端接收调制电平调节器输出。

8. 发明授权

US4612654A Digital encoding circuitry 失效
标题翻译：数字编码电路
公开(公告)号：US4612654A
公开(公告)日：1986-09-16
申请号：US644340
申请日：1984-08-27
申请人： Richard E. DeFreitas
发明人： Richard E. DeFreitas
IPC分类号： G11B20/10 , H03M3/02 , H04B14/06
CPC分类号： H03M3/022
摘要： Delta encoding circuitry of the type in which a digitally-encoded signal is determined by the difference between a present value of an input signal and a reconstructed signal representative of a past value of said input signal. The occurrence of a high or a low state in the digitally-encoded signal corresponds to an incremental change in the input signal of an amount dependent upon a reference signal determined from said digitally-encoded signal. The reference signal is increased by a positive-feedback circuit upon detection of one or more consecutive repetitions of the same digital state in the digitally-encoded signal.
摘要翻译：其中数字编码信号由输入信号的当前值与代表所述输入信号的过去值的重建信号之间的差确定的类型的增量编码电路。在数字编码信号中出现高或低状态对应于取决于从所述数字编码信号确定的参考信号的量的输入信号的增量变化。在检测到数字编码信号中相同数字状态的一个或多个连续重复时，参考信号由正反馈电路增加。

9. 发明授权

US4384278A One-bit codec with slope overload correction 失效
标题翻译：具有斜率过载校正的一位编解码器
公开(公告)号：US4384278A
公开(公告)日：1983-05-17
申请号：US285861
申请日：1981-07-22
申请人： O'Connell J. Benjamin
发明人： O'Connell J. Benjamin
IPC分类号： H03M3/02 , H03K13/22
CPC分类号： H03M3/022
摘要： In a delta modulation coder and decoder system, the disadvantageous effects of slope overload are eliminated by reversing the polarity of the feedback signal in the coder and the polarity of the reconstructed analog signal in the decoder whenever slope overload correction is required. This is accomplished by the addition, to both the coder and decoder, of control circuitry which determines whether slope overload correction is required. To make the determination, first the digital output signal of the coder is tested to determine whether its rate of change is equal to a maximum value. Second, the magnitude of the feedback signal is tested to see if it lies below a threshold value. If both these conditions are satisfied, slope overload correction is then performed.
摘要翻译：在Δ调制编码器和解码器系统中，通过在需要斜率过载校正时，通过在编码器中反转反馈信号的极性和解码器中重构的模拟信号的极性来消除斜率过载的不利影响。这是通过向编码器和解码器两者添加确定是否需要斜率过载校正的控制电路来实现的。为了确定，首先对编码器的数字输出信号进行测试，以确定其变化率是否等于最大值。其次，测试反馈信号的幅度，以查看其是否低于阈值。如果满足这两个条件，则执行斜率过载校正。

10. 发明授权

US4123709A Adaptive digital delta modulation for voice transmission 失效
标题翻译：用于语音传输的自适应数字增量调制
公开(公告)号：US4123709A
公开(公告)日：1978-10-31
申请号：US762436
申请日：1977-01-24
申请人： David E. Dodds , Andrzej M. Sendyk , Donald B. Wohlberg
发明人： David E. Dodds , Andrzej M. Sendyk , Donald B. Wohlberg
IPC分类号： H03M3/02 , H03K13/22
CPC分类号： H03M3/022
摘要： An adaptive delta modulation system wherein the input analog signal is periodically sampled and a binary bit is generated for each period, the logic level of the binary bit being dependent on whether the sampled signal is greater or smaller than the approximate signal of the previous sample. Decoding apparatus converts the stream of binary bits to approximate the analog signal by periodically charging or discharging a capacitor integrator by predetermined variable steps. The charging or discharging of the integrator during each period is determined by the logic level of the binary bits, whereas the increase or decrease in step size for successive periods is determined by successive similar signal binary bits or successive dissimilar bits, respectively. The increase or decrease in step size is achieved by storing a binary step size number S in a register and adding or subtracting a fraction of the number to or from itself during each period, producing a new step size number for each period. In addition, each added fraction may be increased by a fixed least significant number to enhance step size recovery between a transmitter and a receiver. The charge on the capacitor integrator is controlled by a pulse having a width that is directly related to the value of the S number. The pulse controls the conduction time of constant current sources which are connected to the integrator to produce the analog output signal.
摘要翻译：一种自适应增量调制系统，其中周期性地采样输入模拟信号并且为每个周期生成二进制位，二进制位的逻辑电平取决于采样信号是大于还是小于先前样本的近似信号。解码装置通过以预定的可变步长周期性地对电容器积分器进行充电或放电，将二进制比特流转换为近似模拟信号。在每个周期期间，积分器的充电或放电由二进制位的逻辑电平确定，而连续周期的步长的增加或减小分别由连续的相似信号二进制位或连续的不同位决定。通过将二进制步长数字S存储在寄存器中并在每个周期内向其自身添加或减去一部分数字来实现步长的增加或减少，从而产生每个周期的新的步长号。此外，每个添加的分数可以增加固定的最低有效数量，以增强发射机和接收机之间的步长恢复。电容积分器上的电荷由具有与S数值直接相关的宽度的脉冲控制。脉冲控制连接到积分器的恒流源的导通时间，以产生模拟输出信号。

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