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1. 发明授权

US4782458A Architecture for power of two coefficient FIR filter 失效
标题翻译：两系数FIR滤波器的功率结构
公开(公告)号：US4782458A
公开(公告)日：1988-11-01
申请号：US944295
申请日：1986-12-18
申请人： Arup K. Bhattacharya , Michael G. Cristofalo , David Koo , Amihai Miron , Imran A. Shah
发明人： Arup K. Bhattacharya , Michael G. Cristofalo , David Koo , Amihai Miron , Imran A. Shah
IPC分类号： G06F17/15 , H03H17/02 , H03H17/06 , G06F15/31
CPC分类号： H03H17/06 , G06F17/15 , H03H17/0227 , H03H2017/0232
摘要： An architecture for a very large scale integrated (VLSI) implementation of a finite imprise response (FIR) digital filter having no multipliers and a coefficient space limited to powers of two. The filter structure includes a data bus, a coefficient bus and a sum-in bus to each coefficient tap. Each tap has a coefficient and control word register which is loaded during an initialization phase of the filter. Multiplication is provided by a shifter which provides the correct power of two weighting of an input data sample. The weighted data sample at each tap is added to the output of the previous tap. This architecture results in a regular, modular structure which can be cascaded and which is programmable for various data word lengths and coefficient spaces.
摘要翻译：一种用于大规模集成（VLSI）实现的有限扩展响应（FIR）数字滤波器的架构，其没有乘法器和限制为2的幂的系数空间。滤波器结构包括数据总线，系数总线和到每个系数抽头的总和总线。每个抽头具有系数和控制字寄存器，它在滤波器的初始化阶段加载。乘法由提供输入数据样本的两个加权的正确功率的移位器提供。每个水龙头的加权数据样本将添加到先前水龙头的输出。该架构产生了可以级联的规则的模块化结构，并且可针对各种数据字长度和系数空间进行编程。

2. 发明授权

US5262974A Programmable canonic signed digit filter chip 失效
标题翻译：可编程正弦符号位滤波器芯片
公开(公告)号：US5262974A
公开(公告)日：1993-11-16
申请号：US783731
申请日：1991-10-28
申请人： John C. Hausman , Robert R. Harnden , Etan G. Cohen , Harold G. Mills
发明人： John C. Hausman , Robert R. Harnden , Etan G. Cohen , Harold G. Mills
IPC分类号： G06F7/48 , H03H17/02 , G06F7/52
CPC分类号： G06F7/4824 , H03H17/0239 , H03H17/0294 , H03H2017/0232
摘要： A programmable canonic signed digit (CSD) filter is provided which employs programmable CSD multipliers. The filter receives a digital input signal and includes a tapped delay line for providing a delay between the input samples. The filter advantageously employs a plurality of programmable CSD multipliers which receive programmable input filter coefficients and perform multiplication of the coefficient with the delayed input signal. Summation hardware is further included for summing the outputs of the plurality of multipliers to provide the filter output therefrom.
摘要翻译：提供了一种使用可编程CSD乘法器的可编程规范有序数字（CSD）滤波器。滤波器接收数字输入信号并且包括用于在输入采样之间提供延迟的抽头延迟线。滤波器有利地采用多个可编程CSD乘法器，其接收可编程输入滤波器系数并执行系数与延迟输入信号的相乘。还包括求和硬件，用于对多个乘法器的输出进行求和以从其提供滤波器输出。

3. 发明申请

US20170033964A1 REDUCING CREST FACTORS 审中-公开
标题翻译：降低创伤因素
公开(公告)号：US20170033964A1
公开(公告)日：2017-02-02
申请号：US14814157
申请日：2015-07-30
申请人： Futurewei Technologies, Inc.
发明人： Huei Yuan Shih
IPC分类号： H04L27/26 , H04L1/16
CPC分类号： H04L27/2623 , H03H17/0223 , H03H2017/0232 , H03H2017/0692 , H04B1/0475 , H04L27/2614 , H04L27/2624
摘要： The present disclosure describes methods, systems, and computer program products for a reducing crest factors. An input signal is received. The input signal includes a clipping signal that reduces a peak amplitude of a source signal based on a predetermined clipping level. The input signal is transposed to a plurality of transposed signals using a plurality of multipliers. A feedback signal is generated based on the plurality of transposed signals using a first plurality of delay taps. A windowing signal is generated based on the feedback signal. The windowing signal is used to reduce a crest factor of the source signal.
摘要翻译：本公开描述了用于降低波峰因数的方法，系统和计算机程序产品。接收输入信号。输入信号包括基于预定削波电平降低源信号的峰值幅度的限幅信号。使用多个乘法器将输入信号转置到多个转置信号。使用第一多个延迟抽头基于多个转置信号产生反馈信号。基于反馈信号生成开窗信号。加窗信号用于降低源信号的波峰因数。

4. 发明授权

US07680872B2 Canonical signed digit (CSD) coefficient multiplier with optimization 失效
标题翻译：经典有符号数（CSD）系数乘法器与优化
公开(公告)号：US07680872B2
公开(公告)日：2010-03-16
申请号：US11032920
申请日：2005-01-11
申请人： Alon Saado
发明人： Alon Saado
IPC分类号： G06F7/52
CPC分类号： G06F7/5332 , G06F7/5443 , H03H17/0226 , H03H2017/0232
摘要： An apparatus comprising an address generation circuit, a lookup table, a multiplexer and an output circuit. The address generation circuit may be configured to generate a series of addresses. The lookup table may be configured to generate one or more coefficients in response to the addresses. The multiplexer circuit may be configured to generate one or more shifted values in response to (i) the coefficients and (ii) the one or more operands. The output circuit may be configured to generate an output signal by combining one or more component values in response to said shifted values. The coefficients are grouped as one over power of 2 components into mutually exclusive groups.
摘要翻译：一种包括地址生成电路，查找表，多路复用器和输出电路的装置。地址生成电路可以被配置为生成一系列地址。查找表可以被配置为响应于地址生成一个或多个系数。多路复用器电路可以被配置为响应于（i）系数和（ii）一个或多个操作数而产生一个或多个移位值。输出电路可以被配置为通过响应于所述偏移值组合一个或多个分量值来产生输出信号。这些系数被分组为2个分量的功率作为互斥组。

5. 发明申请

US20060155793A1 Canonical signed digit (CSD) coefficient multiplier with optimization 失效
标题翻译：经典有符号数（CSD）系数乘法器与优化
公开(公告)号：US20060155793A1
公开(公告)日：2006-07-13
申请号：US11032920
申请日：2005-01-11
申请人： Alon Saado
发明人： Alon Saado
IPC分类号： G06F17/10
CPC分类号： G06F7/5332 , G06F7/5443 , H03H17/0226 , H03H2017/0232
摘要： An apparatus comprising an address generation circuit, a lookup table, a multiplexer and an output circuit. The address generation circuit may be configured to generate a series of addresses. The lookup table may be configured to generate one or more coefficients in response to the addresses. The multiplexer circuit may be configured to generate one or more shifted values in response to (i) the coefficients and (ii) the one or more operands. The output circuit may be configured to generate an output signal by combining one or more component values in response to said shifted values. The coefficients are grouped as one over power of 2 components into mutually exclusive groups.
摘要翻译：一种包括地址生成电路，查找表，多路复用器和输出电路的装置。地址生成电路可以被配置为生成一系列地址。查找表可以被配置为响应于地址生成一个或多个系数。多路复用器电路可以被配置为响应于（i）系数和（ii）一个或多个操作数而产生一个或多个移位值。输出电路可以被配置为通过响应于所述偏移值组合一个或多个分量值来产生输出信号。这些系数被分组为2个分量的功率作为互斥组。

6. 发明授权

US3521042A Simplified digital filter 失效
标题翻译：简化数字滤波器
公开(公告)号：US3521042A
公开(公告)日：1970-07-21
申请号：US3521042D
申请日：1967-07-19
申请人： IBM
发明人： BLERKOM RICHARD VAN , FREEMAN DON G , WARD RICHARD J
IPC分类号： G06F7/52 , H03H17/06 , G06F7/38 , G01V1/28
CPC分类号： G06F7/5334 , H03H17/06 , H03H2017/0232

7. 发明申请

US20030195913A1 Shared multiplication for constant and adaptive digital filters 审中-公开
标题翻译：恒定和自适应数字滤波器的共享乘法
公开(公告)号：US20030195913A1
公开(公告)日：2003-10-16
申请号：US10118635
申请日：2002-04-10
发明人： Charles Douglas Murphy
IPC分类号： G06F007/52
CPC分类号： G06F7/5334 , H03H17/0226 , H03H2017/0232 , H03H2218/085
摘要： A machine or method used for reducing the implementation cost of digital filters that use multiplication operations. For each new input, a small look-up table of products is computed and stored. Weighting of the inputs when computing digital filter outputs can be accomplished using look-up table access, shifting, and addition. The invention can be used for constant filters or for adaptive filters. With constant filter coefficients, a small look-up table which exploits the properties of the various coefficient representations as a group is possible. With adaptive filters, a larger table may be needed, but can be used to reduce the multiplication cost of both filter output computation and filter adaptation. The invention is particularly useful in technologies where general multiplication is costly, such as field programmable gate arrays, application specific integrated circuits, and software running on general-purpose microprocessors. The invention can be used for high-precision computations without the need for large look-up tables. The invention can lead to digital filter implementation with reduced chip space, computation time, and power consumptions relative to implementations that do not share processing among multipliers.
摘要翻译：用于降低使用乘法运算的数字滤波器的实现成本的机器或方法。对于每个新的输入，计算并存储一个小的产品查询表。计算数字滤波器输出时输入的权重可以通过查询表访问，移位和相加来完成。本发明可用于恒定滤波器或自适应滤波器。利用恒定的滤波器系数，可以将利用各种系数表示的属性作为一组的小型查找表是可能的。使用自适应滤波器，可能需要较大的表，但可用于降低滤波器输出计算和滤波器适配的乘法成本。本发明特别适用于一般乘法费用高昂的技术，例如现场可编程门阵列，专用集成电路和在通用微处理器上运行的软件。本发明可用于高精度计算，而不需要大型查找表。相对于不在乘法器之间共享处理的实现，本发明可以导致数字滤波器实现，减少了芯片空间，计算时间和功耗。

8. 发明授权

US5928314A Digital filter having a substantially equal number of negative and positive weighting factors 失效
标题翻译：具有基本上相等数量的负和正加权因子的数字滤波器
公开(公告)号：US5928314A
公开(公告)日：1999-07-27
申请号：US709454
申请日：1996-09-05
申请人： Marcellinus J. M. Pelgrom , Stefan E. J. Menten
发明人： Marcellinus J. M. Pelgrom , Stefan E. J. Menten
IPC分类号： H03H17/00 , H03H17/02 , H03H17/06 , G06F17/10
CPC分类号： H03H17/0219 , H03H17/023 , H03H17/06 , H03H2017/0232
摘要： In a digital filter in which coefficients are realised using power of two weighting factors, it can occur that due to rounding errors the output signal shows some inaccuracies. By decomposing the filter coefficients into powers of two in such a way that most powers of two have a counterpart with an opposite sign, the rounding errors tend to cancel, resulting in a more accurate filter.
摘要翻译：在使用两个加权因子的功率实现系数的数字滤波器中，可能发生由于舍入误差导致的输出信号显示一些不准确。通过将滤波器系数分解为2的幂，使得大部分功率具有相反符号的对应方式，舍入误差趋向于消除，导致更准确的滤波器。

9. 发明授权

US4843582A Digital filter in which linear combinations of powers of two are converted to binary numbers using wallace trees 失效
标题翻译：数字滤波器，其中两个功率的线性组合使用华莱士树转换为二进制数
公开(公告)号：US4843582A
公开(公告)日：1989-06-27
申请号：US58294
申请日：1987-06-05
申请人： Berthold Heck , Joachim Speidel
发明人： Berthold Heck , Joachim Speidel
IPC分类号： H03H15/00 , G06F7/48 , G06F7/544 , G06F17/10 , H03H17/02 , H03H17/06
CPC分类号： H03H17/06 , G06F7/4824 , G06F7/5443 , H03H2017/0232
摘要： A digital filter having K coefficients h(k) processes code words x(n-k), represented in the binary codes, of an input signal bit-parallel and uses filter coefficients h(k) represented in the CSD code. Substituting in the filter equation ##EQU1## the representation of the coefficients in the CSD code and the representation of the input code words in the binary code, the problem of converting a linear combination of powers of two, having arbitrary integral coefficients, into a binary number will occur repeatedly. Carrying out this conversion by means of cascades of Wallace Trees terminated by adders for two binary numbers results in a digital filter that is suitable for sampling rates up to 20 MHz and that can also be realized without any difficulty when an excess of 25 coefficients is needed for adhering to the required filter characteristic.
摘要翻译：具有K个系数h（k）的数字滤波器处理并行的输入信号的二进制码中的码字x（n-k），并使用CSD码中表示的滤波器系数h（k）。在滤波器方程式中代入CSD码中的系数的表示和二进制码中的输入码字的表示，将具有任意积分系数的两个幂的线性组合转换成二进制的问题号码会重复出现。通过用两个二进制数字加法器终止的华莱士树的级联来实现这一转换，得到了一种数字滤波器，适用于高达20MHz的采样率，并且当需要超过25个系数时也可以毫无困难地实现这一转换以满足所需的过滤特性。

10. 发明授权

US3521041A Digital filters 失效
标题翻译：数字滤波器
公开(公告)号：US3521041A
公开(公告)日：1970-07-21
申请号：US3521041D
申请日：1967-07-19
申请人： IBM
发明人： BLERKOM RICHARD VAN , FREEMAN DON G
IPC分类号： G06F7/52 , H03H17/06 , G06F7/38 , G01V1/28
CPC分类号： G06F7/5334 , H03H17/06 , H03H2017/0232

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