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1. 发明授权

US10084507B2 Receiver for use in an ultra-wideband communication system 有权
公开(公告)号：US10084507B2
公开(公告)日：2018-09-25
申请号：US14290956
申请日：2014-05-29
申请人： Decawave Limited
发明人： Michael McLaughlin , Ciaran McElroy , Sinbad Wilmot , Tony Proudfoot
IPC分类号： H03M1/12 , H04B1/7097 , H04B1/7073 , H04B1/709 , H04B1/7163 , G06F17/15 , H03D3/00 , H04L27/38
CPC分类号： H04B1/7097 , G06F17/15 , H03D3/00 , H04B1/7073 , H04B1/709 , H04B1/71637 , H04L27/38
摘要： In an ultra-wideband (“UWB”) receiver, a received UWB signal is periodically digitized as a series of ternary samples. The samples are continuously correlated with a predetermined preamble sequence to develop a correlation value. When the value exceeds a predetermined threshold, indicating that the preamble sequence is being received, estimates of the channel impulse response (“CIR”) are developed. When a start-of-frame delimiter (“SFD”) is detected, the best CIR estimate is provided to a channel matched filter (“CMF”) substantially to filter channel-injected noise.

2. 发明授权

US09893916B2 Methods and apparatus for performing a high speed phase demodulation scheme using a low bandwidth phase-lock loop 有权
公开(公告)号：US09893916B2
公开(公告)日：2018-02-13
申请号：US15200706
申请日：2016-07-01
申请人： Texas Instruments Incorporated
发明人： Subhashish Mukherjee , Abhijit Anant Patki , Madhulatha Bonu , Kumar Anurag Shrivastava
IPC分类号： H04L7/00 , H04L27/22 , H03L7/087 , H03L7/113 , H03K19/21 , H04L7/033
CPC分类号： H04L27/22 , H03D3/00 , H03K19/21 , H03L7/081 , H03L7/087 , H03L7/113 , H04L7/0087 , H04L7/0331 , H04L27/2271
摘要： Methods and apparatus for performing a high speed phase demodulation scheme using a low bandwidth phase-lock loop are disclosed. An example apparatus includes a low bandwidth phase lock loop to lock to a data signal at a first phase, the data signal capable of oscillating at the first phase or a second phase; and output a first output signal at the first phase and a second output signal at the second phase, the first output signal or the second output signal being utilized in a feedback loop of the low bandwidth phase lock loop. The example apparatus further includes a fast phase change detection circuit coupled to the low bandwidth phase lock loop to determine whether the data signal is oscillating at the first phase or the second phase; when the data signal is oscillating at the first phase, output a first logic value; and when the data signal is oscillating at the second phase, output a second logic value, the output of the fast phase change detection circuit being used to determine whether the first output signal or the second output signal will be utilized in the feedback loop of the low bandwidth phase lock loop.

3. 发明申请

US20170302225A1 DIGITAL ISOLATOR 审中-公开
公开(公告)号：US20170302225A1
公开(公告)日：2017-10-19
申请号：US15640168
申请日：2017-06-30
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Anant Shankar Kamath , Sreeran N S
IPC分类号： H03D3/00 , H04L25/02
CPC分类号： H03D3/00 , H04L25/0268
摘要： Several circuits and methods for transferring an input data signal in a digital isolator are disclosed. In an embodiment, the digital isolator includes an isolation element, input circuit, and output circuit. The isolation element includes at least one input node and at least one output node, the input circuit is electronically coupled to the input node and generates modulated differential data signals based on modulating the input data signal on a carrier signal. The input circuit operates using a first supply voltage with respect to a first ground. The output circuit is electronically coupled to the output node to receive the modulated differential data signals, operates using a second supply voltage with respect to a second ground and includes a frequency-shift keying demodulator configured to generate a demodulated data signal in response to detection of presence of the carrier signal. The output circuit further generates an output data signal.

4. 发明授权

US09484988B2 Power supply device, power receiving device, charging system, and obstacle detection method 有权
标题翻译：电源装置，受电装置，充电系统和障碍物检测方法
公开(公告)号：US09484988B2
公开(公告)日：2016-11-01
申请号：US14378240
申请日：2013-02-08
申请人： Panasonic Corporation
发明人： Satoshi Nakaya , Tsuyoshi Nishio
IPC分类号： H02J7/00 , H04B5/00 , H02J5/00 , H01F38/14 , H03C1/00 , H03C3/00 , H03D1/00 , H03D3/00 , H02J7/02
CPC分类号： H04B5/0037 , H01F38/14 , H02J5/005 , H02J7/025 , H02J50/10 , H02J50/60 , H03C1/00 , H03C3/00 , H03D1/00 , H03D3/00
摘要： Provided are a power supply device, a power receiving device, a charging system, and an obstacle detection method that obtain a sufficient obstacle detection sensitivity even when an obstacle is small. A modulation unit (202) performs amplitude modulation or phase modulation on a test data sequence output from a test data sequence storage unit (201). A power control unit (203) generates, according to an instruction from a determination unit (204), a power control signal for increasing the power level of the test data sequence every time when the test data sequence is transmitted. The determination unit (204) determines whether there is an obstacle between the power receiving device and the power supply device based on whether the test data sequence output from the test data sequence storage unit (201) coincides with the test data sequence output from a power-transmitting-side receiving circuit (124).
摘要翻译：提供即使当障碍物小时也能够获得足够的障碍物检测灵敏度的电源装置，受电装置，充电系统和障碍物检测方法。调制单元（202）对从测试数据序列存储单元（201）输出的测试数据序列进行幅度调制或相位调制。功率控制单元（203）根据来自确定单元（204）的指令产生用于在每次发送测试数据序列时增加测试数据序列的功率电平的功率控制信号。确定单元（204）基于从测试数据序列存储单元（201）输出的测试数据序列是否与从电源输出的测试数据序列一致，确定在电力接收设备和电源设备之间是否存在障碍物 - 发射侧接收电路（124）。

5. 发明申请

US20150002090A1 POWER SUPPLY DEVICE, POWER RECEIVING DEVICE, CHARGING SYSTEM, AND OBSTACLE DETECTION METHOD 有权
标题翻译：电源装置，电力接收装置，充电系统和OBSTACLE检测方法
公开(公告)号：US20150002090A1
公开(公告)日：2015-01-01
申请号：US14378240
申请日：2013-02-08
申请人： Panasonic Corporation
发明人： Satoshi Nakaya , Tsuyoshi Nishio
IPC分类号： H04B5/00 , H03D3/00 , H02J7/02 , H03C3/00 , H01F38/14 , H03D1/00 , H03C1/00
CPC分类号： H04B5/0037 , H01F38/14 , H02J5/005 , H02J7/025 , H02J50/10 , H02J50/60 , H03C1/00 , H03C3/00 , H03D1/00 , H03D3/00
摘要： Provided are a power supply device, a power receiving device, a charging system, and an obstacle detection method that obtain a sufficient obstacle detection sensitivity even when an obstacle is small. A modulation unit (202) performs amplitude modulation or phase modulation on a test data sequence output from a test data sequence storage unit (201). A power control unit (203) generates, according to an instruction from a determination unit (204), a power control signal for increasing the power level of the test data sequence every time when the test data sequence is transmitted. The determination unit (204) determines whether there is an obstacle between the power receiving device and the power supply device based on whether the test data sequence output from the test data sequence storage unit (201) coincides with the test data sequence output from a power-transmitting-side receiving circuit (124).
摘要翻译：提供即使当障碍物小时也能够获得足够的障碍物检测灵敏度的电源装置，受电装置，充电系统和障碍物检测方法。调制单元（202）对从测试数据序列存储单元（201）输出的测试数据序列进行幅度调制或相位调制。功率控制单元（203）根据来自确定单元（204）的指令产生用于在每次发送测试数据序列时增加测试数据序列的功率电平的功率控制信号。确定单元（204）基于从测试数据序列存储单元（201）输出的测试数据序列是否与从电源输出的测试数据序列一致，确定在电力接收设备和电源设备之间是否存在障碍物 - 发射侧接收电路（124）。

6. 发明申请

US20140347122A1 PERIODICALLY RESETTING INTEGRATION ANGLE DEMODULATION DEVICE AND METHOD USING THE SAME 有权
标题翻译：定期整定角度解调装置及使用其的方法
公开(公告)号：US20140347122A1
公开(公告)日：2014-11-27
申请号：US14077458
申请日：2013-11-12
申请人： NATIONAL CHIAO TUNG UNIVERSITY
发明人： HAO-CHIAO HONG , YUN-TSE CHEN , SHAO-FENG HUNG
IPC分类号： H03D3/00
CPC分类号： H03D3/00 , G01J9/02 , G01J9/04 , H03D3/04 , H03D7/161 , H03D2200/0021 , H03D2200/0049
摘要： A periodically resetting integration angle demodulation device and a method using the same is disclosed, which uses a waveform multiplier and a periodically resetting integrator to modulate a continuous-time angle modulation signal into a discrete-time signal. The waveform multiplier multiplies the continuous-time angle modulation signal by a square wave signal whose frequency is integer times a carrier frequency, and then transmits the continuous-time angle modulation signal to a periodically resetting integrated circuit. The periodically resetting integrated circuit performs integration during a carrier period to generate a discrete-time angle modulation output signal. The present invention can greatly reduce the difficulty for designing an optical sensing system in the front end without limiting a modulation depth. Besides, the present invention achieves a small volume, high speed, high sensitivity, high reliability, high performance and high condition-adapting properties.
摘要翻译：公开了周期性复位积分角解调装置及其使用方法，其使用波形乘法器和周期性复位积分器将连续时间角调制信号调制成离散时间信号。波形乘法器将连续时间角调制信号乘以频率为载波频率的整数倍的方波信号，然后将连续时间角调制信号发送到周期性复位集成电路。周期复位集成电路在载波周期期间执行积分以产生离散时间角调制输出信号。本发明可以大大降低在前端设计光学感测系统的难度，而不会限制调制深度。此外，本发明实现了小体积，高速度，高灵敏度，高可靠性，高性能和高条件适应性能。

7. 发明申请

US20140273898A1 Frequency Selective Logarithmic Amplifier With Intrinsic Frequency Demodulation Capability 有权
标题翻译：具有固有频率解调能力的频率选择对数放大器
公开(公告)号：US20140273898A1
公开(公告)日：2014-09-18
申请号：US14213972
申请日：2014-03-14
申请人： DockOn AG
发明人： Forrest Brown , Patrick Rada , Alexandre Dupuy
IPC分类号： H04B1/16
CPC分类号： H04W52/52 , G06G7/24 , H03D1/18 , H03D3/00 , H03D11/04 , H03D11/08 , H03D2200/006 , H04B1/26 , H04L7/033 , H04L27/14
摘要： A regenerative selective logarithmic detector amplifier (LDA) can have integrated FM demodulation capabilities. It can receive a wired or wireless FM modulated signal and amplify or demodulate it with high sensitivity, high skirt ratio and minimized noise when compared to the prior art. When used in conjunction with other circuits such as a PLL or mixer, it can improve interference rejection and frequency selectivity and be locked on a precise channel in frequency and phase. The LDA produces intermittent oscillations that are self-quenched when reaching a given threshold. It also embeds the circuitry to perform direct FM discrimination. FM demodulation process is completed by a simple analog or digital frequency to voltage converter. This plus the fact that the instantaneous regeneration gain is low-medium permit to detect signals of small amplitudes buried in the noise.
摘要翻译：再生选择对数检波放大器（LDA）可以集成FM解调功能。与现有技术相比，它可以接收有线或无线FM调制信号，并以高灵敏度，高裙边比和最小化的噪声放大或解调它。当与其他电路（如PLL或混频器）结合使用时，可以提高干扰抑制和频率选择性，并锁定在频率和相位上的精确信道上。 LDA产生间歇振荡，当达到给定的阈值时，它们会自我淬火。它还嵌入电路以执行直接的FM鉴别。 FM解调过程由简单的模拟或数字频率到电压转换器完成。这加上瞬时再生增益是低介质允许检测埋在噪声中的小幅度信号的事实。

8. 发明授权

US08760334B2 Receiver for use in an ultra-wideband communication system 有权
标题翻译：接收机用于超宽带通信系统
公开(公告)号：US08760334B2
公开(公告)日：2014-06-24
申请号：US13775282
申请日：2013-02-25
申请人： Michael McLaughlin , Ciaran McElroy , Sinbad Wilmot , Tony Proudfoot
发明人： Michael McLaughlin , Ciaran McElroy , Sinbad Wilmot , Tony Proudfoot
IPC分类号： H03M1/12
CPC分类号： H04B1/7097 , G06F17/15 , H03D3/00 , H04B1/7073 , H04B1/709 , H04B1/71637 , H04L27/38
摘要： In an ultra-wideband (“UWB”) receiver, a received UWB signal is periodically digitized as a series of ternary samples. The samples are continuously correlated with a predetermined preamble sequence to develop a correlation value. When the value exceeds a predetermined threshold, indicating that the preamble sequence is being received, estimates of the channel impulse response (“CIR”) are developed. When a start-of-frame delimiter (“SFD”) is detected, the best CIR estimate is provided to a channel matched filter (“CMF”) substantially to filter channel-injected noise.
摘要翻译：在超宽带（“UWB”）接收机中，接收的UWB信号被周期性地数字化为一系列三进制样本。样本与预定的前同步码序列连续相关，以产生相关值。当该值超过预定阈值时，指示正在接收前导码序列，则开发出信道脉冲响应（“CIR”）的估计。当检测到帧起始定界符（“SFD”）时，将最佳CIR估计提供给信道匹配滤波器（“CMF”），以基本上滤除通道注入噪声。

9. 发明申请

US20130058384A1 Frequency Multiplying Transceiver 有权
标题翻译：频率乘法收发器
公开(公告)号：US20130058384A1
公开(公告)日：2013-03-07
申请号：US13636056
申请日：2011-03-23
申请人： Brian Patrick Otis , Jagdish Narayan Pandey
发明人： Brian Patrick Otis , Jagdish Narayan Pandey
IPC分类号： H04B1/38 , H04L27/22 , H04L27/06
CPC分类号： H04B1/16 , G06F7/68 , H03C3/00 , H03D3/00 , H03K3/0315 , H03K5/00006 , H04B1/38
摘要： Described herein is a wireless transceiver and related method that enables ultra low power transmission and reception of wireless communications. In an example embodiment of the wireless transceiver, the wireless transceiver receives a first-reference signal having a first-reference frequency. The wireless transceiver then uses the first-reference signal to injection lock a local oscillator, which provides a set of oscillation signals each having an oscillation frequency that is equal to the first-reference frequency, and each having equally spaced phases. Then the wireless transceiver combines the set of oscillation signals into an output signal having an output frequency that is one of (i) a multiple of the first-reference frequency (in accordance with a transmitter implementation) or (ii) a difference of (a) a second-reference frequency of a second-reference signal and (b) a multiple of the first- reference frequency (in accordance with a receiver implementation).
摘要翻译：这里描述了能够实现无线通信的超低功率发送和接收的无线收发器和相关方法。在无线收发器的示例实施例中，无线收发器接收具有第一参考频率的第一参考信号。然后，无线收发器使用第一参考信号来注入锁定本地振荡器，该本地振荡器提供一组振荡信号，每个振荡信号具有等于第一参考频率的振荡频率，并且每个具有相等间隔的相位。然后无线收发器将该组振荡信号组合成具有输出频率的输出信号，输出频率是（i）第一参考频率的倍数（根据发射机实现）之一或（ii）差异（a ）第二参考信号的第二参考频率和（b）第一参考频率的倍数（根据接收机实现）。

10. 发明授权

US08149952B2 Multi-mode receiver 有权
标题翻译：多模式接收机
公开(公告)号：US08149952B2
公开(公告)日：2012-04-03
申请号：US10696626
申请日：2003-10-29
申请人： Bala Ramachandran , Aravind Loke
发明人： Bala Ramachandran , Aravind Loke
IPC分类号： H03K9/00 , H04L25/06 , H04J3/16 , H04J3/22 , H04B7/216
CPC分类号： H03D3/00 , H04B1/707 , H04L27/0008
摘要： A multi-mode receiver system for processing signals based on a plurality of systems is disclosed. Embodiments of the invention provide for a shared architecture for processing baseband signals corresponding to a plurality of systems.
摘要翻译：公开了一种用于处理基于多个系统的信号的多模式接收机系统。本发明的实施例提供了一种用于处理对应于多个系统的基带信号的共享架构。

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