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1. 发明授权

US08103899B2 Nonvolatile memory system 有权
标题翻译：非易失性存储器系统
公开(公告)号：US08103899B2
公开(公告)日：2012-01-24
申请号：US12245203
申请日：2008-10-03
申请人： Shigemasa Shiota , Hiroyuki Goto , Hirofumi Shibuya , Fumio Hara , Kinji Mitani
发明人： Shigemasa Shiota , Hiroyuki Goto , Hirofumi Shibuya , Fumio Hara , Kinji Mitani
IPC分类号： G06F11/00
CPC分类号： G11C16/349
摘要： A memory system permitting a number of alternative memory blocks to be made ready in order to extend the rewritable life and thereby contributing to enhanced reliability of information storage is to be provided. The memory system is provided with a nonvolatile memory having a plurality of data blocks in predetermined physical address units and a controller for controlling the nonvolatile memory in response to an access request from outside. Each of the data blocks has areas for holding a rewrite count and error check information regarding each data area. The controller, in a read operation on the nonvolatile memory, checks for any error in the area subject to the read according to error check information and, when there is any error, if the rewrite count is greater than a predetermined value, will replace the pertinent data block with another data block or if it is not greater, correct data in the data block pertaining to the error.
摘要翻译：提供允许许多替代存储器块准备好以延长可重写寿命并由此有助于提高信息存储的可靠性的存储器系统。该存储器系统具有非易失性存储器，该非易失性存储器具有预定物理地址单元中的多个数据块，以及用于响应于来自外部的访问请求来控制该非易失性存储器的控制器。每个数据块具有用于保存关于每个数据区的重写计数和错误检查信息的区域。控制器在非易失性存储器中的读取操作中，根据错误检查信息检查受读取区域的任何错误，并且当存在任何错误时，如果重写计数大于预定值，则将替换与另一个数据块相关的数据块，或者如果不大于数据块，则与错误相关的数据块中的数据正确。

2. 发明申请

US20090037767A1 NONVOLATILE MEMORY SYSTEM 有权
标题翻译：非易失性存储系统
公开(公告)号：US20090037767A1
公开(公告)日：2009-02-05
申请号：US12245203
申请日：2008-10-03
申请人： SHIGEMASA SHIOTA , Hiroyuki Goto , Hirofumi Shibuya , Fumio Hara , Kinji Mitani
发明人： SHIGEMASA SHIOTA , Hiroyuki Goto , Hirofumi Shibuya , Fumio Hara , Kinji Mitani
IPC分类号： G06F11/00
CPC分类号： G11C16/349
摘要： A memory system permitting a number of alternative memory blocks to be made ready in order to extend the rewritable life and thereby contributing to enhanced reliability of information storage is to be provided. The memory system is provided with a nonvolatile memory having a plurality of data blocks in predetermined physical address units and a controller for controlling the nonvolatile memory in response to an access request from outside. Each of the data blocks has areas for holding a rewrite count and error check information regarding each data area. The controller, in a read operation on the nonvolatile memory, checks for any error in the area subject to the read according to error check information and, when there is any error, if the rewrite count is greater than a predetermined value, will replace the pertinent data block with another data block or if it is not greater, correct data in the data block pertaining to the error.
摘要翻译：提供允许许多替代存储器块准备好以延长可重写寿命并由此有助于提高信息存储的可靠性的存储器系统。该存储器系统具有非易失性存储器，该非易失性存储器具有预定物理地址单元中的多个数据块，以及用于响应于来自外部的访问请求来控制该非易失性存储器的控制器。每个数据块具有用于保存关于每个数据区的重写计数和错误检查信息的区域。控制器在非易失性存储器中的读取操作中，根据错误检查信息检查受读取区域的任何错误，并且当存在任何错误时，如果重写计数大于预定值，则将替换与另一个数据块相关的数据块，或者如果不大于数据块，则与错误相关的数据块中的数据正确。

3. 发明授权

US07231580B2 Nonvolatile memory apparatus and data processing system 有权
标题翻译：非易失性存储器和数据处理系统
公开(公告)号：US07231580B2
公开(公告)日：2007-06-12
申请号：US10714982
申请日：2003-11-18
申请人： Shigemasa Shiota , Hiroyuki Goto , Hirofumi Shibuya , Fumio Hara , Kinji Mitani
发明人： Shigemasa Shiota , Hiroyuki Goto , Hirofumi Shibuya , Fumio Hara , Kinji Mitani
IPC分类号： G11C29/42 , G11C29/52 , H03M13/29
CPC分类号： G07F7/084 , G06F11/1044 , G06Q20/341 , G07F7/1008
摘要： The reliability of data is significantly increased without considerably increasing costs by performing minor data corrections within an information storage device and performing major error corrections in an information processing device. When a request to transfer user data for reading is issued from an information processing device, a control circuit transfers the user data and management data to an error detection circuit, which checks the user data for errors. If the user data contains no error, the control circuit notifies the information processing device that the user data can be transferred, and transfers it to the information processing device. If the user data contains errors, an X count error position and correction data calculation circuit uses the user data and the management data to calculate correction locations and correction data, and judges whether the correction locations are correctable. If uncorrectable (there are more correction locations than X locations), the control circuit notifies the information processing device that the user data is uncorrectable, and then transfers the user data and the management data to the information processing device.
摘要翻译：通过在信息存储设备内进行小数据校正并且在信息处理设备中执行主要错误校正，数据的可靠性显着增加，而不会显着增加成本。当从信息处理装置发出用于传送用于读取的用户数据的请求时，控制电路将用户数据和管理数据传送到检错用户数据的错误检测电路。如果用户数据不包含错误，则控制电路通知信息处理装置可以传送用户数据，并将其传送到信息处理装置。如果用户数据包含错误，X计数错误位置和校正数据计算电路使用用户数据和管理数据来计算校正位置和校正数据，并且判断校正位置是否可校正。如果不可校正（比X位置更多的校正位置），则控制电路向信息处理设备通知用户数据是不可校正的，然后将用户数据和管理数据传送到信息处理设备。

4. 发明申请

US20100054069A1 MEMORY SYSTEM 有权
标题翻译：记忆系统
公开(公告)号：US20100054069A1
公开(公告)日：2010-03-04
申请号：US12251444
申请日：2008-10-14
申请人： Shigemasa Shiota , Hiroyuki Goto , Hirofumi Shibuya , Fumio Hara , Yasuhiro Nakamura
发明人： Shigemasa Shiota , Hiroyuki Goto , Hirofumi Shibuya , Fumio Hara , Yasuhiro Nakamura
IPC分类号： G11C7/00
CPC分类号： G06F12/0246 , G06F13/161 , G06F13/1673 , G06F2212/7206 , G11C7/1006
摘要： The present invention provides a memory system which contributes to improvement in efficiency of a data process accompanying a memory access. A memory system has a rewritable nonvolatile memory, a buffer memory, and a controller. The controller controls, in response to an access request from an external apparatus, first data transfer between the controller and the external apparatus, second data transfer between the controller and the nonvolatile memory, and third data transfer between the controller and the buffer memory, controls transfer from the controller to the buffer memory in the third data transfer and transfer from the buffer memory to the controller in a time sharing manner, and enables the first data transfer or the second data transfer to be performed in parallel with the transfer carried out in the time sharing manner.
摘要翻译：本发明提供了一种有助于提高伴随存储器访问的数据处理的效率的存储器系统。存储器系统具有可重写非易失性存储器，缓冲存储器和控制器。控制器响应于来自外部设备的访问请求控制控制器和外部设备之间的第一数据传输，控制器和非易失性存储器之间的第二数据传输以及控制器和缓冲存储器之间的第三数据传送，控制在第三次数据传送中从控制器传送到缓冲存储器，并以时间共享的方式从缓冲存储器传输到控制器，并且能够与第一次数据传送或第二数据传输并行执行时间分享的方式。

5. 发明授权

US07197613B2 Nonvolatile memory 有权
标题翻译：非易失性存储器
公开(公告)号：US07197613B2
公开(公告)日：2007-03-27
申请号：US10721086
申请日：2003-11-26
申请人： Hirofumi Shibuya , Fumio Hara , Hiroyuki Goto , Shigemasa Shiota
发明人： Hirofumi Shibuya , Fumio Hara , Hiroyuki Goto , Shigemasa Shiota
IPC分类号： G06F12/12
CPC分类号： G06F11/1666 , G06F11/004 , G06F11/20 , G06F11/2053 , G11C16/04 , G11C29/44 , G11C29/4401 , G11C29/76 , G11C2029/0407 , G11C2029/0409 , G11C2229/723
摘要： It is aimed to detect, notify, and save an abnormal area in semiconductor memory for greatly improving reliability. An inside of semiconductor memories provided for a memory card comprises a user area, a substitution area, an area substitution information storage area, and a management area. An inside of semiconductor memories comprises a user area, a substitution area, and a management area. The user area is a data area a user can use. The substitution area is substituted when an error occurs in the user area. The area substitution information storage area stores area substitution area information. The management area stores substitution information. The information processing section performs substitution on two levels as follows. When detecting an operation indicating a symptom of failure in a semiconductor memory area, the information processing section performs area substitution during an idle state of the memory card. When detecting a faulty operation in an area, the information processing section immediately performs area substitution.
摘要翻译：旨在检测，通知和保存半导体存储器中的异常区域，大大提高可靠性。提供给存储卡的半导体存储器的内部包括用户区域，替换区域，区域替换信息存储区域和管理区域。半导体存储器的内部包括用户区域，替代区域和管理区域。用户区域是用户可以使用的数据区域。当用户区域发生错误时，替换区域被替换。区域替换信息存储区域存储区域替换区域信息。管理区域存储替换信息。信息处理部分按如下两个级别执行替换。当检测到指示半导体存储器区域中的故障症状的操作时，信息处理部件在存储卡的空闲状态期间执行区域替换。当检测到区域中的故障操作时，信息处理部分立即进行区域替换。

6. 发明申请

US20070038901A1 Nonvolatile memory system 失效
标题翻译：非易失性存储器系统
公开(公告)号：US20070038901A1
公开(公告)日：2007-02-15
申请号：US11583156
申请日：2006-10-19
申请人： Shigemasa Shiota , Hiroyuki Goto , Hirofumi Shibuya , Fumio Hara , Kinji Mitani
发明人： Shigemasa Shiota , Hiroyuki Goto , Hirofumi Shibuya , Fumio Hara , Kinji Mitani
IPC分类号： G06F11/00
CPC分类号： G11C16/349
摘要： A memory system permitting a number of alternative memory blocks to be made ready in order to extend the rewritable life and thereby contributing to enhanced reliability of information storage is to be provided. The memory system is provided with a nonvolatile memory having a plurality of data blocks in predetermined physical address units and a controller for controlling the nonvolatile memory in response to an access request from outside. Each of the data blocks has areas for holding a rewrite count and error check information regarding each data area. The controller, in a read operation on the nonvolatile memory, checks for any error in the area subject to the read according to error check information and, when there is any error, if the rewrite count is greater than a predetermined value, will replace the pertinent data block with another data block or if it is not greater, correct data in the data block pertaining to the error.
摘要翻译：提供允许许多替代存储器块准备好以延长可重写寿命并由此有助于提高信息存储的可靠性的存储器系统。该存储器系统具有非易失性存储器，该非易失性存储器具有预定物理地址单元中的多个数据块，以及用于响应于来自外部的访问请求来控制该非易失性存储器的控制器。每个数据块具有用于保存关于每个数据区的重写计数和错误检查信息的区域。控制器在非易失性存储器中的读取操作中，根据错误检查信息检查受读取区域的任何错误，并且当存在任何错误时，如果重写计数大于预定值，则将替换与另一个数据块相关的数据块，或者如果不大于数据块，则与错误相关的数据块中的数据正确。

7. 发明申请

US20050185449A1 Nonvolatile data storage apparatus 审中-公开
标题翻译：非易失数据存储装置
公开(公告)号：US20050185449A1
公开(公告)日：2005-08-25
申请号：US11035227
申请日：2005-01-14
申请人： Shigemasa Shiota , Kinji Mitani , Hiroyuki Goto , Hirofumi Shibuya , Fumio Hara
发明人： Shigemasa Shiota , Kinji Mitani , Hiroyuki Goto , Hirofumi Shibuya , Fumio Hara
IPC分类号： G06F12/16 , G06F3/00 , G06F13/00 , G11C7/02 , G11C7/10 , G11C11/00 , G11C16/06 , H03K5/153 , H03K17/30 , H03K19/0175
CPC分类号： G11C7/02 , G11C7/1006 , G11C16/06
摘要： The present invention is directed to increase noise immunity and largely improve the reliability of a memory device by controlling input/output buffers in accordance with a noise state of input/output signals. When a user data read-transfer request is received from a host, a controller checks the presence or absence of an error in read CRC data. When there is an error in the CRC data due to the influence of noise and the like, a data transfer control unit outputs a control signal to an I/O buffer switching unit to switch I/O buffers to a Schmitt input. If there is no error in the CRC data, the controller transfers user data to the host. When a re-transfer request is sent from the host after the transfer, the controller determines that the data transferred to the host was influenced by noise or the like and the data transfer control unit performs the control of the I/O buffer switching unit to decrease the drivability of the output buffer, thereby reducing noise.
摘要翻译：本发明旨在通过根据输入/输出信号的噪声状态控制输入/输出缓冲器来提高抗噪声性并大大提高存储器件的可靠性。当从主机接收到用户数据读取传送请求时，控制器检查读取的CRC数据中是否存在错误。当由于噪声等的影响而在CRC数据中存在错误时，数据传送控制单元向I / O缓冲器切换单元输出控制信号，以将I / O缓冲器切换到施密特输入。如果CRC数据中没有错误，则控制器将用户数据传送到主机。当在传送之后从主机发送再传送请求时，控制器确定传送到主机的数据受到噪声等的影响，并且数据传送控制单元执行I / O缓冲器切换单元的控制降低输出缓冲器的驾驶性能，从而降低噪音。

8. 发明授权

US08036040B2 Memory system with improved efficiency of data transfer between host, buffer, and nonvolatile memory 有权
标题翻译：内存系统提高了主机，缓冲区和非易失性存储器之间的数据传输效率
公开(公告)号：US08036040B2
公开(公告)日：2011-10-11
申请号：US12251444
申请日：2008-10-14
申请人： Shigemasa Shiota , Hiroyuki Goto , Hirofumi Shibuya , Fumio Hara , Yasuhiro Nakamura
发明人： Shigemasa Shiota , Hiroyuki Goto , Hirofumi Shibuya , Fumio Hara , Yasuhiro Nakamura
IPC分类号： G11C16/06
CPC分类号： G06F12/0246 , G06F13/161 , G06F13/1673 , G06F2212/7206 , G11C7/1006
摘要： The present invention provides a memory system which contributes to improvement in efficiency of a data process accompanying a memory access. A memory system has a rewritable nonvolatile memory, a buffer memory, and a controller. The controller controls, in response to an access request from an external apparatus, first data transfer between the controller and the external apparatus, second data transfer between the controller and the nonvolatile memory, and third data transfer between the controller and the buffer memory, controls transfer from the controller to the buffer memory in the third data transfer and transfer from the buffer memory to the controller in a time sharing manner, and enables the first data transfer or the second data transfer to be performed in parallel with the transfer carried out in the time sharing manner.
摘要翻译：本发明提供了一种有助于提高伴随存储器访问的数据处理的效率的存储器系统。存储器系统具有可重写非易失性存储器，缓冲存储器和控制器。控制器响应于来自外部设备的访问请求控制控制器和外部设备之间的第一数据传输，控制器和非易失性存储器之间的第二数据传输以及控制器和缓冲存储器之间的第三数据传送，控制在第三次数据传送中从控制器传送到缓冲存储器，并以时间共享的方式从缓冲存储器传输到控制器，并且能够与第一次数据传送或第二数据传输并行执行时间分享的方式。

9. 发明授权

US07447936B2 Nonvolatile memory system 失效
标题翻译：非易失性存储器系统
公开(公告)号：US07447936B2
公开(公告)日：2008-11-04
申请号：US11583156
申请日：2006-10-19
申请人： Shigemasa Shiota , Hiroyuki Goto , Hirofumi Shibuya , Fumio Hara , Kinji Mitani
发明人： Shigemasa Shiota , Hiroyuki Goto , Hirofumi Shibuya , Fumio Hara , Kinji Mitani
IPC分类号： G06F11/00
CPC分类号： G11C16/349
摘要： A memory system permitting a number of alternative memory blocks to be made ready in order to extend the rewritable life and thereby contributing to enhanced reliability of information storage is to be provided. The memory system is provided with a nonvolatile memory having a plurality of data blocks in predetermined physical address units and a controller for controlling the nonvolatile memory in response to an access request from outside. Each of the data blocks has areas for holding a rewrite count and error check information regarding each data area. The controller, in a read operation on the nonvolatile memory, checks for any error in the area subject to the read according to error check information and, when there is any error, if the rewrite count is greater than a predetermined value, will replace the pertinent data block with another data block or if it is not greater, correct data in the data block pertaining to the error.
摘要翻译：提供允许许多替代存储器块准备好以延长可重写寿命并由此有助于提高信息存储的可靠性的存储器系统。该存储器系统具有非易失性存储器，该非易失性存储器具有预定物理地址单元中的多个数据块，以及用于响应于来自外部的访问请求来控制该非易失性存储器的控制器。每个数据块具有用于保存关于每个数据区的重写计数和错误检查信息的区域。控制器在非易失性存储器中的读取操作中，根据错误检查信息检查受读取区域的任何错误，并且当存在任何错误时，如果重写计数大于预定值，则将替换与另一个数据块相关的数据块，或者如果不大于数据块，则与错误相关的数据块中的数据正确。

10. 发明申请

US20080046780A1 Nonvolatile memory 审中-公开
标题翻译：非易失性存储器
公开(公告)号：US20080046780A1
公开(公告)日：2008-02-21
申请号：US11907213
申请日：2007-10-10
申请人： Hirofumi Shibuya , Fumio Hara , Hiroyuki Goto , Shigemasa Shiota
发明人： Hirofumi Shibuya , Fumio Hara , Hiroyuki Goto , Shigemasa Shiota
IPC分类号： G06F11/16
CPC分类号： G06F11/1666 , G06F11/004 , G06F11/20 , G06F11/2053 , G11C16/04 , G11C29/44 , G11C29/4401 , G11C29/76 , G11C2029/0407 , G11C2029/0409 , G11C2229/723
摘要： It is aimed to detect, notify, and save an abnormal area in semiconductor memory for greatly improving reliability. An inside of semiconductor memories provided for a memory card comprises a user area, a substitution area, an area substitution information storage area, and a management area. An inside of semiconductor memories comprises a user area, a substitution area, and a management area. The user area is a data area a user can use. The substitution area is substituted when an error occurs in the user area. The area substitution information storage area stores area substitution area information. The management area stores substitution information. The information processing section performs substitution on two levels as follows. When detecting an operation indicating a symptom of failure in a semiconductor memory area, the information processing section performs area substitution during an idle state of the memory card. When detecting a faulty operation in an area, the information processing section immediately performs area substitution.
摘要翻译：旨在检测，通知和保存半导体存储器中的异常区域，大大提高可靠性。提供给存储卡的半导体存储器的内部包括用户区域，替换区域，区域替换信息存储区域和管理区域。半导体存储器的内部包括用户区域，替代区域和管理区域。用户区域是用户可以使用的数据区域。当用户区域发生错误时，替换区域被替换。区域替换信息存储区域存储区域替换区域信息。管理区域存储替换信息。信息处理部分按如下两个级别执行替换。当检测到指示半导体存储器区域中的故障症状的操作时，信息处理部件在存储卡的空闲状态期间执行区域替换。当检测到区域中的故障操作时，信息处理部分立即进行区域替换。

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