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    • 1. 发明授权
    • Raster scan image data display controller including means for reducing
flickering
    • 栅格扫描图像数据显示控制器包括用于减少闪烁的装置
    • US4788540A
    • 1988-11-29
    • US886428
    • 1986-07-17
    • Shigenori TokumitsuMasaaki Nishiura
    • Shigenori TokumitsuMasaaki Nishiura
    • H04N7/08G09G1/14G09G5/18G09G5/395H04N7/025H04N7/03H04N7/035H04N7/081G09G1/00
    • G09G1/146G09G5/395Y10S348/91
    • A raster scan image data display controller including a means for reducing flickering comprises an image memory for storing image data items at horizontal and vertical display addresses corresponding to horizontal and vertical coordinates on an image display area, a read-out device for supplying the horizontal and vertical display addresses to the image memory and reading out the image data items from the image memory, a display device for interlaced displaying of the read-out image data on paired scanning lines of two types of fields which are to be formed by a raster scan, a timing control device for synchronizing the horizontal and vertical display addresses with the raster scan of the display device, and a timing switching device for permitting said paired scanning lines of two types of fields formed by the raster scan in association with a timing control by the timing control device, to be switched, so as to select a pair of scanning lines which are situated close to each other.
    • 包括用于减少闪烁的装置的光栅扫描图像数据显示控制器包括:图像存储器,用于存储与图像显示区域上的水平和垂直坐标对应的水平和垂直显示地址的图像数据项,用于提供水平的读出装置和 垂直显示地址到图像存储器并从图像存储器中读出图像数据项;显示装置,用于在通过光栅扫描形成的两种场的成对扫描线上隔行显示读出的图像数据 用于使水平和垂直显示地址与显示装置的光栅扫描同步的定时控制装置和用于允许通过光栅扫描形成的两种类型的场的所述成对扫描线与定时控制相关联的定时切换装置 定时控制装置被切换,以选择彼此靠近的一对扫描线。
    • 3. 发明授权
    • Binary character generator for interlaced CRT display
    • 用于隔行CRT显示的二进制字符发生器
    • US4649378A
    • 1987-03-10
    • US553224
    • 1983-11-18
    • Michael J. JohnsonWilliam R. Hancock
    • Michael J. JohnsonWilliam R. Hancock
    • G09G5/36G09G1/00G09G1/14G09G1/06
    • G09G1/002G09G1/146
    • An apparatus for flicker reduction and increased writing speed into image memory in a CRT display having an interlaced scan with masking of low priority symbols. The apparatus expands or duplicates adjacent picture elements to provide redundant illumination for alternate fields, thereby providing at least two adjacent illuminated picture elements proximate to a masking image to reduce flickering during the writing of alternate fields. Writing into a single memory location commands illumination of a plurality of adjacent pixels, thereby reducing image memory writing time. The apparatus utilizes an image memory wherein video bit signals are written into only storage locations whose binary x coordinate has a predetermined first digit, and whose binary y coordinate has a predetermined first digit. Signals in storage locations whose addresses correspond to picture elements P.sub.I,J, P.sub.I-1,J, P.sub.I-1, .sub.J+1, and P.sub.I, J+1 are read from the image memory, and a Boolean OR sum signal is generated therefrom which is converted to an analog signal. The picture element P.sub.I,J is illuminated in response to an analog signal representing the Boolean OR sum signal 1.
    • 一种用于闪烁降低的装置,并且在具有具有低优先级符号掩蔽的隔行扫描的CRT显示器中的图像存储器中增加了写入速度。 该装置扩展或复制相邻的图像元素以提供用于替代场的冗余照明,由此提供靠近掩蔽图像的至少两个相邻的照明图像元素,以减少在写入替代场期间的闪烁。 写入单个存储器位置命令多个相邻像素的照明,从而减少图像存储器写入时间。 该装置利用图像存储器,其中视频比特信号被写入其二进制x坐标具有预定的第一数字并且其二进制y坐标具有预定的第一数字的存储位置。 从图像存储器中读取其地址对应于像素PI,J,PI-1,J,PI-1,J + 1和PI,J + 1的存储位置的信号,并从其生成布尔或或和信号 其被转换为模拟信号。 响应于表示布尔或或和信号1的模拟信号,图像元素PI,J被照亮。
    • 4. 发明授权
    • Arrangement for reducing the display size of characters stored in a
character store
    • 用于减少存储在字符存储中的字符的显示大小的布置
    • US4476464A
    • 1984-10-09
    • US359640
    • 1982-03-19
    • Donald S. Hobbs
    • Donald S. Hobbs
    • G06F3/153G09G1/14G09G5/24G09G5/26G09G1/22
    • G09G1/146G09G5/24
    • An alpha-numeric character generator arrangement having a character store (ROM) in which characters are stored in a character format contained within a co-ordinate character matrix of 10.times.6 discrete character elements. For television interlaced display using a 625-line standard, whole character shapes are displayed in both odd and even fields. For television interlaced display using a 525-line standard, only partial character shapes are displayed in each field, by omitting certain character element rows which are different for each field. The stored character set is so chosen in relation to the omitted character element rows that flicker is minimized. The reduced sized characters, as displayed, allow the same number of rows of characters per frame for the 525-line standard as for the 625-line standard.
    • 一种具有字符存储(ROM)的字母数字字符发生器装置,其中以包含在10×6个离散字符元素的坐标字符矩阵内的字符格式存储字符。 对于使用625行标准的电视隔行显示,在奇数和偶数场均显示全字符形状。 对于使用525行标准的电视隔行显示,仅在每个字段中显示部分字符形状,省略对于每个字段不同的某些字符元素行。 所存储的字符集相对于省略的字符元素行被选择,闪烁被最小化。 如显示的缩小字符字符允许525行标准与625行标准相同数量的每行字符数。
    • 5. 发明授权
    • Raster CRT having balanced pel distribution for flicker reduction
    • 光栅CRT具有平衡的像素分布,用于闪烁降低
    • US4521774A
    • 1985-06-04
    • US322819
    • 1981-11-19
    • Alan S. Murphy
    • Alan S. Murphy
    • G09G1/04G09G1/14G09G1/16
    • G09G1/146G09G1/04
    • A raster-scanned CRT device includes auxiliary vertical deflection means operable during each scan line of the raster to deflect the electron beam selectively between adjacent pairs of uniformly spaced image lines on the screen. Control logic operates in response to video information representing an image to be displayed to write image pels on the screen during two successive field scans of the raster. The auxilliary deflection means is controlled so that the entire image is formed on the image lines, and the field scan in which the pels are allocated for display is selected on-the-fly for successive portions of the input video in such a way that pel imbalance between the two fields constituting the final image is minimized.
    • 光栅扫描CRT器件包括辅助垂直偏转装置,其可在光栅的每个扫描线期间操作,以在屏幕上相邻的均匀间隔的成对线对之间选择性地偏转电子束。 控制逻辑响应于表示要显示的图像的视频信息,以在光栅的两个连续的场扫描期间在屏幕上写入图像像素。 控制辅助偏转装置使得整个图像形成在图像线上,并且其中分配用于显示的像素的场扫描被选择在输入视频的连续部分的运行中,使得像素 构成最终图像的两个场之间的不平衡被最小化。
    • 6. 发明授权
    • Flicker preventing circuit
    • 防闪烁电路
    • US4412251A
    • 1983-10-25
    • US298106
    • 1981-08-31
    • Yutaka TanakaToshinobu Isobe
    • Yutaka TanakaToshinobu Isobe
    • H04N5/21G09G1/14H04N5/14
    • H04N7/0132G09G1/146Y10S348/91
    • A flicker preventing circuit for a television receiver is disclosed which includes a first delay line for delaying an input video signal by one horizontal sweep period and producing a first delayed signal, a second delay line for delaying the input video signal by two horizontal periods and producing a second delayed signal, a switching circuit for selecting either the input video signal or the second delayed signal, the switching circuit being switched alternately according to which of the even and odd interlaced fields, respectively, is being displayed, an adder for adding the output signal from the switching circuit and the first delayed signal each other, and a level changing circuit for changing the level of either the input video signal or the second delayed signal relative to the level of the first delayed signal.
    • 公开了一种电视接收机防闪烁电路,它包括一个用于将输入视频信号延迟一个水平扫描周期并产生第一延迟信号的第一延迟线,用于将输入视频信号延迟两个水平周期的第二延迟线,并产生 第二延迟信号,用于选择输入视频信号或第二延迟信号的切换电路,切换电路根据正在显示的偶数和奇数交错场中的哪一个被交替地切换;加法器,用于将输出 来自开关电路的信号和第一延迟信号;以及电平改变电路,用于相对于第一延迟信号的电平改变输入视频信号或第二延迟信号的电平。
    • 8. 发明授权
    • System and method for reducing flicker on a display
    • 用于减少显示屏上闪烁的系统和方法
    • US5936621A
    • 1999-08-10
    • US672597
    • 1996-06-28
    • David MedinPaul J. Weihs
    • David MedinPaul J. Weihs
    • G09G1/14H04N5/44G09G5/00
    • H04N7/0132G09G1/146G09G2320/0247Y10S348/91
    • A system and method for reducing flicker in a display system using a flicker reduction circuit. The display includes a series of scan lines, each of which includes a set of pixels. The display is controlled by a video signal, which includes a series of video lines containing control variables that control the intensity of the pixels in the corresponding scan line. In one embodiment of the flicker reduction circuit, the flicker reduction circuit receives two of the video lines as input, and delays one of the one video lines using a memory, such that its control variables are synchronized in time with the other undelayed video line. The difference between the intensity of the synchronized pairs of control variables is determined, and the difference is fed into a look-up table. Based on the difference, the look-up table provides a control value that is then applied to one of the original synchronized control variables to provide a modified control variable that reduces flicker on the display screen.
    • 一种用于减少使用闪烁减少电路的显示系统中的闪烁的系统和方法。 显示器包括一系列扫描线,每条扫描线包括一组像素。 显示器由视频信号控制,视频信号包括一系列视频行,其中包含控制相应扫描线中像素强度的控制变量。 在闪烁降低电路的一个实施例中,闪烁降低电路接收两条视频线作为输入,并且使用存储器延迟一条视频线中的一条,使得其控制变量与另一个未延迟的视频行在时间上同步。 确定同步控制变量对的强度之间的差异,并将差值馈送到查找表中。 基于差异,查找表提供了一个控制值,然后将其应用于原始的同步控制变量之一,以提供一个减少显示屏上闪烁的修改控制变量。
    • 9. 发明授权
    • Memory efficient video graphics subsystem with vertical filtering and
scan rate conversion
    • 内存高效的视频图形子系统,具有垂直扫描和扫描速率转换
    • US5742349A
    • 1998-04-21
    • US646523
    • 1996-05-07
    • Tat Cheung ChoiPeter J. Lim
    • Tat Cheung ChoiPeter J. Lim
    • G09G1/14G09G1/16G09G5/00H04N11/20
    • G09G5/006G09G1/146G09G1/16G09G2310/0229G09G2320/0247
    • A graphics subsystem converts a first graphics data stream for display on a computer monitor having a first refresh rate into a second graphics data stream for a television monitor having a second, slower refresh rate. The graphics subsystem has a first memory for storing one horizontal scan line of pixel data and a second memory for storing one half of a horizontal scan line of pixel data. Multiplexers direct data to a first summing circuit from an input port and from the first memory itself, so that a first horizontal line of input pixel data is initially stored in the first memory and a second horizontal line of input pixel data is combined with the first horizontal line of data by the first summing circuit, and the resulting combined pixel data is stored in back into the first memory. A controller sends the combined pixel data from the first memory to a second summing circuit while a next horizontal line of input pixel data is received. The second summing circuit combines that next horizontal line of input pixel data with data from the first memory so as to generate vertically averaged pixel data that is then stored in the second memory. The vertically averaged pixel data in the second memory is sent to an output port at a rate of no less than one half the rate at which pixel data is being received at the input port.
    • 图形子系统将用于在具有第一刷新率的计算机监视器上显示的第一图形数据流转换成具有第二较慢刷新率的电视监视器的第二图形数据流。 图形子系统具有用于存储像素数据的一个水平扫描线的第一存储器和用于存储像素数据的水平扫描线的一半的第二存储器。 多路复用器将数据从输入端口和第一存储器本身引导到第一求和电路,使得初始地将第一水平行的输入像素数据存储在第一存储器中,并且输入像素数据的第二水平线与第一 通过第一求和电路的水平线数据,并将所得到的组合像素数据存储回第一存储器。 控制器将组合的像素数据从第一存储器发送到第二求和电路,同时接收下一个输入像素数据的水平行。 第二加法电路将输入像素数据的下一行水平线与来自第一存储器的数据相结合,以产生然后存储在第二存储器中的垂直平均像素数据。 第二存储器中的垂直平均像素数据以不小于在输入端口处接收像素数据的速率的一半的速率被发送到输出端口。