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1. 发明授权

US09015541B2 Device and method for performing timing analysis 有权
标题翻译：用于执行时序分析的装置和方法
公开(公告)号：US09015541B2
公开(公告)日：2015-04-21
申请号：US13798879
申请日：2013-03-13
申请人： Test Research, Inc.
发明人： Yu-Chen Shen , Yi-Hao Hsu
IPC分类号： G01R31/28 , G01R31/319 , G01R31/3193
CPC分类号： G01R31/3191 , G01R31/31937
摘要： A device for performing timing analysis used in a programmable logic array system is provided. The device comprises first and second basic I/O terminals, a channel multiplexer, high-speed I/O terminals, a sampling module and a timing analysis module. The first basic I/O terminals receive under-test signals from an under-test unit. The channel multiplexer receives the under-test signals from the first basic I/O terminals to select at least a group of the under-test signals to be outputted to the second basic I/O terminals. The high-speed I/O terminals has a logic level analyzing speed higher than that of the first and second basic I/O terminals. The sampling module receives the group of under-test signals from the high-speed I/O terminals and samples the group of under-test signals to generate a sample result. The timing analysis module performs timing analysis and measurement according to the sample result.
摘要翻译：提供了一种用于在可编程逻辑阵列系统中使用的时序分析的装置。该器件包括第一和第二基本I / O端子，通道多路复用器，高速I / O端子，采样模块和定时分析模块。第一个基本的I / O终端从受测单元接收未测试信号。信道多路复用器从第一基本I / O终端接收欠测信号，以选择要输出到第二基本I / O终端的至少一组未测试信号。高速I / O端子的逻辑电平分析速度高于第一和第二基本I / O端子。采样模块从高速I / O端子接收一组不足的测试信号，对未测试信号组进行采样以产生采样结果。定时分析模块根据样品结果进行定时分析和测量。

2. 发明申请

US20140201581A1 DEVICE AND METHOD FOR PERFORMING TIMING ANALYSIS 有权
标题翻译：用于执行时序分析的设备和方法
公开(公告)号：US20140201581A1
公开(公告)日：2014-07-17
申请号：US13798879
申请日：2013-03-13
申请人： TEST RESEARCH, INC.
发明人： Yu-Chen SHEN , Yi-Hao Hsu
IPC分类号： G01R31/3177
CPC分类号： G01R31/3191 , G01R31/31937
摘要： A device for performing timing analysis used in a programmable logic array system is provided. The device comprises first and second basic I/O terminals, a channel multiplexer, high-speed I/O terminals, a sampling module and a timing analysis module. The first basic I/O terminals receive under-test signals from an under-test unit. The channel multiplexer receives the under-test signals from the first basic I/O terminals to select at least a group of the under-test signals to be outputted to the second basic I/O terminals. The high-speed I/O terminals has a logic level analyzing speed higher than that of the first and second basic I/O terminals. The sampling module receives the group of under-test signals from the high-speed I/O terminals and samples the group of under-test signals to generate a sample result. The timing analysis module performs timing analysis and measurement according to the sample result.
摘要翻译：提供了一种用于在可编程逻辑阵列系统中使用的时序分析的装置。该器件包括第一和第二基本I / O端子，通道多路复用器，高速I / O端子，采样模块和定时分析模块。第一个基本的I / O终端从受测单元接收未测试信号。信道多路复用器从第一基本I / O终端接收欠测信号，以选择要输出到第二基本I / O终端的至少一组未测试信号。高速I / O端子的逻辑电平分析速度高于第一和第二基本I / O端子。采样模块从高速I / O端子接收一组不足的测试信号，对未测试信号组进行采样以产生采样结果。定时分析模块根据样品结果进行定时分析和测量。

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