专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20160320444A1 EFFICIENT METHOD OF RETESTING INTEGRATED CIRCUITS 有权
标题翻译：有效的电路集成方法
公开(公告)号：US20160320444A1
公开(公告)日：2016-11-03
申请号：US15192418
申请日：2016-06-24
申请人： International Business Machines Corporation
发明人： Teck Seng Eng , Michael Russell Uy Gonzales , Louie Que Hermosura
IPC分类号： G01R31/28
CPC分类号： G01R31/3177 , G01R31/2832 , G01R31/2894 , G01R31/31718
摘要： Efficient production testing of integrated circuits (ICs). A first production test is implemented on a group of ICs and failures among the test group are assessed. Specifically, the results of the first test are analyzed such that ICs having a recoverable fail and ICs having a non-recoverable fail are differentiated. The ICs are integrated based on the analyzed results and a second production test is implemented. The second production test tests the ICs responsive to the segregation, such that the second production test is limited only to ICs with a recoverable fail. The next succeeding production test will then use the new test program in the second production test with the handler bin designated as having ICs not to be re-tested.
摘要翻译：集成电路（IC）的高效生产测试。对一组IC进行第一次生产测试，并对测试组中的故障进行评估。具体地，分析第一测试的结果，使得具有可恢复故障的IC和具有不可恢复故障的IC被区分。基于分析结果集成IC，并实施第二次生产测试。第二次生产测试针对隔离测试IC，使得第二次生产测试仅限于具有可恢复故障的IC。接下来的生产测试将在第二次生产测试中使用新的测试程序，并将处理器bin指定为不重新测试IC。

2. 发明申请

US20150369862A1 EFFICIENT METHOD OF RETESTING INTEGRATED CIRCUITS 有权
标题翻译：有效的电路集成方法
公开(公告)号：US20150369862A1
公开(公告)日：2015-12-24
申请号：US14837402
申请日：2015-08-27
申请人： International Business Machines Corporation
发明人： Teck Seng Eng , Michael Russell Uy Gonzales , Louie Que Hermosura
IPC分类号： G01R31/3177
CPC分类号： G01R31/3177 , G01R31/2832 , G01R31/2894 , G01R31/31718
摘要： Efficient production testing of integrated circuits. A first production test is implemented on a group of integrated circuits and failures among the test group are assessed. Specifically, the results of the first test are analyzed such that integrated circuits having a recoverable fail and integrated circuits having a non-recoverable fail are differentiated. The integrated circuits are integrated based on the analyzed results and a second production test is implemented. The second production test tests the integrated circuits responsive to the segregation, such that the second production test is limited only to integrated circuits with a recoverable fail. The next succeeding production test will then use the new test program in the second production test with the handler bin designated as having integrated circuits not to be re-tested.
摘要翻译：集成电路的高效生产测试。对一组集成电路进行第一次生产测试，并对测试组中的故障进行评估。具体地，分析第一测试的结果，使得具有可恢复故障的集成电路和具有不可恢复故障的集成电路被区分。基于分析结果集成了集成电路，实现了第二次生产测试。第二次生产测试根据分离测试集成电路，使得第二次生产测试仅限于具有可恢复故障的集成电路。接下来的生产测试将在第二次生产测试中使用新的测试程序，并将处理器箱指定为不具有集成电路的重新测试。

3. 发明授权

US09170229B2 Method for diagnosing an electrical contact connection of an exhaust gas sensor 有权
标题翻译：用于诊断废气传感器的电接触连接的方法
公开(公告)号：US09170229B2
公开(公告)日：2015-10-27
申请号：US13775666
申请日：2013-02-25
申请人： CONTINENTAL AUTOMOTIVE GMBH
发明人： Jens Paggel , Sirko Schlegel
IPC分类号： G01N27/417 , G01N27/416 , G01R31/28 , F02D41/14 , G01R31/02 , F02D41/22 , G01R31/00
CPC分类号： G01N27/4175 , F02D41/1456 , F02D41/1495 , F02D41/222 , G01N27/4163 , G01R31/006 , G01R31/026 , G01R31/2832 , Y02T10/40
摘要： A method diagnoses an electrical contact connection of an exhaust gas sensor, in which two current sources are used to impress currents into a pump cell and a reference cell of the exhaust gas sensor. If a line is faulty, the relevant current cannot flow and a voltage on the relevant current source assumes a high value. If a second line is faulty, measurement of the voltage on the second connection, which is connected to the connecting point between the two cells, provides a low value when the relevant second connection is isolated from the reference-ground potential by a second switch, since the cell capacitances have not been able to charge to the reference-ground potential.
摘要翻译：一种用于诊断排气传感器的电接触连接的方法，其中使用两个电流源来将电流注入到泵电池和废气传感器的参考电池中。如果线路故障，相关电流不能流动，相关电流源上的电压值会较高。如果第二线路故障，则当相关的第二连接通过第二开关与基准接地电位隔离时，连接到两个电池之间的连接点的第二连接上的电压的测量值提供较低的值，因为电池电容不能充电到基准电位。

4. 发明申请

US20140278196A1 EFFICIENT METHOD OF RETESTING INTEGRATED CIRCUITS 有权
标题翻译：有效的电路集成方法
公开(公告)号：US20140278196A1
公开(公告)日：2014-09-18
申请号：US13833308
申请日：2013-03-15
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Teck Seng Eng , Michael Russell Uy Gonzales , Louie Que Hermosura
IPC分类号： G01R31/28
CPC分类号： G01R31/3177 , G01R31/2832 , G01R31/2894 , G01R31/31718
摘要： Efficient production testing of integrated circuits. A first production test is implemented on a group of integrated circuits and failures among the test group are assessed. Specifically, the results of the first test are analyzed such that integrated circuits having a recoverable fail and integrated circuits having a non-recoverable fail are differentiated. The integrated circuits are integrated based on the analyzed results and a second production test is implemented. The second production test tests the integrated circuits responsive to the segregation, such that the second production test is limited only to integrated circuits with a recoverable fail. The next succeeding production test will then use the new test program in the second production test with the handler bin designated as having integrated circuits not to be re-tested.
摘要翻译：集成电路的高效生产测试。对一组集成电路进行第一次生产测试，并对测试组中的故障进行评估。具体地，分析第一测试的结果，使得具有可恢复故障的集成电路和具有不可恢复故障的集成电路被区分。基于分析结果集成了集成电路，实现了第二次生产测试。第二次生产测试根据分离测试集成电路，使得第二次生产测试仅限于具有可恢复故障的集成电路。接下来的生产测试将在第二次生产测试中使用新的测试程序，并将处理器箱指定为不具有集成电路的重新测试。

5. 发明申请

US20140132083A1 USB PERIPHERAL DEVICE DETECTION ON AN UNPOWERED BUS 有权
标题翻译： USB外设设备检测未加功率总线
公开(公告)号：US20140132083A1
公开(公告)日：2014-05-15
申请号：US14076446
申请日：2013-11-11
申请人： THOMSON LICENSING
发明人： Phillippe Marchand , Philippe Guillot , Xavier Guitton
IPC分类号： G01R31/28
CPC分类号： G01R31/2832 , G06F13/4072 , G06F13/4081 , G06F2213/0042 , Y10T307/858
摘要： Method for detecting a connection of a peripheral device to a communication interface of an electronic device and associated detection circuit; the communication interface comprising a voltage power line for the power supply of a peripheral device, a range of nominal operating voltage values being associated with the power line, the method being characterised in that it comprises steps of application of a nominal voltage comprised in the range of nominal operating voltage values to the power line, of withdrawal of the nominal operating voltage applied to the power line, of detection, on the power line, in the presence of a residual voltage less than a threshold value of the nominal voltage value, of a transient signal resulting from the connection of the peripheral device to the interface, and of application of the nominal voltage to the voltage power line, according to the transient signal detected.
摘要翻译：用于检测外围设备与电子设备的通信接口和相关联的检测电路的连接的方法; 所述通信接口包括用于外围设备的电源的电压电源线，所述额定工作电压值的范围与所述电力线相关联，所述方法的特征在于，其包括以下步骤：施加包括在所述范围内的标称电压在电源线上的额定工作电压值，在存在小于标称电压值的阈值的剩余电压的情况下，提取施加到电力线上的额定工作电压，检测电力线上的额定工作电压值根据检测到的瞬态信号，由外围设备连接到接口产生的瞬态信号，以及将标称电压施加到电压电源线。

6. 发明申请

US20130229197A1 TEST APPARATUS 有权
标题翻译：测试仪器
公开(公告)号：US20130229197A1
公开(公告)日：2013-09-05
申请号：US13781416
申请日：2013-02-28
申请人： ADVANTEST CORPORATION
发明人： Takashi Kusaka , Masahiro Ishida
IPC分类号： G01R31/28
CPC分类号： G01R31/2832 , G01R31/31924 , H02M3/156 , H02M2001/0019
摘要： A main power supply is arranged such that its output terminal Po is connected to a power supply terminal of a DUT via a power supply line, and is configured to feedback control an output voltage VOUT output from the output terminal such that a detection value VDD′ that corresponds to a power supply voltage VDD at the power supply terminal approaches a target value VREF′. When a test pattern is supplied to the DUT, a power supply control unit is configured to feedforward control the main power supply such that the power supply voltage VDD approaches a predetermined target waveform VTGT.
摘要翻译：主电源被布置成使得其输出端子Po经由电源线连接到DUT的电源端子，并且被配置为反馈控制从输出端子输出的输出电压VOUT，使得检测值VDD' 对应于电源端子处的电源电压VDD接近目标值VREF'。当测试图案被提供给DUT时，电源控制单元被配置为前馈控制主电源，使得电源电压VDD接近预定的目标波形VTGT。

7. 发明申请

US20050030069A1 Semiconductor test device 失效
标题翻译：半导体测试装置
公开(公告)号：US20050030069A1
公开(公告)日：2005-02-10
申请号：US10935894
申请日：2004-09-08
申请人： Katsumi Isobe
发明人： Katsumi Isobe
IPC分类号： G01R31/28 , H03B1/00
CPC分类号： G01R31/2839 , G01R31/2832
摘要： The present invention provides a semiconductor test device that can output a higher voltage as a driver output without increasing power consumption of a high-speed driver, so as to test a device under test. In order to achieve this, the semiconductor test device for switching a driver output between a plurality of voltages and a higher voltage that is higher than said plurality of voltages and outputting said driver output to test a device under test, includes: a first buffer portion operable to output said plurality of voltages by a push-pull circuit of an emitter follower serving as a source and an emitter follower serving as a sink; and a second buffer portion operable to output said higher voltage by a push-pull circuit of said emitter follower serving as said sink of said first buffer portion and an emitter follower serving as a source of said higher voltage.
摘要翻译：本发明提供一种可以在不增加高速驱动器的功耗的情况下输出较高电压作为驱动器输出的半导体测试装置，以便测试被测器件。为了实现这一点，用于切换多个电压之间的驱动器输出和高于所述多个电压的较高电压并且输出所述驱动器输出以测试被测器件的半导体测试装置包括：第一缓冲部分可操作地通过用作源的射极跟随器的引入电路和用作接收器的射极跟随器来输出所述多个电压; 以及第二缓冲器部分，其可操作以通过作为所述第一缓冲部分的所述吸收器的所述射极跟随器的推挽电路和用作所述较高电压源的射极跟随器来输出所述较高电压。

8. 发明授权

US09797942B2 Radiometric test and configuration of an infrared focal plane array at wafer probe 有权
公开(公告)号：US09797942B2
公开(公告)日：2017-10-24
申请号：US14838048
申请日：2015-08-27
申请人： Seek Thermal, Inc.
发明人： Andreas Engberg , William J. Parrish
IPC分类号： G01R31/265 , G01J1/08 , G01J5/52 , G01R31/28 , G01J5/02 , G01R31/3185 , G01J5/20 , G01J5/00 , G01J5/06
CPC分类号： G01R31/2656 , G01J1/08 , G01J5/02 , G01J5/20 , G01J5/522 , G01J2005/0048 , G01J2005/0077 , G01J2005/068 , G01R31/2832 , G01R31/318511 , G01R31/31937
摘要： FPAs on a wafer can be tested prior to dicing the wafer into individual dies. A focal plane array (FPA) can comprise an array of photodetectors, such as microbolometers, on a semiconductor substrate or die. FPAs can be manufactured on a wafer to make multiple FPAs on a single wafer that can be later diced or divided into individual FPAs. Prior to dicing the wafer, the FPAs can be tested electrically and radiometrically in bulk to characterize individual FPAs, to identify bad pixels, to identify bad chips, to calibrate individual FPAs, and the like. These test results can be used to determine acceptable FPAs and can be used to provide initial settings for imaging systems with the tested and integrated FPA.

9. 发明申请

US20170256341A1 CONTROL CIRCUIT AND CONTROL METHOD 审中-公开
公开(公告)号：US20170256341A1
公开(公告)日：2017-09-07
申请号：US15503759
申请日：2015-09-01
申请人： NEC Corporation
发明人： Takafumi KOBAYASHI
IPC分类号： H01C7/10 , H01C1/16 , G01R31/28
CPC分类号： H01C7/10 , G01R31/2832 , H01C1/16 , H03K19/0005 , H03K19/017545 , H04L25/0298
摘要： The present invention addresses the problem of many man-hours being required for a hardware engineer to adjust a resistance value such that the rise time of a signal input to an LSI body falls within a defined range. To solve this problem, the present invention provides a control circuit provided with: a conductive wire for transmitting an input electric signal to an integrated circuit; a resistance circuit which has a variable resistance value and which is connected to the conductive wire and grounded; a measurement means for measuring a rise time of the electric signal transmitted through the conductive wire, that is, the amount of time it takes for the voltage value of the electric signal to reach a predetermined second voltage value from a predetermined first voltage value, said predetermined second voltage value being higher than the first voltage value; and a control means for changing the resistance value of the resistance circuit to a value which is lower by a specific amount when the time measured by the measurement means is shorter than the minimum time of a predetermined time range, and changing the resistance value to a value which is higher by a specific amount when the time measured by the measurement means is longer than the maximum time of the predetermined time range. The control means outputs a predetermined signal upon having changed the resistance value a predetermined number of times.

10. 发明授权

US09684034B2 Efficient method of retesting integrated circuits 有权
公开(公告)号：US09684034B2
公开(公告)日：2017-06-20
申请号：US15192418
申请日：2016-06-24
申请人： International Business Machines Corporation
发明人： Teck Seng Eng , Michael Russell Uy Gonzales , Louie Que Hermosura
IPC分类号： G01R31/28 , G01R31/317 , G01R31/3177
CPC分类号： G01R31/3177 , G01R31/2832 , G01R31/2894 , G01R31/31718
摘要： Efficient production testing of integrated circuits (ICs). A first production test is implemented on a group of ICs and failures among the test group are assessed. Specifically, the results of the first test are analyzed such that ICs having a recoverable fail and ICs having a non-recoverable fail are differentiated. The ICs are integrated based on the analyzed results and a second production test is implemented. The second production test tests the ICs responsive to the segregation, such that the second production test is limited only to ICs with a recoverable fail. The next succeeding production test will then use the new test program in the second production test with the handler bin designated as having ICs not to be re-tested.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式