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1. 发明授权

US07660270B2 Computer system and method using efficient module and backplane tiling to interconnect computer nodes via a Kautz-like digraph 失效
标题翻译：计算机系统和方法使用高效模块和背板平铺，通过考茨特图连接计算机节点
公开(公告)号：US07660270B2
公开(公告)日：2010-02-09
申请号：US11594416
申请日：2006-11-08
申请人： Judson S. Leonard , Matthew H. Reilly , Lawrence C. Stewart , Washington Taylor
发明人： Judson S. Leonard , Matthew H. Reilly , Lawrence C. Stewart , Washington Taylor
IPC分类号： H04L12/28
CPC分类号： G06F15/173
摘要： Computer systems and methods using efficient module and backplane tiling to interconnect computer nodes via a Kautz-like digraph. A multinode computing system includes a large plurality of computing nodes interconnected via a Kautz topology having order O, diameter n, and degree k. The order equals (k+1)kn−1. The interconnections from a node x to a node y in the topology satisfy the relationship y=(−x*k−j) mod O, where 1≦j≦k, and the computing nodes are arranged onto a plurality of modules. Each module has an equal plurality of computing nodes on it. A majority of the inter-node connections are contained on the plurality of modules and a minority of the inter-node connections are inter-module connections. Inter-module connections are routed among modules in parallel on an inter-module connection plane.
摘要翻译：使用高效模块和背板平铺的计算机系统和方法通过考茨特图连接计算机节点。多节点计算系统包括通过具有阶数O，直径n和度k的考茨拓扑互连的大量多个计算节点。顺序等于（k + 1）kn-1。从拓扑中的节点x到节点y的互连满足关系y =（ - x * k-j）mod O，其中1 <= j <= k，并且计算节点被布置在多个模块上。每个模块在其上具有相等的多个计算节点。大多数节点间连接包含在多个模块中，并且少数节点间连接是模块间连接。模块间连接在模块间连接平面上并行路由。

2. 发明申请

US20080109604A1 Systems and methods for remote direct memory access to processor caches for RDMA reads and writes 审中-公开
标题翻译：用于远程直接内存访问用于RDMA读取和写入的处理器高速缓存的系统和方法
公开(公告)号：US20080109604A1
公开(公告)日：2008-05-08
申请号：US11594447
申请日：2006-11-08
申请人： Matthew H. Reilly , Judson S. Leonard
发明人： Matthew H. Reilly , Judson S. Leonard
IPC分类号： G06F12/00
CPC分类号： G06F12/0835 , G06F12/0813 , G06F12/0879 , G06F2212/2542
摘要： The invention relates to a systems and methods for remote direct memory access to processor caches for remote direct memory access (RDMA) reads and writes. One aspect of the invention is a computer node within a multi-node computer system having a plurality of interconnected processing nodes. The computer node has least one processor associated with at least one processor cache for holding cache entries for the at least one processor. A cache interface for the remote DMA engine on the node includes logic to consult the processor cache control structure, to determine whether the processor cache has a cache entry associated with a physical address of a DMA transfer, and if so, reading from that cache entry or writing to that cache entry to service the DMA transfer.
摘要翻译：本发明涉及用于远程直接存储器访问用于远程直接存储器访问（RDMA）读取和写入的处理器高速缓存的系统和方法。本发明的一个方面是具有多个互连处理节点的多节点计算机系统内的计算机节点。计算机节点具有与至少一个处理器高速缓存相关联的至少一个处理器，用于保存至少一个处理器的高速缓存条目。用于该节点上的远程DMA引擎的高速缓存接口包括参考处理器高速缓存控制结构的逻辑，以确定处理器高速缓存是否具有与DMA传输的物理地址相关联的高速缓存条目，如果是，则从该高速缓存条目读取或写入该缓存条目以服务于DMA传输。

3. 发明授权

US07689856B2 Mesochronous clock system and method to minimize latency and buffer requirements for data transfer in a large multi-processor computing system 失效
标题翻译：用于在大型多处理器计算系统中最小化数据传输的延迟和缓冲器要求的中间时钟系统和方法
公开(公告)号：US07689856B2
公开(公告)日：2010-03-30
申请号：US11594442
申请日：2006-11-08
申请人： Nitin Godiwala
发明人： Nitin Godiwala
IPC分类号： G06F1/00 , G06F1/04 , G06F1/12
CPC分类号： H04L7/0012
摘要： A mesochronous clock system and method to minimize latency and buffer requirements for data transfer in a large multiprocessor computing system. A stream of data is transferred from a first clock domain with a first clock signal to a second clock domain with a second clock signal. The first and second clock signals have a mesochronous relationship. The first clock signal is sampled in the second clock domain. In response to the sampling of the first clock signal, a modified version of the first clock signal is formed having a known phase relationship to the second clock signal. A parallel form of the received data is formed under the control of modified version of the first clock signal. In response to the sampling of the first clock signal, a subset of contiguous bits of the parallel data is selected for use in the second clock domain.
摘要翻译：一种用于在大型多处理器计算系统中最小化数据传输的延迟和缓冲器要求的中间时钟系统和方法。数据流从具有第一时钟信号的第一时钟域传送到具有第二时钟信号的第二时钟域。第一和第二时钟信号具有中间同步关系。第一个时钟信号在第二个时钟域采样。响应于第一时钟信号的采样，形成具有与第二时钟信号的已知相位关系的第一时钟信号的修改版本。在第一时钟信号的修改版本的控制下形成接收数据的并行形式。响应于第一时钟信号的采样，选择并行数据的连续位的子集用于第二时钟域。

4. 发明申请

US20080109544A1 Computer system and method using a kautz-like digraph to interconnect computer nodes and having control back channel between nodes 失效
标题翻译：计算机系统和方法使用类似kautz的有向图来互连计算机节点并在节点之间具有控制回路
公开(公告)号：US20080109544A1
公开(公告)日：2008-05-08
申请号：US11594423
申请日：2006-11-08
申请人： Judson S. Leonard , Matthew H. Reilly , Lawrence C. Stewart , Washington Taylor
发明人： Judson S. Leonard , Matthew H. Reilly , Lawrence C. Stewart , Washington Taylor
IPC分类号： G06F15/173
CPC分类号： H04L41/12 , H04L41/145
摘要： Computer system and method using a Kautz-like digraph to interconnect computer nodes and having control back channel between nodes. A multinode computing system includes a large plurality of computing nodes interconnected via a Kautz topology having order O, diameter n, and degree k. The order equals (k+1)kn−1; The data interconnections from a node x to a node y in the topology satisfy the relationship y=(−x*k−j) mod O, where 1≦j≦k; and each x,y pair includes a unidirectional control link from node y to node x to convey flow control and error information from a receiving node y to a transmitting node x.
摘要翻译：计算机系统和方法使用类似Kautz的有向图互连计算机节点并具有节点之间的控制回路。多节点计算系统包括通过具有阶数O，直径n和度k的考茨拓扑互连的大量多个计算节点。顺序等于（k + 1）k 1; 从拓扑中的节点x到节点y的数据互连满足关系y =（ - x * k-j）mod O，其中1 <= j <= k; 并且每个x，y对包括从节点y到节点x的单向控制链路，以将流量控制和错误信息从接收节点y传送到发送节点x。

5. 发明申请

US20080107106A1 System and method for preventing deadlock in richly-connected multi-processor computer system using dynamic assignment of virtual channels 失效
标题翻译：使用虚拟通道的动态分配来防止富连接多处理器计算机系统中的死锁的系统和方法
公开(公告)号：US20080107106A1
公开(公告)日：2008-05-08
申请号：US11594426
申请日：2006-11-08
申请人： Judson S. Leonard , Matthew H. Reilly , Nitin Godiwala
发明人： Judson S. Leonard , Matthew H. Reilly , Nitin Godiwala
IPC分类号： H04L12/56
CPC分类号： G06F15/17381 , H04L47/10 , H04L47/11
摘要： Systems and methods for preventing deadlock in richly-connected multiprocessor computer system using dynamic assignment of virtual channels. Deadlock is prevented in a multiprocessor computer system having a large plurality of processing nodes interconnected by a defined interconnection topology. Each link in the interconnection topology is associated with a set of virtual channels. Each virtual channel has corresponding communication buffers to store communication data and each virtual channel has an associated virtual channel identifier. Each communication between a source processing node and a target processing node is assigned an initial virtual channel to convey the communication from the source processing node. At an intermediate processing node, a different virtual channel is assigned to convey the communication toward the target processing node, in accordance with pre-defined rules to avoid a cycle of dependency of communication buffer resources.
摘要翻译：使用虚拟通道的动态分配来防止富连接多处理器计算机系统中的死锁的系统和方法。在具有通过定义的互连拓扑互连的大量多个处理节点的多处理器计算机系统中，阻止了死锁。互连拓扑中的每个链路与一组虚拟通道相关联。每个虚拟通道具有对应的通信缓冲器以存储通信数据，并且每个虚拟通道具有相关联的虚拟通道标识符。为源处理节点和目标处理节点之间的每个通信被分配初始虚拟通道以传送来自源处理节点的通信。在中间处理节点处，分配不同的虚拟信道以根据预定义的规则向目标处理节点传送通信，以避免通信缓冲器资源的依赖循环。

6. 发明授权

US07773616B2 System and method for communicating on a richly connected multi-processor computer system using a pool of buffers for dynamic association with a virtual channel 失效
标题翻译：用于在富连接的多处理器计算机系统上使用用于与虚拟通道动态关联的缓冲池的通信的系统和方法
公开(公告)号：US07773616B2
公开(公告)日：2010-08-10
申请号：US11594405
申请日：2006-11-08
申请人： Matthew H. Reilly , Nitin Godiwala , Judson S. Leonard
发明人： Matthew H. Reilly , Nitin Godiwala , Judson S. Leonard
IPC分类号： H04L12/28 , H04L12/56
CPC分类号： H04L49/9047 , H04L45/10 , H04L49/90
摘要： Systems and methods for communicating on a richly-connected multiprocessor computer system using a pool of buffers for dynamic association with a virtual channel. Packets are communicated in a multiprocessor computer system having a large plurality of processing nodes interconnected by a defined interconnection topology, in which a communication from a source processing node to a target processing node may pass through one or more intermediate nodes en route to the target processing node. A set of virtual channels is associated for each link in the interconnection topology. A first subset of buffers is dedicated for fixed correspondence to virtual channel identifiers, and a second subset of buffers is dedicated for dynamic allocation and assignment to virtual channels.
摘要翻译：用于在富连接的多处理器计算机系统上进行通信的系统和方法，该缓冲区用于与虚拟通道动态关联。分组在具有通过定义的互连拓扑互联的大量多个处理节点的多处理器计算机系统中通信，其中从源处理节点到目标处理节点的通信可以通过到目标处理的一个或多个中间节点节点。一组虚拟通道与互连拓扑中的每个链路相关联。缓冲器的第一子集专用于对虚拟信道标识符的固定对应，并且第二子缓存器专用于动态分配和分配给虚拟信道。

7. 发明授权

US07751344B2 Computer system and method using a kautz-like digraph to interconnect computer nodes and having control back channel between nodes 失效
标题翻译：计算机系统和方法使用类似kautz的有向图来互连计算机节点并在节点之间具有控制回路
公开(公告)号：US07751344B2
公开(公告)日：2010-07-06
申请号：US11594423
申请日：2006-11-08
申请人： Judson S. Leonard , Matthew H. Reilly , Lawrence C. Stewart , Washington Taylor
发明人： Judson S. Leonard , Matthew H. Reilly , Lawrence C. Stewart , Washington Taylor
IPC分类号： H04L12/28
CPC分类号： H04L41/12 , H04L41/145
摘要： Computer system and method using a Kautz-like digraph to interconnect computer nodes and having control back channel between nodes. A multinode computing system includes a large plurality of computing nodes interconnected via a Kautz topology having order O, diameter n, and degree k. The order equals (k+1)kn−1; The data interconnections from a node x to a node y in the topology satisfy the relationship y=(−x*k−j) mod O, where 1≦j≦k; and each x,y pair includes a unidirectional control link from node y to node x to convey flow control and error information from a receiving node y to a transmitting node x.
摘要翻译：计算机系统和方法使用类似Kautz的有向图互连计算机节点并具有节点之间的控制回路。多节点计算系统包括通过具有阶数O，直径n和度k的考茨拓扑互连的大量多个计算节点。顺序等于（k + 1）kn-1; 拓扑中节点x到节点y的数据互连满足关系y =（ - x * k-j）mod O，其中1＆nlE; j＆nlE; k; 并且每个x，y对包括从节点y到节点x的单向控制链路，以将流量控制和错误信息从接收节点y传送到发送节点x。

8. 发明申请

US20080126571A1 Computer system and method using efficient module and backplane tiling to interconnect computer nodes via a Kautz-like digraph 失效
标题翻译：计算机系统和方法使用高效模块和背板平铺，通过考茨特图连接计算机节点
公开(公告)号：US20080126571A1
公开(公告)日：2008-05-29
申请号：US11594416
申请日：2006-11-08
申请人： Judson S. Leonard , Matthew H. Reilly , Lawrence C. Stewart , Washington Taylor
发明人： Judson S. Leonard , Matthew H. Reilly , Lawrence C. Stewart , Washington Taylor
IPC分类号： G06F15/173
CPC分类号： G06F15/173
摘要： Computer systems and methods using efficient module and backplane tiling to interconnect computer nodes via a Kautz-like digraph. A multinode computing system includes a large plurality of computing nodes interconnected via a Kautz topology having order O, diameter n, and degree k. The order equals (k+1)kn−1. The interconnections from a node x to a node y in the topology satisfy the relationship y=(−x*k−j) mod O, where 1≦j≦k, and the computing nodes are arranged onto a plurality of modules. Each module has an equal plurality of computing nodes on it. A majority of the inter-node connections are contained on the plurality of modules and a minority of the inter-node connections are inter-module connections. Inter-module connections are routed among modules in parallel on an inter-module connection plane.
摘要翻译：使用高效模块和背板平铺的计算机系统和方法通过考茨特图连接计算机节点。多节点计算系统包括通过具有阶数O，直径n和度k的考茨拓扑互连的大量多个计算节点。顺序等于（k + 1）k 1。从拓扑中的节点x到节点y的互连满足关系y =（ - x * k-j）mod O，其中1 <= j <= k，并且计算节点被布置在多个模块上。每个模块在其上具有相等的多个计算节点。大多数节点间连接包含在多个模块中，并且少数节点间连接是模块间连接。模块间连接在模块间连接平面上并行路由。

9. 发明申请

US20080109573A1 RDMA systems and methods for sending commands from a source node to a target node for local execution of commands at the target node 审中-公开
标题翻译：用于从源节点向目标节点发送命令的RDMA系统和方法，用于在目标节点处本地执行命令
公开(公告)号：US20080109573A1
公开(公告)日：2008-05-08
申请号：US11594443
申请日：2006-11-08
申请人： Judson S. Leonard , Lawrence C. Stewart , David Gingold
发明人： Judson S. Leonard , Lawrence C. Stewart , David Gingold
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： The invention relates to a RDMA system for sending commands from a source node to a target node. These commands are locally executed at the target node. One aspect of the invention is a multi-node computer system having a plurality of interconnected processing nodes. The computer system issues a direct memory access (DMA) command from a first node to be executed by a DMA engine at a second node. Commands are transferred and executed by forming, at a first node, a packet having a payload containing the DMA command. The packets are sent to the second node via the interconnection topology, where the second node receives the packet and validating that the packet complies with a predefined trust relationship. The command is then processed by the DMA engine at the second node.
摘要翻译：本发明涉及一种用于从源节点向目标节点发送命令的RDMA系统。这些命令在目标节点本地执行。本发明的一个方面是具有多个互连处理节点的多节点计算机系统。计算机系统从第一节点发出由DMA引擎在第二节点执行的直接存储器访问（DMA）命令。通过在第一节点处形成具有包含DMA命令的有效负载的分组来传送和执行命令。分组经由互连拓扑被发送到第二节点，其中第二节点接收分组并且验证分组符合预定义的信任关系。该命令然后由DMA引擎在第二个节点进行处理。

10. 发明申请

US20080109672A1 Large scale computing system with multi-lane mesochronous data transfers among computer nodes 审中-公开
标题翻译：在计算机节点之间具有多通道同步数据传输的大规模计算系统
公开(公告)号：US20080109672A1
公开(公告)日：2008-05-08
申请号：US11594441
申请日：2006-11-08
申请人： Nitin Godiwala , Matthew H. Reilly
发明人： Nitin Godiwala , Matthew H. Reilly
IPC分类号： G06F1/12
CPC分类号： H04L7/0012 , H04J3/0658 , H04J3/0697
摘要： Large scale computing systems with multi-lane mesochronous data transfers among computer nodes. A large scale computing system includes a large plurality of computing nodes interconnected in a predefined topology. Each computing node is controlled by a corresponding clock signal, and the each clock signal has a mesochronous relationship to the clock signals on the other computing nodes. Each connection between nodes is a multi-lane connection, and each lane carries a serial stream of data that is mesochronously related to the other lanes. Each data lane is characterized relative to the other data lanes between the first and second node to determine relative delay in transmission between the first and second nodes. The transmission delays are equalized so that each data lane provides data for processing in the second clock domain in substantial synchronism with the other lanes.
摘要翻译：在计算机节点之间具有多通道同步数据传输的大规模计算系统。大规模计算系统包括以预定拓扑互连的大量多个计算节点。每个计算节点由对应的时钟信号控制，并且每个时钟信号与其他计算节点上的时钟信号具有中间同步关系。节点之间的每个连接都是多通道连接，每个通道都携带与其他通道中间相关的串行数据流。每个数据通道相对于第一和第二节点之间的其他数据通道进行表征，以确定第一和第二节点之间的传输中的相对延迟。传输延迟被均衡，使得每个数据通道提供用于在第二时钟域中与其他通道基本同步的处理的数据。

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