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    • 3. 发明授权
    • Performing rounding in an arithmetic operation
    • 在算术运算中执行舍入
    • US08095587B2
    • 2012-01-10
    • US11479933
    • 2006-06-30
    • Tariq KurdMark O. Homewood
    • Tariq KurdMark O. Homewood
    • G06F7/38G06F7/52
    • G06F7/5334G06F7/49947G06F7/49957G06F7/49963
    • An arithmetic unit comprising: an encoding circuit arranged to receive first and second operands each having a bit length of m bits and to generate therefrom a number n of partial products of bit length of 2m bits or less; an addition circuit having 2m columns each having n inputs, wherein bits of said partial products are applied to said inputs for combining said partial products into a result leaving certain of said inputs unused; and a rounding bit generator connected to supply a rounding bit to at least one of said unused inputs in one of said in columns at a bit position to cause said result to be rounded.
    • 一种算术单元,包括:编码电路,被配置为接收每个具有m比特位长度的第一和第二操作数,并从其生成位数为2m位或更少的n个部分乘积; 具有每个具有n个输入的2m列的加法电路,其中所述部分乘积的位被施加到所述输入,用于将所述部分乘积组合成使得某些所述输入未被使用的结果; 以及圆形位发生器,其被连接以在位位置向所述列中的一个列中的至少一个所述未使用的输入提供舍入位,以使所述结果舍入。
    • 5. 发明申请
    • Multiplication circuitry
    • 乘法电路
    • US20070043802A1
    • 2007-02-22
    • US11490475
    • 2006-07-20
    • Tariq Kurd
    • Tariq Kurd
    • G06F7/44
    • G06F7/5318
    • Combining circuitry for combining a plurality of multi-bit partial product terms in a multiplier circuit includes a plurality of compression columns, each column receiving a plurality of partial product term bits. At least one compression column includes: a first circuit arranged to receive a first set of the plurality of partial product term bits for the at least one compression column, the first circuit further arranged to combine the first set of term bits to produce a first combined term bit set; and a second circuit arranged to receive a second set of the plurality of term bits for the at least one compression column and all of the first combined term bit set.
    • 用于在乘法器电路中组合多个多位部分乘积项的组合电路包括多个压缩列,每列接收多个部分乘积项。 至少一个压缩列包括:第一电路,被布置为接收用于所述至少一个压缩列的多个部分乘积项中的第一组,所述第一电路还被布置为组合所述第一组术语位以产生第一组合 术语位设置; 以及第二电路,被布置为接收用于所述至少一个压缩列的所述多个术语比特的第二组以及所述第一组合项比特集合。
    • 6. 发明申请
    • Performing rounding in an arithmetic operation
    • 在算术运算中执行舍入
    • US20070043801A1
    • 2007-02-22
    • US11479933
    • 2006-06-30
    • Tariq KurdMark Homewood
    • Tariq KurdMark Homewood
    • G06F7/38
    • G06F7/5334G06F7/49947G06F7/49957G06F7/49963
    • An arithmetic unit comprising: an encoding circuit arranged to receive first and second operands each having a bit length of m bits and to generate therefrom a number n of partial products of varying bit length of m bits or less; an addition circuit having m columns each having n inputs, wherein bits of said partial products are applied to said inputs for combining said partial products into a result leaving certain of said inputs unused; and a rounding bit generator connected to supply a rounding bit to at least one of said unused inputs in one of said m columns at a bit position to cause said result to be rounded.
    • 一种算术单元,包括:编码电路,被配置为接收第一和第二操作数,每个操作数具有m位的位长度,并由其产生m位或更少的位长度变化的n个部分乘积; 具有m列的加法电路,每一列具有n个输入,其中所述部分乘积的位被施加到所述输入,用于将所述部分乘积组合成使得某些所述输入未被使用的结果; 以及一个四舍五入比特发生器,其连接以在位位置向所述m列中的一个列中的至少一个所述未使用的输入提供舍入位,以使所述结果舍入。