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1. 发明申请

US20070043801A1 Performing rounding in an arithmetic operation 有权
标题翻译：在算术运算中执行舍入
公开(公告)号：US20070043801A1
公开(公告)日：2007-02-22
申请号：US11479933
申请日：2006-06-30
申请人： Tariq Kurd , Mark Homewood
发明人： Tariq Kurd , Mark Homewood
IPC分类号： G06F7/38
CPC分类号： G06F7/5334 , G06F7/49947 , G06F7/49957 , G06F7/49963
摘要： An arithmetic unit comprising: an encoding circuit arranged to receive first and second operands each having a bit length of m bits and to generate therefrom a number n of partial products of varying bit length of m bits or less; an addition circuit having m columns each having n inputs, wherein bits of said partial products are applied to said inputs for combining said partial products into a result leaving certain of said inputs unused; and a rounding bit generator connected to supply a rounding bit to at least one of said unused inputs in one of said m columns at a bit position to cause said result to be rounded.
摘要翻译：一种算术单元，包括：编码电路，被配置为接收第一和第二操作数，每个操作数具有m位的位长度，并由其产生m位或更少的位长度变化的n个部分乘积; 具有m列的加法电路，每一列具有n个输入，其中所述部分乘积的位被施加到所述输入，用于将所述部分乘积组合成使得某些所述输入未被使用的结果; 以及一个四舍五入比特发生器，其连接以在位位置向所述m列中的一个列中的至少一个所述未使用的输入提供舍入位，以使所述结果舍入。

2. 发明申请

US20060277245A1 Multiply-accumulate unit and method of operation 有权
标题翻译：乘法累加单元和操作方法
公开(公告)号：US20060277245A1
公开(公告)日：2006-12-07
申请号：US11400020
申请日：2006-04-07
申请人： Tariq Kurd
发明人： Tariq Kurd
IPC分类号： G06F7/52
CPC分类号： G06F7/57 , G06F7/5443
摘要： An arithmetic unit for selectively implementing one of a multiply and multiply-accumulate instruction, including a multiplier, addition circuitry, a result register, and accumulator circuitry. The multiplier arranged to receive first and second operands and operable to generate multiplication terms. The addition circuitry for receiving multiplication terms from the multiplier and operable to combine them to generate a multiplication result. The result register for receiving the multiplication result from the adder. The accumulator circuitry connected to receive a value stored in the result register and an accumulate control signal which determines whether the arithmetic unit implements a multiply or a multiply-accumulate instruction.
摘要翻译：一种用于选择性地实现乘法和乘法累加指令之一的算术单元，包括乘法器，加法电路，结果寄存器和累加器电路。所述乘法器被布置为接收第一和第二操作数并可操作以产生乘法项。加法电路，用于从乘法器接收乘法项并且可操作以将它们组合以产生乘法结果。结果寄存器用于从加法器接收乘法结果。连接以接收存储在结果寄存器中的值的累加器电路和确定算术单元是否执行乘法或乘法累加指令的累加控制信号。

3. 发明授权

US08099450B2 Multiplication circuitry 有权
标题翻译：乘法电路
公开(公告)号：US08099450B2
公开(公告)日：2012-01-17
申请号：US11490475
申请日：2006-07-20
申请人： Tariq Kurd
发明人： Tariq Kurd
IPC分类号： G06F7/52
CPC分类号： G06F7/5318
摘要： Combining circuitry for combining a plurality of multi-bit partial product terms in a multiplier circuit includes a plurality of compression columns, each column receiving a plurality of partial product term bits. At least one compression column includes: a first circuit arranged to receive a first set of the plurality of partial product term bits for the at least one compression column, the first circuit further arranged to combine the first set of term bits to produce a first combined term bit set; and a second circuit arranged to receive a second set of the plurality of term bits for the at least one compression column and all of the first combined term bit set.
摘要翻译：用于在乘法器电路中组合多个多位部分乘积项的组合电路包括多个压缩列，每列接收多个部分乘积项。至少一个压缩列包括：第一电路，被布置为接收用于所述至少一个压缩列的多个部分乘积项中的第一组，所述第一电路还被布置为组合所述第一组术语位以产生第一组合术语位设置; 以及第二电路，被布置为接收用于所述至少一个压缩列的所述多个术语比特的第二组以及所述第一组合项比特集合。

4. 发明授权

US07840628B2 Combining circuitry 有权
标题翻译：组合电路
公开(公告)号：US07840628B2
公开(公告)日：2010-11-23
申请号：US11400041
申请日：2006-04-07
申请人： Tariq Kurd
发明人： Tariq Kurd
IPC分类号： G06F7/52
CPC分类号： G06F7/4876 , G06F7/5318
摘要： A combining circuit and method combines a plurality of terms in a multiplier circuit. The combining circuit includes a first circuit, arranged to receive a first set of the plurality of terms and to combine the first set of terms to produce a first combined term set. The combining circuit also includes a second circuit, arranged to receive a second set of the plurality of terms and to combine the second set of terms to produce a second combined term set. The combining circuit further includes a third circuit, arranged to receive the first and second combined term sets and to combine the first and second combined term sets to produce a third combined term set. The combining circuit outputs the first combined term set as a first combination result and the third combined term set as a second combination result.
摘要翻译：组合电路和方法在乘法器电路中组合多个项。组合电路包括第一电路，被布置成接收多个项的第一组并且组合第一组项以产生第一组合项集合。组合电路还包括第二电路，被布置成接收多个项的第二组，并且组合第二组项以产生第二组合项集合。组合电路还包括第三电路，其被布置为接收第一和第二组合项集合，并且组合第一和第二组合项集合以产生第三组合项集合。组合电路将第一组合项集合作为第一组合结果输出，并将第三组合项集合作为第二组合结果输出。

5. 发明申请

US20060277242A1 Combining circuitry 有权
标题翻译：组合电路
公开(公告)号：US20060277242A1
公开(公告)日：2006-12-07
申请号：US11400041
申请日：2006-04-07
申请人： Tariq Kurd
发明人： Tariq Kurd
IPC分类号： G06F7/38
CPC分类号： G06F7/4876 , G06F7/5318
摘要： A combining circuit and method combines a plurality of terms in a multiplier circuit. The combining circuit includes a first circuit, arranged to receive a first set of the plurality of terms and to combine the first set of terms to produce a first combined term set. The combining circuit also includes a second circuit, arranged to receive a second set of the plurality of terms and to combine the second set of terms to produce a second combined term set. The combining circuit further includes a third circuit, arranged to receive the first and second combined term sets and to combine the first and second combined term sets to produce a third combined term set. The combining circuit outputs the first combined term set as a first combination result and the third combined term set as a second combination result.
摘要翻译：组合电路和方法在乘法器电路中组合多个项。组合电路包括第一电路，被布置成接收多个项的第一组并且组合第一组项以产生第一组合项集合。组合电路还包括第二电路，被布置成接收多个项的第二组，并且组合第二组项以产生第二组合项集合。组合电路还包括第三电路，其被布置为接收第一和第二组合项集合，并且组合第一和第二组合项集合以产生第三组合项集合。组合电路将第一组合项集合作为第一组合结果输出，并将第三组合项集合作为第二组合结果输出。

6. 发明授权

US08751797B2 Integrated circuit with restricted data access 有权
标题翻译：具有受限数据访问的集成电路
公开(公告)号：US08751797B2
公开(公告)日：2014-06-10
申请号：US12082046
申请日：2008-04-07
申请人： Paul Elliott , Tariq Kurd
发明人： Paul Elliott , Tariq Kurd
IPC分类号： H04L29/06
CPC分类号： G06F12/1441 , G06F12/145 , G06F12/1483
摘要： A semiconductor integrated circuit includes a hardware mechanism arranged to ensure that associations between instructions and data are enforced so that a processor cannot fetch data from an instruction that is not authorized to do so. A Memory Protection Unit stores entries comprising instructions and associated data memory ranges. A hardware arrangement impairs the operation of the circuit if the processor attempts to make a data fetch from an instruction that is outside the range associated with data in a Memory Protection Unit. Such functioning may be by issuing a chip reset. The Memory Protection Unit may be implemented in a Memory Management Unit having an extension so as to store a validity flag. The validity flag may only be set by a secure process such as the CPU well entrusted code or by a separate trusted hardware source.
摘要翻译：半导体集成电路包括硬件机制，其被配置为确保指令和数据之间的关联被强制执行，使得处理器不能从未被授权的指令获取数据。存储器保护单元存储包括指令和相关数据存储器范围的条目。如果处理器尝试从与存储器保护单元中的数据相关联的范围之外的指令进行数据取出，则硬件布置会损害电路的操作。这种功能可能是通过发出芯片复位。存储器保护单元可以在具有扩展的存储器管理单元中实现，以便存储有效性标志。有效性标志只能通过诸如CPU良好委托的代码或单独的可信硬件源之类的安全处理来设置。

7. 发明授权

US07730118B2 Multiply-accumulate unit and method of operation 有权
标题翻译：乘法累加单元和操作方法
公开(公告)号：US07730118B2
公开(公告)日：2010-06-01
申请号：US11400020
申请日：2006-04-07
申请人： Tariq Kurd
发明人： Tariq Kurd
IPC分类号： G06F7/38
CPC分类号： G06F7/57 , G06F7/5443
摘要： An arithmetic unit for selectively implementing one of a multiply and multiply-accumulate instruction, including a multiplier, addition circuitry, a result register, and accumulator circuitry. The multiplier arranged to receive first and second operands and operable to generate multiplication terms. The addition circuitry for receiving multiplication terms from the multiplier and operable to combine them to generate a multiplication result. The result register for receiving the multiplication result from the adder. The accumulator circuitry connected to receive a value stored in the result register and an accumulate control signal which determines whether the arithmetic unit implements a multiply or a multiply-accumulate instruction.
摘要翻译：一种用于选择性地实现乘法和乘法累加指令之一的算术单元，包括乘法器，加法电路，结果寄存器和累加器电路。所述乘法器被布置为接收第一和第二操作数并可操作以产生乘法项。加法电路，用于从乘法器接收乘法项并且可操作以将它们组合以产生乘法结果。结果寄存器用于从加法器接收乘法结果。连接以接收存储在结果寄存器中的值的累加器电路和确定算术单元是否执行乘法或乘法累加指令的累加控制信号。

8. 发明授权

US07167887B2 Circuitry for carrying out square root and division operations 有权
标题翻译：电路进行平方根和除法运算
公开(公告)号：US07167887B2
公开(公告)日：2007-01-23
申请号：US10291218
申请日：2002-11-08
申请人： Tariq Kurd
发明人： Tariq Kurd
IPC分类号： G06F7/38 , G06F7/52
CPC分类号： G06F7/535 , G06F7/5525
摘要： The invention provides circuitry for carrying out a square root operation and a division operation. The circuitry utilizes common iteration circuitry for carrying out a plurality of iterations and means for identifying if an square root operation or a division operation is to be performed. The iteration circuitry is controlled in accordance with whether a square root or division operation is to be performed.
摘要翻译：本发明提供了用于执行平方根操作和分割操作的电路。该电路利用公共迭代电路进行多个迭代，以及用于识别是否要执行平方根操作或除法运算的装置。根据是否要执行平方根或除法运算来控制迭代电路。

9. 发明申请

US20060277246A1 Multiplication circuitry 审中-公开
标题翻译：乘法电路
公开(公告)号：US20060277246A1
公开(公告)日：2006-12-07
申请号：US11400753
申请日：2006-04-07
申请人： Tariq Kurd
发明人： Tariq Kurd
IPC分类号： G06F7/52
CPC分类号： G06F7/4876
摘要： A multiplier circuit multiplies a first and a second operand. The circuit includes a sectioning circuit arranged to section the first operand into a first number of parts and a multiplier arranged to receive the second operand and a second number of the first number of parts. The multiplier is further arranged to generate only a second number of product terms, each product term being one of the second number of parts multiplied by the second operand.
摘要翻译：乘法器电路将第一和第二操作数相乘。该电路包括分段电路，该分段电路被布置为将第一操作数分成第一数目的部分，以及乘法器，被布置为接收第二操作数和第二数量的第一数目的部分。乘法器还被布置成仅产生第二数量的乘积项，每个乘积项是第二数量的乘积乘以第二操作数之一。

10. 发明授权

US08209486B2 Cache memory 有权
标题翻译：高速缓存存储器
公开(公告)号：US08209486B2
公开(公告)日：2012-06-26
申请号：US12217119
申请日：2008-07-01
申请人： Tariq Kurd
发明人： Tariq Kurd
IPC分类号： G06F12/08
CPC分类号： G06F12/0886 , G06F9/3802 , G06F9/3814 , Y02D10/13
摘要： A cache memory comprises a first set of storage locations for holding syllables and addressable by a first group of addresses; a second set of storage locations for holding syllables and addressable by a second group of addresses; addressing circuitry operable to provide in each addressing cycle a pair of addresses comprising one from the first group and one from the second group, thereby accessing a plurality of syllables from each set of storage locations; and selection circuitry operable to select from said plurality of syllables to output to a processor lane based on whether a required syllable is addressable by an address in the first or second group.
摘要翻译：缓存存储器包括用于保存音节并由第一组地址寻址的第一组存储位置; 用于保存音节并由第二组地址寻址的第二组存储位置; 寻址电路，其可操作以在每个寻址周期中提供一对地址，其包括来自所述第一组和所述第二组中的一个，从而从每组存储位置访问多个音节; 以及选择电路，其可操作以基于所述第一组或第二组中的地址是否可寻址所需音节，从所述多个音节中选择输出到处理器通道。

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