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1. 发明申请

US20160036332A1 CONTROL APPARATUS, BUCK-BOOST POWER SUPPLY AND CONTROL METHOD 有权
标题翻译：控制装置，升压电源和控制方法
公开(公告)号：US20160036332A1
公开(公告)日：2016-02-04
申请号：US14447688
申请日：2014-07-31
申请人： Spansion LLC
发明人： Makoto YASHIKI , Toru Miyamae
IPC分类号： H02M3/158
CPC分类号： H02M3/1582 , H02M1/08 , H02M2001/0003 , H03K17/063 , H03K2217/0081
摘要： A control apparatus, a buck-boost power supply, and a control method that can control an output part comprising two primary switches which are N-type transistors without changing the switching frequency are provided. A control apparatus for a buck-boost power supply comprises: a pulse-width modulation (PWM) signal generator configured to generate a PWM signal having a pulse whose pulse width is based on an output voltage; a mode pulse signal generator configured to generate a mode pulse signal having a signal whose time period is based on at least one of an input voltage, a difference between an input voltage and the output voltage, and a difference between an input voltage and a voltage proportional to the output voltage; a first delayed signal generator configured to generate a first delayed signal having a pulse whose rising edge or falling edge is delayed for a first delay time from a rising edge or a falling edge of the pulse of the PWM signal; and an output controller configured to control an output part of the buck-boost power supply, based on the PWM signal, the mode pulse signal, and the first delayed signal, the output part comprising: two primary switches that are each an N-type transistor; a boost capacitor for driving the high-side switch of the primary switches; and two secondary switches that are each a transistor, wherein the output controller controls switching of the output part so that a first time period during which the high-side switch of the primary switches is off and the low-side switch of the primary switches is on is longer than or equal to the first delay time.
摘要翻译：提供一种控制装置，降压 - 升压电源和控制方法，其可以控制包括作为N型晶体管的两个初级开关的输出部分而不改变开关频率。一种用于降压 - 升压电源的控制装置，包括：脉冲宽度调制（PWM）信号发生器，被配置为产生具有脉冲宽度基于输出电压的脉冲的PWM信号; 模式脉冲信号发生器，其被配置为产生具有其时间周期基于输入电压，输入电压和输出电压之间的差异以及输入电压和电压之间的差异中的至少一个的信号的模式脉冲信号与输出电压成比例; 第一延迟信号发生器，被配置为产生具有脉冲的第一延迟信号，其上升沿或下降沿从PWM信号的脉冲的上升沿或下降沿延迟第一延迟时间; 以及输出控制器，其被配置为基于所述PWM信号，所述模式脉冲信号和所述第一延迟信号来控制所述降压升压电源的输出部分，所述输出部分包括：两个主开关，每个为N型晶体管用于驱动主开关的高侧开关的升压电容器; 以及两个各自为晶体管的次级开关，其中输出控制器控制输出部分的切换，使得初级开关的高侧开关关闭的第一时间段和主开关的低侧开关为 on长于或等于第一个延迟时间。

2. 发明申请

US20150262838A1 Buried Trench Isolation in Integrated Circuits 有权
标题翻译：集成电路埋藏沟槽隔离
公开(公告)号：US20150262838A1
公开(公告)日：2015-09-17
申请号：US14207303
申请日：2014-03-12
申请人： Spansion LLC
发明人： Rinji Sugino , Lei Xue , Ching-Huang Lu , Simon Chan
IPC分类号： H01L21/324 , H01L21/762 , H01L29/06 , H01L21/764
CPC分类号： H01L29/0649 , H01L21/3247 , H01L21/76224 , H01L21/764 , H01L29/0684 , H01L29/161
摘要： A system and method for providing electrical isolation between closely spaced devices in a high density integrated circuit (IC) are disclosed herein. An integrated circuit (IC) comprising a substrate, a first device, a second device, and a buried trench in the substrate and a method of fabricating the same are also discussed. The buried trench is positioned between first and second devices and may be filled with dielectric material. Alternatively, the buried trench contains air. A method of using Hydrogen annealing to create the buried trench is disclosed.
摘要翻译：本文公开了一种用于在高密度集成电路（IC）中的紧密间隔的器件之间提供电隔离的系统和方法。还讨论了包括衬底中的衬底，第一器件，第二器件和埋入沟槽的集成电路（IC）及其制造方法。埋置的沟槽位于第一和第二器件之间，并且可以用电介质材料填充。或者，埋入的沟槽包含空气。公开了一种使用氢退火来形成埋入沟槽的方法。

3. 发明授权

US09081710B2 Restoring ECC syndrome in non-volatile memory devices 有权
标题翻译：在非易失性存储器件中恢复ECC综合征
公开(公告)号：US09081710B2
公开(公告)日：2015-07-14
申请号：US13860542
申请日：2013-04-11
申请人： SPANSION LLC
发明人： Ilan Bloom , Amichai Givant , Yoav Yogev , Amit Shefi
IPC分类号： H03M13/00 , G06F11/10
CPC分类号： G06F11/1068 , G06F3/0619 , G06F3/064 , G06F3/0644 , G06F3/0652 , G06F3/0679 , G06F11/1052 , G11C29/52
摘要： A method of restoring an ECC syndrome in a non-volatile memory device having memory cells arranged in a plurality of sectors within a memory cell array, the method comprising identifying a first sector including at least one page having a disabled ECC (error correction code) flag; reading the value of all data bits in said at least one page; calculating values for ECC bits in said at least one page; and writing said data bit values and said calculated ECC bit values to a second sector in the memory cell array.
摘要翻译：一种在具有布置在存储单元阵列内的多个扇区中的存储器单元的非易失性存储器件中恢复ECC校正器的方法，所述方法包括：识别包括具有禁用的ECC（纠错码）的至少一个页面的第一扇区，旗; 读取所述至少一个页面中的所有数据位的值; 计算所述至少一页中的ECC位的值; 以及将所述数据位值和所述计算的ECC位值写入存储单元阵列中的第二扇区。

4. 发明申请

US20150162226A1 Forming Charge Trap Separation in a Flash Memory Semiconductor Device 审中-公开
标题翻译：在闪存半导体器件中形成电荷陷阱分离
公开(公告)号：US20150162226A1
公开(公告)日：2015-06-11
申请号：US14626815
申请日：2015-02-19
申请人： Spansion LLC
发明人： Angela Tai HUI
IPC分类号： H01L21/67
CPC分类号： H01L21/67207 , H01L21/6719 , H01L27/11568 , H01L29/40117 , H01L29/4234
摘要： During formation of a charge trap separation in a semiconductor device, a polymer deposition is formed in a reactor using a first chemistry. In a following step, a second chemistry can be used to etch the polymer deposition in the reactor. The same or similar second chemistry can be used in a second etching step to expose a first oxide layer in each of the cells of the semiconductor device and to form a flat upper surface. This additional etch step can also be performed by the reactor, thereby reducing the number of machines required in the formation process.
摘要翻译：在半导体器件中形成电荷陷阱分离期间，在反应器中使用第一化学形成聚合物沉积。在随后的步骤中，可以使用第二化学物质来蚀刻反应器中的聚合物沉积。可以在第二蚀刻步骤中使用相同或相似的第二化学物质来暴露半导体器件的每个单元中的第一氧化物层并形成平坦的上表面。这个额外的蚀刻步骤也可以由反应器进行，从而减少形成过程中所需要的机器的数量。

5. 发明申请

US20150109594A1 Multiple Phase-Shift Photomask and Semiconductor Manufacturing Method 有权
标题翻译：多相移光掩模和半导体制造方法
公开(公告)号：US20150109594A1
公开(公告)日：2015-04-23
申请号：US14056547
申请日：2013-10-17
申请人： Spansion LLC
发明人： Gong CHEN , Frank Tsai
IPC分类号： G03F7/20 , G03F1/26
CPC分类号： G03F7/70283 , G03F1/26 , G03F1/70 , G03F7/2012 , G03F7/70191 , G03F7/70433
摘要： Manufacturing of semiconductor devices often involves performed photolithography to pattern and etch the various features of those devices. Such photolithography involves masking and focusing light onto a surface of the semiconductor device for exposing and etching the features of the semiconductor devices. However, due to design specifications and other causes, the semiconductor devices may not have a perfectly flat light-incident surface. Rather, some areas of the semiconductor device may be raised or lowered relative to other areas of the semiconductor device. Therefore, focusing the light on one area causes another to become unfocused. By carefully designing a photomask to cause phase shifts of the light transmitted therethrough, focus across all areas of the semiconductor device can be achieved during photolithography, which results in sharp and accurate patterns formed on the semiconductor device.
摘要翻译：半导体器件的制造通常涉及进行的光刻以图案化和蚀刻这些器件的各种特征。这种光刻术涉及将光掩蔽并聚焦到半导体器件的表面上，用于暴露和蚀刻半导体器件的特征。然而，由于设计规格和其它原因，半导体器件可能没有完全平坦的光入射表面。相反，半导体器件的一些区域可以相对于半导体器件的其它区域升高或降低。因此，将光聚焦在一个区域会导致另一个区域变得不专心。通过仔细地设计光掩模以引起透射的光的相移，可以在光刻期间实现半导体器件的所有区域的聚焦，这导致形成在半导体器件上的尖锐和精确的图案。

6. 发明申请

US20150106405A1 HIDDEN MARKOV MODEL PROCESSING ENGINE 有权
标题翻译： HIDDEN MARKOV模型加工发动机
公开(公告)号：US20150106405A1
公开(公告)日：2015-04-16
申请号：US14054884
申请日：2013-10-16
申请人： Spansion LLC
发明人： Ojas BAPAT , Richard Fastow , Jens Olson , Kenichi Kumatani
IPC分类号： G06F17/30
CPC分类号： G06F17/30587 , G06F17/30536 , G10L15/14 , G10L15/142 , G10L15/30
摘要： A method, apparatus, and tangible computer readable medium for processing a Hidden Markov Model (HMM) structure are disclosed herein. For example, the method includes receiving Hidden Markov Model (HMM) information from an external system. The method also includes processing back pointer data and first HMM states scores for one or more NULL states in the HMM information. Second HMM state scores are processed for one or more non-NULL states in the HMM information based on at least one predecessor state. Further, the method includes transferring the second HMM state scores to the external system.
摘要翻译：本文公开了一种用于处理隐马尔可夫模型（HMM）结构的方法，装置和有形计算机可读介质。例如，该方法包括从外部系统接收隐马尔可夫模型（HMM）信息。该方法还包括处理HMM信息中的一个或多个NULL状态的反指针数据和第一HMM状态得分。基于至少一个前身状态，HMM信息中的一个或多个非空状态的第二HMM状态得分被处理。此外，该方法包括将第二HMM状态得分传送到外部系统。

7. 发明申请

US20150103601A1 MULTI-PASS SOFT PROGRAMMING 有权
标题翻译：多通软件编程
公开(公告)号：US20150103601A1
公开(公告)日：2015-04-16
申请号：US14050490
申请日：2013-10-10
申请人： Spansion LLC
发明人： Gulzar A. KATHAWALA , Mark W. RANDOLPH , Yi HE , Zhizheng LIU , Tio Wei NEO , Cindy SUN , Shivananda SHETTY , Phuog BANH , Richard FASTOW , Loi LA , Harry Hao KUO
IPC分类号： G11C16/12 , G11C16/34
CPC分类号： G11C16/12 , G11C16/10 , G11C16/3409 , G11C16/3413 , G11C16/3459
摘要： Disclosed herein are system, method and computer program product embodiments for utilizing soft programming a nonvolatile memory. An embodiment operates by sequentially applying a single soft programming voltage pulse to all memory cells along each word line in the nonvolatile memory that fail soft programming verification in a first phase. This sequential application of the single soft programming voltage pulse in the first phase may repeat a predetermined number of times or until a threshold is met. Once the predetermined number of times completes, or the threshold is met, soft programming proceeds to a second phase where soft programming remains with each word line until all memory cells along the word line passes soft programming verification.
摘要翻译：这里公开了用于利用软编程非易失性存储器的系统，方法和计算机程序产品实施例。实施例通过对在第一阶段中软编程验证失败的非易失性存储器中的每个字线向所有存储器单元顺序施加单个软编程电压脉冲来操作。第一阶段中单个软编程电压脉冲的这种顺序应用可以重复预定次数或直到满足阈值。一旦预定次数完成或者阈值被满足，则软编程进行到第二阶段，其中软编程保留在每个字线上，直到沿着字线的所有存储单元通过软编程验证。

8. 发明授权

US08995201B1 Methods circuits apparatuses and systems for sensing a logical state of a non-volatile memory cell and non-volatile memory devices produced accordingly 有权
标题翻译：方法用于感测非易失性存储器单元和非易失性存储器件的逻辑状态的电路装置和系统相应地产生
公开(公告)号：US08995201B1
公开(公告)日：2015-03-31
申请号：US14073914
申请日：2013-11-07
申请人： Spansion LLC
发明人： Alexander Kushnarenko , Yoram Betser
IPC分类号： G11C16/06 , G11C16/28
CPC分类号： G11C16/28 , G11C16/0483 , G11C16/3454
摘要： Disclose is a non-volatile memory (NVM) cell sensing circuit. The sensing circuit may include a sense-side-line conditioning circuit segment adapted to condition a sense-side-line of the NVM cell. Conditioning may include adjusting a charge density within the NVM cell sense-side-line during a first NVM cell current sensing phase. The conditioning circuit segment may also be adapted to maintain an NVM cell current sensing condition during a second NVM cell current sensing phase. Adjusting a charge density within the NVM cell sense-side-line may include inducing current in the sense-side-line in a direction opposite to the sensing current.
摘要翻译： Disclose是一种非易失性存储器（NVM）单元感测电路。感测电路可以包括适于调节NVM单元的感测侧线的感测侧线路调理电路段。调节可以包括在第一NVM单元电流感测阶段期间调整NVM单元感测侧线中的电荷密度。调理电路段还可以适于在第二NVM电池电流感测阶段期间维持NVM电池电流感测条件。调整NVM单元感测侧线内的电荷密度可以包括在与感测电流相反的方向上在感测侧线中感应电流。

9. 发明授权

US08981823B1 Apparatus and method for smart VCC trip point design for testability 有权
标题翻译：智能VCC跳变点设计的设备和方法，用于可测试性
公开(公告)号：US08981823B1
公开(公告)日：2015-03-17
申请号：US13972008
申请日：2013-08-21
申请人： Spansion LLC
发明人： Hor Ching-Kooi , Teoh Boon-Weng , Ong Mee-Choo
IPC分类号： H03L7/00 , H03K3/012 , H03K5/24
CPC分类号： G01R19/16552 , G01R31/2856
摘要： An apparatus and method for testing is provided. An integrated circuit includes a comparison circuit that is arranged to trip based on a power supply signal reaching a trip point. The integrated circuit also includes an analog-to-digital converter that is arranged to convert the power supply signal into a digital signal. The integrated circuit also includes a storage component that stores a digital value associated with the digital signal, and provides the power supply value at an output pin of the integrated circuit. The integrated circuit includes a latch that is coupled between the analog-to-digital converter and the storage component. The latch is arranged to open when the comparison circuit trips, such that, when the comparison circuit trips, the storage component continues to store a digital value such that the digital value corresponds to the voltage associated with the power supply signal when the comparison circuit tripped.
摘要翻译：提供了一种用于测试的装置和方法。集成电路包括比较电路，该比较电路被布置为基于到达跳变点的电源信号跳闸。集成电路还包括被配置为将电源信号转换为数字信号的模数转换器。集成电路还包括存储与数字信号相关联的数字值的存储部件，并且在集成电路的输出引脚处提供电源值。集成电路包括耦合在模数转换器和存储部件之间的锁存器。当比较电路跳闸时，锁存器被布置成打开，使得当比较电路跳闸时，存储部件继续存储数字值，使得当比较电路跳闸时，数字值对应于与电源信号相关联的电压。

10. 发明申请

US20150056726A1 CHIP POSITIONING IN MULTI-CHIP PACKAGE 有权
标题翻译：芯片定位在多芯片包装中
公开(公告)号：US20150056726A1
公开(公告)日：2015-02-26
申请号：US14532039
申请日：2014-11-04
申请人： Spansion LLC
发明人： Sally FOONG , Sheshasayee GADDAMRAJA , Teoh Lai BENG , Lai Nguk CHIN , Suthakavatin AUNGKUL
IPC分类号： H01L25/00 , H01L25/065 , H01L23/544 , H01L23/00
CPC分类号： H01L25/50 , H01L21/77 , H01L23/544 , H01L24/48 , H01L24/73 , H01L24/85 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L2223/5442 , H01L2223/54426 , H01L2223/54486 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/48095 , H01L2224/48227 , H01L2224/48247 , H01L2224/73265 , H01L2224/8513 , H01L2225/06506 , H01L2225/0651 , H01L2225/06562 , H01L2225/06593 , H01L2924/00014 , H01L2924/14 , H01L2924/15311 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/05599
摘要： Embodiments of the present invention include a method for multi-chip packaging. For example, the method includes positioning a first integrated circuit (IC) on a substrate package based on a first set of reference markers in physical contact with the substrate package and confirming an alignment of the first IC based on a second set of reference markers in physical contact with the substrate package. A second IC is stacked onto first IC based on the first set of reference markers. An alignment of the second IC is confirmed based on the second set of reference markers, where the second set of reference markers is disposed at a different location on the substrate package than the first set of reference markers.
摘要翻译：本发明的实施例包括一种用于多芯片封装的方法。例如，该方法包括基于与衬底封装物理接触的第一组参考标记物将第一集成电路（IC）定位在衬底封装上，并基于第二组参考标记确认第一IC的对准与基板封装物理接触。基于第一组参考标记将第二IC堆叠到第一IC上。基于第二组参考标记来确认第二IC的对准，其中第二组参考标记布置在衬底封装上与第一组参考标记不同的位置处。

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