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1. 发明申请

US20160049416A1 INTEGRATION OF SEMICONDUCTOR MEMORY CELLS AND LOGIC CELLS 有权
标题翻译：半导体记忆细胞和逻辑细胞的整合
公开(公告)号：US20160049416A1
公开(公告)日：2016-02-18
申请号：US14458542
申请日：2014-08-13
申请人： Cypress Semiconductor Corporation
发明人： Kimihiko HOSAKA , Toru Anezaki
IPC分类号： H01L27/115 , H01L21/28
CPC分类号： H01L27/11524 , H01L21/28008 , H01L27/11529 , H01L27/11536 , H01L29/66545
摘要： A polysilicon gate electrode is formed in a memory cell area, and a dummy polysilicon gate electrode is formed in a logic cell area of a silicon substrate. The dummy polysilicon gate electrode is removed and a gate insulation film and a metal gate electrode having a recess portion are formed. Further, contact holes are formed on source regions and drain regions of the memory cell area and the logic cell area. The recess portion of the metal gate electrode and the contact holes are filled with a wiring metal, substantially simultaneously, and thereafter the wiring metal is planarized by polishing.
摘要翻译：在存储单元区域中形成多晶硅栅电极，在硅衬底的逻辑单元区域中形成虚设多晶硅栅电极。除去虚设多晶硅栅电极，形成具有凹部的栅极绝缘膜和金属栅电极。此外，在存储单元区域和逻辑单元区域的源极区域和漏极区域上形成接触孔。金属栅电极的凹部和接触孔基本上同时被布线金属填充，然后通过研磨将布线金属平坦化。

2. 发明申请

US20160026593A1 DETECTING THE DRIFT OF THE DATA VALID WINDOW IN A TRANSACTION 审中-公开
标题翻译：检测数据有效窗口在交易中的移动
公开(公告)号：US20160026593A1
公开(公告)日：2016-01-28
申请号：US14339377
申请日：2014-07-23
申请人： Spansion LLC
发明人： Kai Dieffenbach , Uwe Moslehner , Jasmin Kotoric
IPC分类号： G06F13/40 , G06F9/46 , G06F1/08
CPC分类号： G06F13/4068 , G06F1/08 , G06F9/466 , H04L7/0033
摘要： Disclosed herein are system, apparatus, article of manufacture, method and/or computer program product embodiments for detecting the drift of the data valid window in a transaction. An embodiment operates by configuring a data capture range comprising data capture points, measuring values of a signal at the data capture points, and detecting the drift of the data valid window based on the values at the data capture points.
摘要翻译：本文公开了用于检测事务中的数据有效窗口漂移的系统，装置，制品，方法和/或计算机程序产品实施例。实施例通过配置数据捕获范围来进行操作，数据捕获范围包括数据捕获点，测量数据捕获点处的信号的值，以及基于数据捕获点处的值来检测数据有效窗口的漂移。

3. 发明申请

US20150378882A1 BOOTING AN APPLICATION FROM MULTIPLE MEMORIES 有权
标题翻译：从多个记忆中应用
公开(公告)号：US20150378882A1
公开(公告)日：2015-12-31
申请号：US14319079
申请日：2014-06-30
申请人： Spansion LLC
发明人： Stephan Rosner , Qamrul Hasan , Venkat Natarajan
IPC分类号： G06F12/02 , G06F9/54
CPC分类号： G06F12/023 , G06F9/4408 , G06F9/44573 , G06F2212/251
摘要： Disclosed herein are system, apparatus, article of manufacture, method and/or computer program product embodiments for booting an application from multiple memories. An embodiment operates by executing in place from a first memory a first portion of the application, loading a second portion of the application from a second memory, and executing the second portion of the application.
摘要翻译：本文公开了用于从多个存储器引导应用的系统，装置，制品，方法和/或计算机程序产品实施例。实施例通过从第一存储器执行应用的第一部分，从第二存储器加载应用的第二部分，以及执行应用的第二部分来进行操作。

4. 发明申请

US20150340098A1 METHODS, CIRCUITS, DEVICES AND SYSTEMS FOR SENSING AN NVM CELL 有权
标题翻译：方法，电路，用于感测NVM单元的设备和系统
公开(公告)号：US20150340098A1
公开(公告)日：2015-11-26
申请号：US14284632
申请日：2014-05-22
申请人： Spansion LLC
发明人： Eduardo Maayan , Yoram Betser , Alexander Kushnarenko
IPC分类号： G11C16/28
CPC分类号： G11C16/28 , G11C8/10 , G11C11/5642
摘要： Disclosed is a non-volatile memory (NVM) device including an array of NVM cells segmented into at least a first sector and a second sector and at least one sensing circuit to sense a state of a target NVM cell in the first sector using a reference current of the second sector received from at least a dynamic reference cell.
摘要翻译：公开了一种非易失性存储器（NVM）装置，其包括被分割成至少第一扇区和第二扇区的NVM单元的阵列和至少一个感测电路，以使用参考来感测第一扇区中的目标NVM单元的状态从至少动态参考单元接收的第二扇区的电流。

5. 发明申请

US20150333188A1 TILTED IMPLANT FOR POLY RESISTORS 审中-公开
标题翻译：用于聚电阻的倾斜植入物
公开(公告)号：US20150333188A1
公开(公告)日：2015-11-19
申请号：US14278114
申请日：2014-05-15
申请人： Spansion LLC
发明人： Shenqing FANG , Timothy Thurgate , Kuo Tung Chang
IPC分类号： H01L29/8605 , H01L21/265
CPC分类号： H01L21/26586 , H01L21/26513 , H01L28/20 , H01L29/8605
摘要： A semiconductor device having a substrate, a dielectric layer, a polycrystalline silicon (“poly”) resistor, a drain, and a source is disclosed. After implantation, the poly resistor may have a lateral doping profile with two peaks, one near each edge of the poly resistor, and a trough near the middle of the poly resistor. Such a doping profile can allow the poly resistor to have a resistance that is insensitive to small variations in critical dimension of the poly resistor. The resistance of the poly resistor may be determined by the doping dose of the tilted implant used to form the poly resistor. The tilted implant may be used to form the drain and the source of a transistor substantially simultaneously as forming the poly resistor.
摘要翻译：公开了具有基板，电介质层，多晶硅（“poly”）电阻，漏极和源极的半导体器件。在植入之后，多晶硅电阻器可以具有横向掺杂分布，其具有两个峰值，一个在多个电阻器的每个边缘附近，以及靠近该多个电阻器中间的槽。这种掺杂分布可以允许多晶硅电阻具有对聚电阻器的临界尺寸的小变化不敏感的电阻。多晶硅电阻器的电阻可以通过用于形成多晶硅电阻器的倾斜注入的掺杂剂量来确定。倾斜的植入物可以用于在形成多晶硅电阻器的同时基本上同时形成晶体管的漏极和源极。

6. 发明申请

US20150253988A1 Memory Access Bases on Erase Cycle Time 有权
标题翻译：内存访问基础擦除周期时间
公开(公告)号：US20150253988A1
公开(公告)日：2015-09-10
申请号：US14199837
申请日：2014-03-06
申请人： Spansion LLC
发明人： Mee-Choo ONG , Wei-Kent ONG , Ogiwara YUUSUKE , Sie-Wei Henry LAU
IPC分类号： G06F3/06
CPC分类号： G06F3/061 , G06F3/0659 , G06F3/0688 , G06F11/34 , G06F12/0246 , G06F2212/1028 , G06F2212/7204 , G06F2212/7207 , G06F2212/7211 , G11C16/14 , G11C16/20 , G11C16/28 , G11C16/32 , G11C16/349 , G11C16/3495
摘要： Disclosed herein are system, apparatus, article of manufacture, method and/or computer program product embodiments for improving a read margin in non-volatile semiconductor memory device. An embodiment includes measuring an erase-time of a memory block in a memory device and associating an indicator from the plurality Of indicators for the memory block. The indicator is saved and later retrieved during a read operation.
摘要翻译：本文公开了用于改善非易失性半导体存储器件中的读取余量的系统，装置，制品，方法和/或计算机程序产品实施例。一个实施例包括测量存储器件中的存储器块的擦除时间，并将存储器块的多个指示器中的指示符相关联。指示器在读取操作期间保存并稍后检索。

7. 发明申请

US20150194537A1 MULTI-LAYER INTER-GATE DIELECTRIC STRUCTURE 审中-公开
标题翻译：多层间栅电介质结构
公开(公告)号：US20150194537A1
公开(公告)日：2015-07-09
申请号：US14149628
申请日：2014-01-07
申请人： Spansion LLC
发明人： Chun CHEN , Shenqing Fang
IPC分类号： H01L29/792 , H01L21/311 , H01L29/51 , H01L21/28 , H01L29/66 , H01L29/423
CPC分类号： H01L29/792 , H01L29/40117 , H01L29/42344 , H01L29/66833
摘要： A semiconductor device having a first gate stack on a substrate is disclosed. The first gate stack may include a first gate conductor over a first gate dielectric structure. A dielectric structure can be formed over the first gate stack and the substrate. The dielectric structure layer can include four or more layers of two or more dielectric films disposed in an alternating manner. The dielectric structure can be selectively etched to form an inter-gate dielectric structure. A second gate conductor can be formed over a second gate dielectric structure, adjacent to the inter-gate dielectric structure. A dielectric layer can be formed over the substrate, the first and second gate conductors, and the inter-gate dielectric structure. The first gate conductor may be used to make a memory gate and the second gate conductor can be used to make a select gate of a split-gate memory cell.
摘要翻译：公开了一种在衬底上具有第一栅叠层的半导体器件。第一栅极堆叠可以包括在第一栅极电介质结构之上的第一栅极导体。可以在第一栅极堆叠和衬底上形成电介质结构。电介质结构层可以包括以交替方式设置的两个或更多个介电膜的四层或更多层。可以选择性地蚀刻电介质结构以形成栅极间电介质结构。第二栅极导体可以形成在与栅极间电介质结构相邻的第二栅极电介质结构上。可以在衬底，第一和第二栅极导体以及栅极间电介质结构之上形成电介质层。第一栅极导体可以用于制造存储器栅极，并且第二栅极导体可以用于形成分离栅极存储器单元的选择栅极。

8. 发明申请

US20150187891A1 Formation of Gate Sidewall Structure 有权
标题翻译：门侧壁结构的形成
公开(公告)号：US20150187891A1
公开(公告)日：2015-07-02
申请号：US14143317
申请日：2013-12-30
申请人： Spansion LLC
发明人： Rinji SUGINO , Scott BELL , Chun CHEN , Shenging FANG
IPC分类号： H01L29/40 , H01L29/423 , H01L29/51
CPC分类号： H01L29/401 , H01L21/28282 , H01L27/11568 , H01L29/42344 , H01L29/512 , H01L29/518 , H01L29/7833
摘要： A semiconductor device having a gate stack on a substrate is disclosed. The gate stack may include a mask layer disposed over a first gate conductor layer. The first gate conductor layer may be laterally etched beneath the mask layer to create an overhanging portion of the mask layer. A sidewall dielectric can be formed on the sidewall of the first gate conductor layer beneath the overhanging portion of the mask layer. A sidewall structure layer can be formed adjacent to the sidewall dielectric and beneath the overhanging portion of the mask layer. The mask layer can be removed. The first gate conductor layer can be used to form a memory gate and the sidewall structure layer can be used to form a select gate.
摘要翻译：公开了一种在衬底上具有栅叠层的半导体器件。栅极堆叠可以包括设置在第一栅极导体层上的掩模层。第一栅极导体层可以在掩模层下面被横向蚀刻，以形成掩模层的悬垂部分。可以在掩模层的伸出部分下方的第一栅极导体层的侧壁上形成侧壁电介质。侧壁结构层可以邻近于侧壁电介质并且在掩模层的悬垂部分下方形成。可以去除掩模层。第一栅极导体层可用于形成存储栅极，并且侧壁结构层可用于形成选择栅极。

9. 发明申请

US20150171100A1 PROCESS FOR FORMING EDGE WORDLINE IMPLANTS ADJACENT EDGE WORDLINES 有权
标题翻译：形成边缘字线的过程相似边缘词
公开(公告)号：US20150171100A1
公开(公告)日：2015-06-18
申请号：US14108780
申请日：2013-12-17
申请人： Spansion LLC
发明人： Timothy THURGATE , Yu SUN , Chun CHEN
IPC分类号： H01L27/115 , H01L21/265
CPC分类号： H01L21/26586 , H01L27/1157 , H01L29/66833
摘要： A process for forming tilted edge wordline implants is disclosed. The process includes forming a first drain implant in a substrate, forming a first tilted implant in a substrate adjacent a first edge wordline to supplement said first drain implant where the first tilted implant is provided at a tilt angle from a first direction and forming a second tilted implant in the substrate adjacent a second edge wordline to supplement another first drain implant where the second tilted implant is provided at a tilt angle from a second direction. A second drain implant is formed in the substrate.
摘要翻译：公开了一种用于形成倾斜边缘字线植入物的方法。该方法包括在衬底中形成第一漏极注入，在邻近第一边缘字线的衬底中形成第一倾斜注入，以补充所述第一漏极注入，其中第一倾斜植入物以与第一方向成倾斜角度形成，倾斜的植入物邻近第二边缘字线在衬底中以补充另一个第一漏极注入，其中第二倾斜植入物以与第二方向成倾斜角度设置。在衬底中形成第二漏极注入。

10. 发明申请

US20150155162A1 Reduction of Charging Induced Damage in Photolithography Wet Process 审中-公开
标题翻译：减少光刻湿法中的充电诱导损伤
公开(公告)号：US20150155162A1
公开(公告)日：2015-06-04
申请号：US14095150
申请日：2013-12-03
申请人： Spansion LLC
发明人： Daniel E. SUTTON , Christopher M. FOSTER , Kelley Kyle HIGGINS, SR. , Moutasim KHOGLY , Alexander J. BIERWAG , Daniel H. WILCOX
IPC分类号： H01L21/02 , H01L49/02
CPC分类号： H01L21/31111 , H01L21/0206 , H01L28/40
摘要： An approach is developed to use an acidic rinse to reduce charge during the lithographic process, and thereby eliminate the crystalline damage and associated yield loss associated with the accumulated charge. The crystalline damage has been found to occur for certain thicknesses of dielectric layers, and such damage is irreparable. A sparge can be used to dissolve carbon dioxide in water to provide a weak acidic rinse.
摘要翻译：开发了一种方法来使用酸性漂洗在光刻过程中减少电荷，从而消除与累积电荷相关的结晶损伤和相关的产量损失。已经发现，对于某些厚度的介电层，会发生结晶损伤，这种损伤是不可修复的。喷雾可用于将二氧化碳溶解在水中以提供弱酸性漂洗。

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